CN106024730B - Semiconductor package and method of manufacturing the same - Google Patents

Abstract

A semiconductor package and a manufacturing method thereof. The semiconductor package comprises a substrate, a signal contact, a semiconductor chip, a package body, a ground layer and a dielectric layer. The semiconductor chip is arranged on the substrate. The package body covers the semiconductor chip and has an upper surface and a signal groove, wherein the signal groove extends from the upper surface of the package body to the signal contact. The ground layer is formed on the inner side wall of the signal groove. The dielectric layer is formed in the signal groove.

Description

Semiconductor package and method of manufacturing the same

This application is a divisional application of the invention patent application with the application number "201310109829.0" and the invention name "semiconductor package and its manufacturing method" submitted by the applicant on March 29, 2013.

technical field

The present invention relates to a semiconductor package and a manufacturing method thereof, and more particularly, to a semiconductor package having a signal groove and a manufacturing method thereof.

Background technique

Due to the demands of increasing process speed and downsizing, semiconductor devices have become very complex. As process speed increases and the benefits of small size increase significantly, the characteristics of semiconductor packages also present problems. In particular, a higher operating clock speed results in more frequent transitions between signal levels, thus resulting in reduced signal strength at high frequencies or at short wavelengths. Therefore, how to improve the weakening of high-frequency signal strength is one of the focuses of the industry.

SUMMARY OF THE INVENTION

The present invention relates to a semiconductor package and a manufacturing method thereof, which can reduce signal loss.

According to the present invention, a semiconductor package is proposed. The semiconductor package includes a substrate, a first signal contact, a semiconductor chip, a package body, a first ground layer and a dielectric layer. The semiconductor chip is arranged on the substrate. The package body covers the semiconductor chip and has an upper surface and a signal groove, and the signal groove extends from the upper surface of the package body to the first signal contact. The first ground layer is formed on the inner sidewall of the signal groove. A dielectric layer is formed in the signal groove.

According to the present invention, a method of manufacturing a semiconductor package is provided. The manufacturing method includes the following steps. A substrate is provided; a semiconductor chip is arranged on the substrate; a package body is formed to cover the semiconductor chip; a signal groove is formed to extend from the upper surface of the package body to a first signal contact; a first ground layer is formed in the signal groove on the inner sidewalls; and, forming a dielectric layer in the signal groove.

In order to make the above-mentioned content of the present invention more obvious and easy to understand, the following specific examples are given, and the accompanying drawings are described in detail as follows:

Description of drawings

FIG. 1A is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

FIG. 1B is a top view of FIG. 1A .

FIG. 2 is a top view of a semiconductor package according to another embodiment of the present invention.

3 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

4 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

5A illustrates a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

FIG. 5B is a top view of FIG. 5A .

6A illustrates a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

FIG. 6B is a top view of FIG. 6A .

7A illustrates a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

FIG. 7B is a bottom view of FIG. 7A .

8A illustrates a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

FIG. 8B is a bottom view of FIG. 8A .

FIG. 9 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

10 illustrates a cross-sectional view of a stacked semiconductor package according to another embodiment of the present invention.

11 illustrates a cross-sectional view of a stacked semiconductor package according to another embodiment of the present invention.

12A illustrates a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

FIG. 12B is a bottom view of the signal transmission element in FIG. 12A .

FIG. 13 is a bottom view of a signal transmission element according to another embodiment of the present invention.

FIG. 14 illustrates a bottom view of a signal transmission element according to another embodiment of the present invention.

FIG. 15 is a bottom view of a signal transmission element according to another embodiment of the present invention.

16 illustrates a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

17 illustrates a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

18A illustrates a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

18B illustrates a top view of a semiconductor package according to another embodiment of the present invention.

19A illustrates a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

FIG. 19B is a top view of FIG. 19A .

20 illustrates a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

21 illustrates a cross-sectional view of a semiconductor package according to another embodiment of the present invention.

22A to 22G are diagrams illustrating a manufacturing process of the semiconductor package of FIG. 5A .

23A to 23O are diagrams illustrating a manufacturing process of the semiconductor package of FIG. 12A.

24A to 24I are diagrams illustrating a manufacturing process of the semiconductor package of FIG. 20 .

25A to 25C are diagrams illustrating a manufacturing process of the semiconductor package of FIG. 21 .

Description of main component symbols:

100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1000, 1200, 1300, 1400, 1500, 1600, 1700: Semiconductor packages

110, 710, 810, 1210: Substrate

110b, 111b, 1210b: lower surface

110s, 140s, 1250s: outer side

110u, 111u, 1210u, 1250u, 1260u, 140u, 150u: Upper surface

111: Substrate

111h, 141h, 150h, 710h, 1210h: through hole

112: First composite layer

1121: circuit layer

1122: Dielectric Layer

1123: Conductive holes

1124: Ground Pad

113: Second composite layer

1132, 5722: Ground pad

120: The first signal contact

121, 1131, 5721: Signal pads

1211: Ground Point

1212: first conductive layer

1213: Second Conductive Layer

1250: Shield

1250h, 1260h: Opening

1260: Dielectric Layer

1270: Antenna Layer

1271: Feeds Department

1280, 1380: Signal transmission components

1281: Grounding Post

130: Semiconductor chip

131: Soldering Wire

130u: Active side

140: Package body

140r: Signal groove

140r1: Inside Wall

150: Dielectric layer

160, 360: first ground plane

161: Inside

162: Upper

163: Bottom

364: Outer part

570: First Signal Transmission Column

571: The first pad layer

572: Second pad layer

573: Partial Materials

620: Second signal contact

670: Second signal transmission column

714: Third Signal Transmission Column

715: Second ground plane

814: Fourth Signal Transmission Column

P1, P2: cutting path

Detailed ways

Please refer to FIG. 1A , which is a cross-sectional view of a semiconductor package according to an embodiment of the present invention. The semiconductor package 100 includes a substrate 110 , a first signal contact 120 , a semiconductor chip 130 , a package body 140 , a dielectric layer 150 and a first ground layer 160 . Although not shown, the semiconductor package 100 further includes at least one passive element, such as a resistor, a capacitor or an inductor.

The substrate 110 includes a substrate 111 , a first composite layer 112 and a second composite layer 113 , wherein the first composite layer 112 and the second composite layer 113 are respectively formed on the upper surface 111u and the lower surface 111b of the substrate 111 . The substrate 111 is, for example, a BT substrate, a glass substrate, a dielectric substrate, or other suitable substrates. The first composite layer 112 includes at least one circuit layer 1121 , at least one dielectric layer 1122 and at least one conductive via 1123 , wherein the dielectric layer 1122 electrically isolates two adjacent circuit layers 1121 and two adjacent circuit layers 1121 can be electrically connected through corresponding conductive holes 1123 . The structure of the second composite layer 113 may be similar to that of the first composite layer 112 , and details are not described herein again.

The first signal contact 120 is formed on the upper surface 110 u of the substrate 110 , which may be a part of the circuit layer 1121 . The first signal contact 120 can be electrically connected to the semiconductor chip 130 through the circuit layer 1121 and the conductive hole 1123 , so that the signal can be transmitted between the first signal contact 120 and the semiconductor chip 130 . In addition, the semiconductor package 100 further includes signal pads 121 formed on the first signal pads 120 . The signal pads 121 and the first ground layer 160 can be formed at one time with the same material in the same process. In another example, the signal pads 121 can also be omitted.

The semiconductor chip 130 is, for example, a wireless signal transceiving chip or other types of chips, wherein the wireless signal transceiving chip is, for example, a radio frequency (Radio frequency, RF) chip. The semiconductor chip 130 is disposed on the upper surface 110u of the substrate 110 with the active surface 130u facing upward, and is electrically connected to the first composite layer 112 through at least one bonding wire 131 . The semiconductor chip 130 can be electrically connected to the first signal contact 120 through the bonding wires 131 and the circuit layer 1121 of the substrate 110 . In another example, the semiconductor chip 130 is, for example, a flip chip, which is disposed on the upper surface 110u of the substrate 110 with the active surface 130u facing downward, and is electrically connected to the first composite layer 112 through at least one solder ball.

The package body 140 is formed on the upper surface 110u of the substrate 110 and covers the semiconductor chip 130 . The package body 140 has an upper surface 140u and at least one signal groove 140r. The signal groove 140r extends from the upper surface 140u of the package body 140 to the first signal contacts 120 and the upper surface 110u of the substrate 110 to expose the first signal contacts 120 .

The package body 140 may include a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or other suitable capping agents. The package body 140 may also include a suitable filler, such as powdered silica. The package body 140 may be formed using several packaging techniques, such as compression molding, injection molding, or transfer molding.

Due to the removal of the package body material, the signal transmitted in the signal groove 140r will not be disturbed by the package body 140 . The dielectric layer 150 is selectively formed in the signal groove 140r, so as to improve the transmission of the signal in the signal groove 140r. For example, the dielectric layer 150 is a waveguide medium that can fill at least a portion of the signal groove 140r. Preferably, but not limitedly, the dielectric layer 150 may be made of a low-loss material. The external signal enters the dielectric layer 150 and conducts wave conduction in the dielectric layer 150, and then is transmitted to the semiconductor chip 130 through the first signal contact 120; or, the signal from the semiconductor chip 130 is transmitted to the dielectric layer 150 and then Waves are conducted in the dielectric layer 150 and then radiated from the dielectric layer 150 to the outside. Furthermore, even if the physical or mechanical conductive lines are omitted, the signal can still be conducted in the dielectric layer 150 between the first signal contact 120 and the upper surface 150u of the dielectric layer 150 due to the waveguide properties of the dielectric layer 150 . between.

The first ground layer 160 includes an inner side portion 161 formed on the inner sidewall 140r1 of the signal groove 140r. The inner portion 161 can confine the signal within the signal groove 140r to reduce signal loss or maintain signal strength. In addition, since the inner portion 161 can shield external electromagnetic interference, the signal transmitted in the signal groove 140r is less likely to be adversely affected. In addition, in this example, the inner portion 161 is a closed annular ground layer, which is formed around the inner sidewall 140r1 of the signal groove 140r in a closed manner; however, in another example, the inner portion 161 may be an open annular ground layer.

The first ground layer 160 further includes an upper portion 162 formed on the upper surface 140u of the package body 140 and extending between the signal groove 140r and the outer side surface 140s of the package body 140 . In this example, the first ground layer 160 extends to the outer side surface 140s of the package body 140 and is aligned with the outer side surface 140s of the package body 140 , eg, coplanar; however, it may not be aligned. In one example, the upper portion 162 can also cover the entire upper surface 140u of the package body 140 so as to completely overlap the semiconductor chip 130 up and down, thereby enhancing the technical effect of electromagnetic interference protection. In another example, the upper portion 162 of the first ground layer 160 may also be omitted.

The first ground layer 160 further includes a bottom portion 163 formed on the circuit layer 1121 of the substrate 110 . The bottom 163 is electrically connected to an external ground terminal (not shown) through the circuit layer 1121 , the conductive holes 1123 , the conductive holes 1111 of the substrate 111 and the second composite layer 113 , so that the first ground layer 160 is grounded. In another example, the bottom portion 163 of the first ground layer 160 may be omitted.

Please refer to FIG. 1B , which shows a top view of FIG. 1A . The cross-section of the signal groove 140r is, for example, a circle, which is not intended to limit the embodiments of the present invention. In another example, the cross-section of the signal groove 140r is oval or polygonal, and the polygon is, for example, a triangle, a rectangle or other polygons.

Please refer to FIG. 2 , which shows a top view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 200 includes a substrate 110 (not shown), a first signal contact 120 , a semiconductor chip 130 (not shown), a package body 140 , a dielectric layer 150 (not shown) and a first ground layer 160 .

In this example, the cross-sectional shape of the signal groove 140r of the package body 140 is a rectangle, but it can also be a polygon with other geometric shapes, such as a pentagon, a hexagon, and the like. The cross-sectional shape of the signal groove 140r is not particularly limited in the embodiment of the present invention.

Please refer to FIG. 3 , which is a cross-sectional view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 300 includes a substrate 110 , a first signal contact 120 , a semiconductor chip 130 , a package body 140 , a dielectric layer 150 and a first ground layer 360 .

The first ground layer 360 includes an inner portion 161 , an upper portion 162 , a bottom portion 163 and an outer portion 364 , wherein the outer portion 364 is formed on the outer side surface 140s of the package body 140 and the outer side surface 110s of the substrate 110 , and extends above the package body 140 . between the surface 140u and the lower surface 110b of the substrate 110 . In this example, the outer portion 364 extends from the upper surface 140u of the package body 140 to the lower surface 110b of the substrate 110 . The outer portion 364 covers the circuit layer 1121 on the outer side surface 110s of the substrate 110 , so as to be electrically connected to the external ground terminal through the circuit layer 1121 to ground the first ground layer 360 .

Please refer to FIG. 4 , which is a cross-sectional view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 400 includes a substrate 110 , a first signal contact 120 , a semiconductor chip 130 , a package body 140 , a dielectric layer 150 and a first ground layer 160 .

In this example, the first signal contact 120 is formed on the active surface 130u of the semiconductor chip 130 . The signal grooves 140r of the package body 140 extend from the upper surface 140u of the package body 140 to the first signal pads 120 formed on the semiconductor chip 130 to expose the first signal pads 120 . The dielectric layer 150 fills up at least a part of the signal groove 140r, and the signal can be wave-conducted in the dielectric layer 150 .

Please refer to FIG. 5A , which is a cross-sectional view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 500 includes a substrate 110 , a first signal contact 120 , a semiconductor chip 130 , a package body 140 , a dielectric layer 150 , a first ground layer 160 and a first signal transmission column 570 .

In this example, the dielectric layer 150 can be epoxy or a material similar to the package body 140 , which can fill the groove space between the first signal transmission pillar 570 and the first ground layer 160 . The inner portion 161 of the first ground layer 160 surrounds the first signal transmission column 570 and is arranged coaxially with the first signal transmission column 570 (Coaxial Via Structure, CVS); however, it can also be arranged coaxially. In this example, the inner portion 161 of the first ground layer 160 and the first signal transmission column 570 are located in the same lateral structure layer, so that no vertical space is occupied, that is, the first signal transmission column 570 does not increase the semiconductor The height of the package 100 .

The first signal transmission column 570 is, for example, a through molding via (TMV), which extends from the upper surface 150u of the dielectric layer 150 to the signal pads 121 and passes through the signal pads 121 , the first signal contacts 120 , The conductive hole 1123 and the circuit layer 1121 are electrically connected to the semiconductor chip 130 . In another example, the signal pads 121 may be omitted, so that the first signal transmission pillars 570 extend directly from the upper surface 150u of the dielectric layer 150 to the first signal pads 120 . By designing the outer diameter of the first signal transmission column 570, the inner diameter of the inner portion 161 of the first ground layer 160 and the dielectric coefficient of the dielectric layer 150, an impedance matching of about 50 ohms can be obtained, and the waveguide electromagnetic mode exceeds the desired The operating frequency is to avoid mode conversion; in another example, with proper design, the waveguide electromagnetic mode can exceed 70 GHz (the desired operating frequency), but can also be less than 70 GHz, such as between 40 GHz and 69 GHz.

Please refer to FIG. 5B , which shows the top view of FIG. 5A . In this example, the cross-sectional shape of the first signal transmission column 570 is circular, but it can also be an ellipse or a polygon, wherein the polygon is a triangle, a rectangle or other polygons.

Please refer to FIG. 6A , which is a cross-sectional view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 600 includes a substrate 110 , a first signal contact 120 , a second signal contact 620 , a semiconductor chip 130 , a package body 140 , a dielectric layer 150 , a first ground layer 160 , a first signal transmission column 570 and a second signal transmission Column 670. The semiconductor package 600 of this example is different from the semiconductor package 100 in that two signal transmission pillars are formed in a signal groove 140r, such as a first signal transmission pillar 570 and a second signal transmission pillar 670 .

The first signal contacts 120 and the second signal contacts 620 are both formed on the upper surface 110 u of the substrate 110 , which may be a part of the circuit layer 1121 of the substrate 110 . The material and structure of the second signal contact 620 may be similar to those of the first signal contact 120 , and details are not described herein again.

The dielectric layer 150 fills the groove space between the first signal transmission pillar 570 , the second signal transmission pillar 670 and the first ground layer 160 .

The second signal transmission pillars 670 are, for example, through-molded vias, which extend from the upper surface 150u of the dielectric layer 150 to the signal pads 121 and the upper surface 110u of the substrate 110 , and pass through the signal pads 121 , the second signal contacts 620 , The conductive hole 1123 and the circuit layer 1121 are electrically connected to the semiconductor chip 130 . In another example, the signal pads 121 may be omitted, so that the second signal transmission pillars 670 extend directly from the upper surface 150u of the dielectric layer 150 to the second signal pads 620 . The semiconductor chip 130 can control the phase difference of the signals transmitted to the first signal transmission column 570 and the second signal transmission column 670 by 180 degrees. In addition, the material and structure of the second signal transmission column 670 may be similar to the first signal transmission column 570 , and details are not described herein again.

Please refer to FIG. 6B, which shows the top view of FIG. 6A. In this example, the cross-sectional shape of the second signal transmission column 670 is circular, but it can also be an ellipse or a polygon, wherein the polygon is a triangle, a rectangle or other polygons. In addition, the cross-sectional shape of the signal groove 140r of the package body 140 is elliptical, but can also be a circle or a polygon, wherein the polygon is a triangle, a rectangle or other polygons.

Please refer to FIG. 7A , which is a cross-sectional view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 700 includes a substrate 710 , a first signal contact 120 , a semiconductor chip 130 and a package body 140 .

The substrate 710 includes a base material 111 , a first composite layer 112 and a second composite layer 113 , a third signal transmission column 714 and a second ground layer 715 and has at least a through hole 710h. The through hole 710h penetrates the entire thickness of the substrate 710 . The third signal transmission column 714 passes through the through hole 710h and extends to the first signal contact 120 , so that the semiconductor chip 130 can be electrically connected to an external circuit (not shown) through the first signal contact 120 and the third signal transmission column 714 ).

The second ground layer 715 is formed on the inner sidewall of the through hole 710h, the upper surface 111u and the lower surface 111b of the substrate 111, and is electrically connected to an external ground terminal (not shown) through the conductive hole 1123, so that the second ground Layer 715 is grounded. The technical effect of the second ground layer 715 is similar to that of the first ground layer 160 , and details are not described herein again.

Please refer to FIG. 7B, which shows a bottom view of FIG. 7A. The second composite layer 113 includes at least one signal pad 1131 and a plurality of ground pads 1132 . The signal pads 1131 are formed on the end surfaces of the third signal transmission pillars 714 , and the ground pads 1132 surround the signal pads 1131 separately from each other. . In addition, the cross-sectional shape of the through hole 710h is circular, but can also be an ellipse or a polygon, such as a triangle, a rectangle or other polygons.

Please refer to FIG. 8A , which is a cross-sectional view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 800 includes a substrate 810 , a first signal contact 120 , a semiconductor chip 130 and a package body 140 .

The substrate 810 includes a base material 111 , a first composite layer 112 and a second composite layer 113 , at least one third signal transmission column 714 , a second ground layer 715 and at least one fourth signal transmission column 814 and has at least a through hole 710h. The through hole 710h penetrates the entire thickness of the substrate 710 . The fourth signal transmission column 814 passes through the through hole 710h and extends to the first signal contact 120 so that the semiconductor chip 130 can be electrically connected to an external circuit (not shown) through the first signal contact 120 and the fourth signal transmission column 814 ).

The second ground layer 715 is formed on the inner sidewall of the through hole 710h and surrounds the third signal transmission column 714 and the fourth signal transmission column 814 .

Please refer to FIG. 8B, which shows a bottom view of FIG. 8A. The second composite layer 113 ( FIG. 8A ) includes a plurality of signal pads 1131 and a plurality of ground pads 1132 . The two signal pads 1131 are respectively formed on the end face of the third signal transmission column 714 and the end face of the fourth signal transmission column 814 . The ground pads 1132 surround the signal pads 1131 separately from each other. In addition, the cross-sectional shape of the through hole 710h is an ellipse, but it can also be a circle or a polygon, such as a triangle, a rectangle or other polygons.

Please refer to FIG. 9 , which is a cross-sectional view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 900 includes a substrate 710 , a first signal contact 120 , a semiconductor chip 130 , a package body 140 , a dielectric layer 150 , a first ground layer 160 and a first signal transmission pillar 570 .

The substrate 710 includes a base material 111 , a first composite layer 112 and a second composite layer 113 , a third signal transmission column 714 and a second ground layer 715 and has at least a through hole 710h. The through hole 710h penetrates the entire thickness of the substrate 710 . The third signal transmission column 714 passes through the through hole 710h and extends to the first signal contact 120 , so that the semiconductor chip 130 can be electrically connected to an external circuit (not shown) through the first signal contact 120 and the third signal transmission column 714 ).

The first signal transmission column 570 and the third signal transmission column 714 are electrically connected, so that signals can be transmitted between the semiconductor chip 130 , the first signal transmission column 570 and the third signal transmission column 714 . In this example, the first signal transmission column 570 is docked with the third signal transmission column 714 , that is, the first signal transmission column 570 and the third signal transmission column 714 are arranged in a straight line direction, so that the signal transmission path is the shortest. In another example, the first signal transmission column 570 and the third signal transmission column 714 can be staggered from left to right, and are electrically connected through the first composite layer 112 .

Please refer to FIG. 10 , which is a cross-sectional view of a stacked semiconductor package according to another embodiment of the present invention. The stacked semiconductor package 1000 includes two semiconductor packages 100 which are butted in an opposite manner with the signal grooves 140r, so that the signals between the two semiconductor packages 100 can be transmitted through the two opposite signal grooves 140r. Although not shown in the figure, a solder is included between the two semiconductor packages 100 to bond the two semiconductor packages 100 together.

Please refer to FIG. 11 , which is a cross-sectional view of a stacked semiconductor package according to another embodiment of the present invention. The stacked semiconductor package 1100 includes semiconductor packages 500 and 900 , wherein the first signal transmission column 570 of the semiconductor package 500 is docked with the third signal transmission column 714 of the semiconductor package 900 , so that the two semiconductor packages 500 and 900 are connected. Signals therebetween can be transmitted through the first signal transmission column 570 and the third signal transmission column 714 . In this example, the first signal transmission column 570 and the third signal transmission column 714 of the semiconductor package 900 and the first signal transmission column 570 of the semiconductor package 500 are arranged in a straight line direction, so that the signal transmission path is the shortest.

Although the stacked semiconductor packages in the above-mentioned embodiments are described by taking the stacking of the semiconductor packages 100 , 500 and 900 as an example, in another example, at least two of the semiconductor packages 100 to 900 may also be stacked on each other; or, Several identical semiconductor packages can also be stacked on top of each other.

Please refer to FIG. 12A , which is a cross-sectional view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 1200 includes a substrate 1210 , a first signal contact 120 , a semiconductor chip 130 , a package body 140 , a shielding layer 1250 , a dielectric layer 1260 , an antenna layer 1270 , a feed point 1271 and at least one signal transmission element 1280 .

The substrate 1210 is, for example, a multi-layer structure, which includes at least one circuit layer 1121 and at least one conductive hole 1123 . In another example, the substrate 1210 may be a single-layer structure. The substrate 1210 further includes at least one grounding point 1211 , which is formed on the upper surface 1210u of the substrate 1210 and is electrically connected to an external ground terminal (not shown) through the circuit layer 1121 and the conductive hole 1123 ; in another example, the grounding point 1211 may be It extends between the upper surface 1210u and the lower surface 1210b of the substrate 1210 .

The first signal contact 120 is formed on the substrate 1210 and is electrically connected to the semiconductor chip 130 through the circuit layer 1121 and the conductive hole 1123 of the substrate 1210 . The semiconductor chip 130 is disposed on the substrate 1210 and is electrically connected to the substrate 1210 through the bonding wires 131 .

The shielding layer 1250 is formed on the outer side surface 140s and the upper surface 140u of the package body 140 , and is electrically connected to the grounding point 1211 of the substrate 1210 to ground the shielding layer 1250 .

The material of the shielding layer 1250 is made of aluminum, copper, chromium, tin, gold, silver, nickel, stainless steel or a combination of the above materials, which can be applied such as chemical vapor deposition (Chemical Vapor Deposition, CVD), electroless plating (electrolessplating) , electroplating, printing (printing), spraying (spraying), sputtering or vacuum deposition (vacuum deposition) and other techniques.

The dielectric layer 1260 is formed of, for example, a low-loss, low-k material, such as Teflon, polytetrafluoroethylene (PTEE), and polystyrene. The dielectric layer 1260 covers the upper surface 1250u of the shielding layer 1250 and has at least one opening 1260h. The antenna layer 1270 is formed on the upper surface 1260u of the dielectric layer 1260 . The feeding part 1271 connects the antenna layer 1270 and the first signal transmission column 570 through the opening 1260h, so that the antenna layer 1270 can pass through the feeding part 1271, the first signal transmission column 570, the first signal contact 120, the circuit layer 1121, the conductive hole 1123 and the The bonding wires 131 are electrically connected to the semiconductor chip 130 .

The signal transmission element 1280 is electrically connected to the first signal contact 120 , and is electrically connected to the semiconductor chip 130 through the first signal contact 120 , the conductive hole 1123 , the circuit layer 1121 , and the bonding wire 131 .

The signal transmission element 1280 includes at least one first signal transmission pillar 570 , at least one ground pillar 1281 , the dielectric layer 150 , the first pad layer 571 and the second pad layer 572 , and the signal transmission element 1280 is, for example, a surface mount element or Interposer. The first signal transmission column 570 and the grounding column 1281 penetrate through the entire dielectric layer 150 . The first signal transmission column 570 is connected to the first signal contact 120 to be electrically connected to the semiconductor chip 130 through the first signal contact 120 .

Please refer to FIG. 12B , which is a bottom view of the signal transmission element in FIG. 12A . Several grounding columns 1281 surround the first signal transmission column 570 separately from each other, so as to produce electromagnetic interference protection effect on the first signal transmission column 570 . In this example, a plurality of grounding pillars 1281 are arranged in a circle around the first signal transmission pillar 570, but this is not intended to limit the embodiment of the present invention. In addition, the second pad layer 572 includes a signal pad 5721 and a ground pad 5722, wherein the signal pad 5721 is formed on the end surface of the first signal transmission column 570, and the ground pad 5722 is formed on each ground column 1281 in a closed ring shape , so as to electrically connect all the grounding posts 1281 at the same time. In another example, the ground pad 5722 may include several separate sub-pad layers, each of which is formed on the end surface of the corresponding ground pillar 1281 .

Please refer to FIG. 13 , which shows a bottom view of a signal transmission element according to another embodiment of the present invention. In this example, the signal transmission element 1280 includes a plurality of grounding columns 1281 and a first signal transmission column 570 , wherein the plurality of grounding columns 1281 are arranged in a rectangular shape to surround the first signal transmission column 570 .

Please refer to FIG. 14 , which shows a bottom view of a signal transmission element according to another embodiment of the present invention. In this example, the signal transmission element 1280 includes a single grounding column 1281 and a first signal transmission column 570 , wherein the grounding column 1281 is a closed circular annular column that encloses the first signal transmission column 570 .

Please refer to FIG. 15 , which shows a bottom view of a signal transmission element according to another embodiment of the present invention. In this example, the signal transmission element 1280 includes a single grounding column 1281 and a first signal transmission column 570 , wherein the grounding column 1281 is a closed rectangular annular column that encloses the first signal transmission column 570 .

Please refer to FIG. 16 , which is a cross-sectional view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 1300 includes a substrate 1210 , a first signal contact 120 , a semiconductor chip 130 , a package body 140 , a shielding layer 1250 , a dielectric layer 1260 , an antenna layer 1270 and a signal transmission element 1380 .

Compared with the semiconductor package 1200 , the signal transmission element 1380 of the semiconductor package 1300 of this example omits the first signal transmission column 570 , and the semiconductor package 1200 omits the feeding portion 1271 . The dielectric layer 150 of the signal transmission element 1280 may be formed of a waveguide material to help improve signal transmission. The shielding layer 1250 has an opening 1250h directly above the dielectric layer 150 of the signal transmission element 1380 . The signal of the semiconductor chip 130 can be transmitted to the dielectric layer 150 through the first signal contact 120 , and conduct wave conduction in the dielectric layer 150 to the opening 1250h , and then through the electromagnetic induction principle, the shielding layer 1250 and the antenna layer 1270 induce The signal is radiated to the outside by the antenna layer 1270 . Furthermore, even if the physical or mechanical conductive lines are omitted, the signal transmission between the antenna layer 1270 and the first signal contact 120 can still be achieved by electromagnetic induction. In addition, the opening 1250h faces the first signal contact 120 in the vertical direction, so that the signal transmission path is short or shortest.

Please refer to FIG. 17 , which is a cross-sectional view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 1400 includes a substrate 1210 , a first signal contact 120 , a semiconductor chip 130 , a package body 140 , a shielding layer 1250 and at least one signal transmission element 1380 .

Compared with the semiconductor package 1300 , the semiconductor package 1400 of this example omits the dielectric layer 1260 and the antenna layer 1270 . The signal of the semiconductor chip 130 can be transmitted to the dielectric layer 150 through the first signal contact 120 , and is conducted in the dielectric layer 150 to the opening 1250h and then radiated to the outside.

Please refer to FIG. 18A , which is a cross-sectional view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 1500 includes a substrate 1210 , at least two first signal contacts 120 , a semiconductor chip 130 , a package body 140 , a shielding layer 1250 and at least two signal transmission elements 1380 .

Compared with the semiconductor package 1400 , the semiconductor package 1500 of this example includes a plurality of signal transmission elements 1380 , each of which is disposed on the corresponding first signal contact 120 .

Please refer to FIG. 18B , which shows a top view of a semiconductor package according to another embodiment of the present invention. A plurality of signal transmission elements 1380 are arranged in two columns, which are respectively located on opposite sides of the semiconductor chip 130 . By increasing the number of signal transmission elements 1380 , the signal strength of the semiconductor package 1500 can be improved.

Please refer to FIG. 19A , which is a cross-sectional view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 1600 includes a substrate 1210 , at least one first signal contact 120 , a semiconductor chip 130 , a package body 140 , a shielding layer 1250 and at least one signal transmission element 1380 .

The substrate 1210 includes a circuit layer 1121 ′, which is electrically connected to the semiconductor chip 130 to transmit signals of the semiconductor chip 130 . Taking the input signal as an example, the external signal is transmitted to the dielectric layer 150 of the signal transmission element 1380 through the opening 1250h of the shielding layer 1250 , and to several ground posts of the signal transmission element 1380 in the direction of the circuit layer 1121 ′ of the substrate 1210 Waves are conducted laterally back and forth between the 1281 , and through electromagnetic induction, the circuit layer 1121 ′ senses the signal, and then transmits the signal to the semiconductor chip 130 . For the output signal, the signal of the semiconductor chip 130 is transmitted to the wiring layer 1121 ′ and then enters the dielectric layer 150 , and conducts transverse wave conduction between the grounding pillars 1281 in the direction of the opening 1250 h , and then passes through the shielding layer 1250 1250h of the openings radiate out.

Please refer to FIG. 19B, which shows a top view of FIG. 19A. A plurality of grounding pillars 1281 of the signal transmission element 1380 are arranged in a ㄇ shape, and the circuit layer 1121 ′ of the substrate 1210 extends between two opposite rows of the ㄇ shape to receive signals from the dielectric layer 150 ( FIG. 19A ) or The signal of the semiconductor chip 130 is transmitted to the dielectric layer 150 . In addition, the substrate 1210 includes at least one ground pad 1124. A single ground pad 1124 can be electrically connected to all the ground columns 1281 of the single signal transmission element 1380, but as long as all the ground columns 1281 of the single signal transmission element 1380 can be electrically connected at one time, The embodiment of the present invention does not limit the shape of the ground pad 1124 . In addition, the ground pads 1124 are formed in a U-shape, the opening of which faces the circuit layer 1121', and the circuit layer 1121' and the opening of the U-shape are overlapped up and down.

Please refer to FIG. 20 , which is a cross-sectional view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 1700 includes a substrate 1210 , a first signal contact 120 , a semiconductor chip 130 , a package body 140 , a shielding layer 1250 , a dielectric layer 1260 , an antenna layer 1270 and at least one grounding post 1281 .

Compared with the semiconductor package 1300 ( FIG. 16 ), the grounding post 1281 in this example is not formed in the signal transmission element 1280 , but is integrated in the process of the semiconductor package 1400 . The upper surface 140u of the 140 extends to the ground pads 1124 of the substrate 1210 . The grounding pad 1124 is electrically connected to a ground terminal, so that the shielding layer 1250 is grounded through the grounding post 1281 and the grounding pad 1124 . In addition, the circuit layer 1121' of the substrate 1210 can be electrically connected to the semiconductor chip 130 through the conductive holes 1123.

The shielding layer 1250 has at least one opening 1250h located between the grounding pillars 1281 , so that the signal received by the antenna layer 1270 can enter between the first signal transmission pillars 570 from the opening 1250h, or output from the semiconductor chip 130 The signal of 1250h is conducted between these ground posts 1281 and then radiated out from the opening 1250h. In this example, the package body 140 is, for example, a waveguide material, which fills up the space between the grounding pillars 1281 , so that the signal can be transmitted between the grounding pillars 1281 .

The dielectric layer 1260 covers the upper surface 1250u and the outer side surface 1250s of the shielding layer 1250 , that is, the dielectric layer 1260 covers the entire shielding layer 1250 and can completely protect the shielding layer 1250 . The antenna layer 1270 is formed on the upper surface 1260u of the dielectric layer 1260 and disposed corresponding to the openings 1250h of the shielding layer 1250 , so that the signal transmission path between the antenna layer 1270 and the openings 1250h is short or shortest.

Please refer to FIG. 21 , which is a cross-sectional view of a semiconductor package according to another embodiment of the present invention. The semiconductor package 1800 includes a substrate 1210 , a first signal contact 120 , a semiconductor chip 130 , a package body 140 , a shielding layer 1250 , a dielectric layer 1260 , an antenna layer 1270 and a plurality of first signal transmission pillars 570 .

Compared with the semiconductor package 1700 ( FIG. 20 ), the dielectric layer 1260 in this example covers the upper surface 1250u of the shielding layer 1250 but does not cover the outer side surface of the shielding layer 1250 .

Please refer to FIGS. 22A to 22G, which illustrate a manufacturing process diagram of the semiconductor package of FIG. 5A.

As shown in FIG. 22A , at least one semiconductor chip 130 is disposed on the substrate 110 using, for example, Surface Mounted Technology (SMT), and at least one bonding wire 131 is used to electrically connect the semiconductor chip 130 and the substrate 110 .

The substrate 110 includes a substrate 111 , a first composite layer 112 and a second composite layer 113 , wherein the first composite layer 112 and the second composite layer 113 are respectively formed on the upper surface 111u and the lower surface 111b of the substrate 111 . The substrate 111 is, for example, a BT substrate, a glass substrate, a dielectric substrate, or other suitable substrates. The first composite layer 112 includes at least one circuit layer 1121, at least one dielectric layer 1122, and at least one conductive via 1123, wherein the dielectric layer 1122 isolates two adjacent circuit layers 1121, and the two adjacent circuit layers 1121 can be They are electrically connected through corresponding conductive holes 1123 . The structure of the second composite layer 113 may be similar to that of the first composite layer 112 , and details are not described herein again. In addition, the first signal contact 120 is formed on the upper surface 110u of the substrate 110 , which may be a part of the wiring layer 1121 .

As shown in FIG. 22A , a package body 140 is formed to enclose the semiconductor chip 130 and the bonding wires 131 by, for example, compression molding, injection molding or transfer molding.

As shown in FIG. 22B , at least one signal groove 140r is formed in the package body 140 by, for example, laser drilling, jetting drilling or mechanical drilling, wherein the signal groove 140r extends from the upper surface 140u of the package body 140 to the first signal contact 120 to expose the first signal contact 120 .

As shown in FIG. 22C , the first ground layer 160 and the signal pads 121 are formed using, for example, a material forming technique. The first ground layer 160 includes an inner portion 161, an upper portion 162 and a bottom portion 163, wherein the inner portion 161 is formed on the inner sidewall 140r1 of the signal groove 140r, the upper portion 162 is formed on the upper surface 140u of the package body 140, and the bottom portion 163 is formed on the inner sidewall 140r1 of the signal groove 140r. on the circuit layer 1121 of the substrate 110 . The signal pads 121 are formed on the first signal pads 120 .

The above-mentioned material forming techniques are, for example, chemical vapor deposition, electroless plating, electrolytic plating, printing, spin coating, spray coating, sputtering or vacuum deposition.

As shown in FIG. 22D , a dielectric layer 150 is formed to fill the signal groove 140r by means of glue filling. In this example, the dielectric layer 150 may be epoxy resin. So far, the structure of the semiconductor package 100 of FIG. 1A is formed. The method for manufacturing the semiconductor package 500 of FIG. 5A will continue to be described below.

As shown in FIG. 22E , at least through holes 150h are formed through the corresponding dielectric layers 150 by, for example, laser, spray or tool, wherein the through holes 150h extend from the upper surface 150u of the dielectric layer 150 to the signal pads 121 . In another example, if the signal pads 121 are omitted, the through holes 150h extend directly from the upper surface 150u of the dielectric layer 150 to the first signal pads 120 .

As shown in FIG. 22F , the first signal transmission pillar 570 is formed in the through hole 150h using, for example, the above-mentioned material forming technology, wherein part of the material 573 of the first signal transmission pillar 570 protrudes from the upper surface 150u of the dielectric layer 150 .

Then, the upper portion 162 of the first ground layer 160 is patterned in a patterning technique, for example, to obtain a predetermined pattern. In addition, during the patterning step, a portion of the edges of the material 573 may be modified at the same time to obtain suitable or desired dimensions. The patterning technique here is, for example, photolithography, chemical etching, laser drilling or mechanical drilling.

As shown in FIG. 22G , at least one scribe line P1 is formed through the first ground layer 160 , the package body 140 and the substrate 110 with, for example, a knife or a laser, to form at least one structure of the semiconductor package 500 as shown in FIG. 5A .

The manufacturing method of the semiconductor packages 200 , 300 , 400 and 600 is similar to the manufacturing method of the semiconductor package 500 in FIG. 5A , and details are not described herein again.

During the manufacturing process of the semiconductor package 700, the substrate 110 of FIG. 22A can be replaced by the substrate 710, and the signal groove 140r (FIG. 22B), the first ground layer 160 (FIG. 22C), and the dielectric layer 150 (FIG. 22D) are omitted , the formation steps of the through hole 150h (FIG. 22E) and the first signal transmission column 570 (FIG. 22F).

The manufacturing process of the semiconductor package 800 is similar to that of the semiconductor package 700 , and details are not described herein again.

During the fabrication of the semiconductor package 900 , the substrate 110 of FIG. 22A may be replaced by the substrate 710 , so that the semiconductor package 900 may be formed.

Please refer to FIGS. 23A to 23O, which are diagrams illustrating a manufacturing process of the semiconductor package of FIG. 12A.

As shown in FIG. 23A, a substrate 1200 is provided. The substrate 1200 includes a substrate 111, a first conductive layer 1212 and a second conductive layer 1213. The first conductive layer 1212 and the second conductive layer 1213 respectively cover the entire upper surface of the substrate 111. 111u and the entire lower surface 111b. In this example, the substrate 111 may be an insulator.

As shown in FIG. 23B , at least through holes 1210h are formed throughout the entire substrate 1200 by, for example, laser drilling, jet drilling or mechanical drilling.

As shown in FIG. 23C , grounding pillars 1281 are formed on the inner sidewalls of the through holes 1210h by, for example, electroplating, wherein the grounding pillars 1281 are connected to the first conductive layer 1212 and the second conductive layer 1213 .

As shown in FIG. 23D , a dielectric layer 150 is formed to fill the through holes 1210h by, for example, a glue filling method.

As shown in FIG. 23E, at least through holes 150h are formed throughout the entire dielectric layer 150 by, for example, laser drilling, jet drilling or mechanical drilling.

As shown in FIG. 23F , the first signal transmission column 570 , the first pad layer 571 and the second pad layer 572 are formed by the above-mentioned material forming technology, wherein the first signal transmission column 570 fills the through hole 150 h , and the first signal transmission column 570 The pad layer 571 and the second pad layer 572 respectively cover the first conductive layer 1212 and the second conductive layer 1213 and are electrically connected to the first signal transmission column 570 .

As shown in FIG. 23G , the first conductive layer 1212 and the second conductive layer 1213 are patterned by the above patterning technology to electrically isolate the first signal transmission column 570 and the ground column 1281 . After patterning, the first conductive layer 1212 and the second conductive layer 1213 respectively form a first pad layer 571 and a second pad layer 572, each of which includes at least one pad.

As shown in FIG. 23H , at least one scribe line P1 is formed through the substrate 111 , the first conductive layer 1212 and the second conductive layer 1213 by, for example, a knife or a laser, so as to form at least one signal transmission element 1280 as shown in FIG. 12A . .

As shown in FIG. 23I, a substrate 1210 is provided. The substrate 1210 is, for example, a multi-layer structure, which includes at least one circuit layer 1121 and at least one conductive hole 1123 . In another example, the substrate 1210 may be a single-layer structure. In addition, the substrate 1210 further includes at least one grounding point 1211 formed protruding from the upper surface 1210u of the substrate 1210 ; in another example, the grounding point 1211 may extend between the upper surface 1210u and the lower surface 1210b of the substrate 1210 .

As shown in FIG. 23I , at least one semiconductor chip 130 is disposed on the substrate 110 using, for example, surface mount technology, and at least one bonding wire 131 is used to electrically connect the semiconductor chip 130 and the substrate 1210 .

As shown in FIG. 23I , the signal transmission element 1280 of FIG. 23H is disposed on the substrate 1210 by, for example, a surface mount technology, wherein the second pad layer 572 and the first signal transmission column 570 of the signal transmission element 1280 are respectively electrically connected On the circuit layer 1121 (the circuit layer 1121 isolated from the first signal contact 120 ) and the first signal contact 120 . The second pad layer 572 is grounded through the circuit layer 1121 .

As shown in FIG. 23J , the package body 140 is formed to cover the semiconductor chip 130 , the bonding wires 131 and the signal transmission element 1280 by, for example, compression molding, injection molding or transfer molding.

As shown in FIG. 23K , the upper material of the package body 140 is removed by grinding, for example, to form the upper surface 140u of the package body 140 , wherein the first pad layer 571 of the signal transmission element 1280 is exposed from the upper surface 140u of the package body 140 .

As shown in FIG. 23L , at least one scribe line P1 is formed to pass through the package body 140 with, for example, a knife or a laser, until the grounding point 1211 of the substrate 1210 is exposed. Since the dicing line P1 does not completely cut the substrate 1210, this cutting method is called "half-cut". In another example, the dicing line P1 can cut through the entire package body 140 and the entire substrate 1210 , and this cutting method is called “full-cut”.

As shown in FIG. 23M , the shielding layer 1250 is formed to cover the outer side surface 140 s and the upper surface 140 u of the package body 140 by the above-mentioned material forming technology.

As shown in FIG. 23N, a dielectric layer 1260 is formed to cover the upper surface 1250u of the shielding layer 1250 using, for example, a coating technique.

As shown in FIG. 23N , the antenna layer 1270 is formed on the upper surface 1260u of the dielectric layer 1260 by the above-mentioned material forming technology, and the feeding portion 1271 is formed in the opening 1260h of the dielectric layer 1260 , so that the antenna layer 1270 can pass through the feeding portion 1271 It is electrically connected to the first signal transmission column 570 .

As shown in FIG. 230 , at least one scribe line P2 is formed through the substrate 1210 to form at least one semiconductor package 1200 as shown in FIG. 12A .

In the manufacturing process of the semiconductor package 1300 ( FIG. 16 ), the formation steps of the through hole 150h ( FIG. 23E ), the first signal transmission column 570 ( FIG. 23F ), the opening 1260h and the feeding portion 1271 are omitted, and the remaining manufacturing steps are similar to The corresponding steps of manufacturing the semiconductor package 1200 will not be repeated here.

In the manufacturing process of the semiconductor package 1400 ( FIG. 17 ), compared with the manufacturing process of the semiconductor package 1300 , the forming steps of the dielectric layer 1260 and the antenna layer 1270 can be omitted, and the remaining manufacturing steps are similar to those of manufacturing the semiconductor package 1300 . The corresponding steps will not be repeated here.

The manufacturing process of the semiconductor packages 1500 and 1600 is similar to the manufacturing process of the semiconductor package 1400 , and details are not described herein again.

Please refer to FIGS. 24A to 24I , which are diagrams illustrating a manufacturing process of the semiconductor package of FIG. 20 .

As shown in FIG. 24A , a substrate 1210 is provided, wherein the substrate 1210 is, for example, a multi-layer structure including at least one circuit layer 1121 , at least one conductive hole 1123 , at least one ground point 1211 and at least one ground pad 1124 .

As shown in FIG. 24A , at least one semiconductor chip is disposed on the substrate 1210 using, for example, surface mount technology.

As shown in FIG. 24B , a package body 140 is formed to enclose the semiconductor chip 130 and the ground pads 1124 by, for example, compression molding, injection molding or transfer molding.

As shown in FIG. 24C , at least through-holes 141h are formed to extend from the upper surface 140u of the package body 140 to the ground pads 1124 using, for example, the above-mentioned patterning technique to expose the ground pads 1124 .

As shown in FIG. 24D , at least one grounding column 1281 is formed to fill the corresponding through hole 141h by, for example, the above-mentioned material forming technology, so that the grounding column 1281 is grounded through the grounding pads 1124 .

As shown in FIG. 24E , at least one scribe line P1 is formed to extend from the upper surface 140u of the package body 140 to the grounding point 1211 by, for example, a knife or a laser, so as to expose the grounding point 1211 . Since the cutting line P1 does not cut the entire structure, this cutting method is called "semi-penetrating cutting". However, in another example, the all-through dicing method can also be used, that is, the dicing line P1 cuts the entire substrate 1210 .

As shown in FIG. 24F , the shielding layer 1250 is formed on the outer side surface 140s and the upper surface 140u of the package body 140 by, for example, the above-mentioned material forming technology, wherein the shielding layer 1250 is electrically connected to the grounding point 1211 . The shielding layer 1250 has at least one opening 1250h located between the plurality of grounding posts 1281 .

As shown in FIG. 24G , a dielectric layer 1260 is formed to cover the upper surface 1250u and the outer side surface 1250s of the shielding layer 1250 using, for example, a coating technique.

As shown in FIG. 24H , the antenna layer 1270 is formed on the upper surface 1260u of the dielectric layer 1260 by, for example, the above-mentioned material forming technology, wherein the antenna layer 1270 is facing the position of the opening 1250h, so that the distance between the antenna layer 1270 and the opening 1250h is formed. The signal transmission distance between them is the shortest and the loss is the least.

As shown in FIG. 24I , at least one scribe line P2 is formed through the dielectric layer 1260 and the substrate 1210 using, for example, a knife or a laser, to form at least one semiconductor package 1700 as shown in FIG. 20 .

Please refer to FIGS. 25A to 25C , which are diagrams illustrating a manufacturing process of the semiconductor package of FIG. 21 .

As shown in FIG. 25A , a dielectric layer 1260 is formed to cover the upper surface 1250u of the shielding layer 1250 , but expose the outer side surface 1250s of the shielding layer 1250 using, for example, a coating technique.

As shown in FIG. 25B , the antenna layer 1270 is formed on the upper surface 1260u of the dielectric layer 1260 by, for example, the above-mentioned material forming technology, wherein the antenna layer 1270 is facing the position of the opening 1250h, so that the distance between the antenna layer 1270 and the opening 1250h is formed. The signal transmission distance between them is the shortest and the loss is the least.

As shown in FIG. 25C , at least one scribe line P2 is formed through the substrate 1210 to form at least one semiconductor package 1800 as shown in FIG. 21 .

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined according to the claims.

Claims (5)

1. A semiconductor package, comprising: a base plate, including several ground pads; a first signal contact formed on the substrate; a semiconductor chip disposed on the substrate and electrically connected to the first signal contact; and A signal transmission component, disposed on the substrate, includes a dielectric layer, a first signal transmission column and a plurality of grounding columns, wherein the first signal transmission column penetrates the dielectric layer and is connected to the first signal contact, and several grounding columns a grounding column penetrates through the dielectric layer and surrounds the first signal transmission column and is electrically connected to a plurality of grounding pads; a package body, covering the semiconductor chip and the signal transmission component, and having an upper surface and an outer side surface; and a shielding layer formed on an outer side surface and the upper surface of the package body and electrically connected to a ground point of the substrate, wherein the shielding layer has an opening located above the dielectric layer of the signal transmission component; a dielectric layer covering an upper surface of the shielding layer and having an opening; An antenna layer is formed on an upper surface of the dielectric layer on the upper surface of the shielding layer. 2. The semiconductor package of claim 1, wherein the semiconductor package further comprises: A feeding portion is electrically connected to the antenna layer and the first signal transmission column through the opening of the dielectric layer. 3. A semiconductor package, comprising: a base plate, including several ground pads; a first signal contact; a semiconductor chip, disposed on the substrate and electrically connected to the first signal contact; a package body for covering the semiconductor chip and having an upper surface; and a plurality of grounding posts, extending directly from the upper surface of the package body to a plurality of grounding pads of the substrate, and surrounding a part of the package body; A shielding layer is formed on an outer side surface and the upper surface of the package body, and has at least one opening and is located between several grounding posts, wherein the substrate further includes at least one grounding point, and the shielding layer is electrically connected to the ground point; a dielectric layer covering an upper surface of the shielding layer; and An antenna layer is formed on the upper surface of the dielectric layer and disposed corresponding to the opening of the shielding layer. 4. The semiconductor package of claim 3, wherein the substrate further comprises: a plurality of circuit layers, wherein a circuit layer is arranged between the plurality of ground posts to receive signals from the dielectric layer or transmit signals of the semiconductor chip to the dielectric layer; and A plurality of conductive holes, each of the ground pads is electrically connected to an external ground terminal through one of the circuit layers and one of the conductive holes, and the semiconductor chip is electrically connected to the first signal contact through one of the circuit layers and one of the conductive holes. 5 . The semiconductor package of claim 3 , wherein the dielectric layer further covers an outer side surface of the shielding layer. 6 .