CN106023921A - GOA circuit - Google Patents
GOA circuit Download PDFInfo
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- CN106023921A CN106023921A CN201610536534.5A CN201610536534A CN106023921A CN 106023921 A CN106023921 A CN 106023921A CN 201610536534 A CN201610536534 A CN 201610536534A CN 106023921 A CN106023921 A CN 106023921A
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- 239000010409 thin film Substances 0.000 claims abstract description 243
- 239000003990 capacitor Substances 0.000 claims abstract description 22
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims abstract description 19
- 230000005856 abnormality Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 14
- 230000002159 abnormal effect Effects 0.000 description 4
- 230000001808 coupling effect Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention provides a GOA circuit comprising cascaded n-level GOA units; each level GOA unit comprises an up-pull control module, an up-pull module, a down-pull module, a bootstrap capacitor and a square wave signal generation module. The up-pull control module is connected respectively with the up-pull module, the down-pull module and the square wave signal generation module. The GOA circuit of the invention, with a square wave signal generation module to generate a square wave signal whose frequency is between the low frequency and the high frequency, can effectively prevent the gate of a thin film transistor from being affected by too high frequency or too low frequency, thus causing no work abnormality to the circuit.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a GOA circuit.
Background
The Gate Driver On Array, referred to as GOA for short, is a driving method for scanning scan lines line by fabricating a scan driving circuit On an Array substrate of a conventional thin film transistor liquid crystal display panel. Fig. 1 shows a schematic structural diagram of a conventional GOA circuit, which includes a pull-up control module 101, a pull-up module 104, a pull-down module 105, a bootstrap capacitor 103, and a pull-down maintaining module 102.
The pull-down maintaining module 102 is configured to perform auxiliary pull-down on the output q (n) of the pull-up control module in the GOA circuit and the output of the scan signal g (n). The switching frequency of the pull-down maintaining module generally adopts the same frequency as the clock signal frequency or switches once every several frames, which easily causes the gate of the thin film transistor to be affected by high frequency or low frequency signals, resulting in abnormal circuit operation.
Therefore, it is desirable to provide a GOA circuit to solve the problems of the prior art.
Disclosure of Invention
The present invention is directed to a GOA circuit, which can provide a square wave signal to maintain the low levels of the current-stage scan level signal and the current-stage scan signal, and the frequency of the square wave signal is between the low frequency and the high frequency, so as to solve the technical problem of abnormal circuit operation caused by too high or too low switching frequency of the existing GOA circuit.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the embodiment of the invention provides a GOA circuit, which comprises cascaded n-level GOA units, wherein each level of GOA unit comprises:
the pull-up control module is used for generating a scanning level signal of the current stage according to the control of the scanning signal of the previous stage;
the pull-up module is used for pulling up the scanning signal of the current stage according to the scanning level signal of the current stage and the clock signal of the current stage;
the pull-down module is used for pulling down the scanning level signal of the current stage according to the scanning signal of the next stage;
a bootstrap capacitor for generating a high level of the scan signal of the present stage; and the number of the first and second groups,
the square wave signal generating module is used for generating square wave signals to maintain the low level of the scanning level signals of the stage and the scanning signals of the stage; wherein,
the pull-up control module is respectively connected with the pull-up module, the pull-down module and the square wave signal generation module.
The GOA circuit further includes 2m second clock signal sources electrically connected to the square wave signal generating module, and configured to provide the second clock signal of the current stage to the square wave signal generating module to generate the square wave signal of the current stage, where m is a positive integer.
In the GOA circuit of the present invention, the square wave signal generation module of the 2mk + a-th GOA unit is electrically connected to the a-th second clock signal source, where a is an integer less than or equal to 2m, and k is a positive integer greater than or equal to 0.
In the GOA circuit of the present invention, the pulses of the second clock signals provided by the 2m second clock signal sources are the same and the time differences of the second clock signals provided by the adjacent second clock signal sources are the same.
In the GOA circuit, the frequency of the second clock signals provided by the 2m second clock signal sources is 2-50 times of the frequency of the clock signal of the current stage.
In the GOA circuit, the square wave signal generating module comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor and an eighth thin film transistor;
the grid electrode of the first thin film transistor is electrically connected to the output end of the square wave signal generating module of the nth-m grade GOA unit circuit; the source electrode of the first thin film transistor is electrically connected with the constant voltage high level source; the drain electrode of the first thin film transistor is electrically connected with the grid electrode of the third thin film transistor, the grid electrode of the fifth thin film transistor and the drain electrode of the second thin film transistor;
the grid electrode of the second thin film transistor is electrically connected to the output end of the square wave signal generating module of the (n + m) -th-level GOA unit circuit, and the source electrode of the second thin film transistor is electrically connected to the constant voltage low-level source;
the source electrode of the third thin film transistor is electrically connected to the second clock signal source of the current stage; the drain electrode of the third thin film transistor is electrically connected with the output end of the square wave signal generating module;
the grid electrode of the fourth thin film transistor is electrically connected to the output end of the square wave signal generating module of the n + m-th-level GOA unit circuit; the source electrode of the fourth thin film transistor is electrically connected with the constant voltage low level source; the drain electrode of the fourth thin film transistor is electrically connected with the drain electrode of the fifth thin film transistor, the drain electrode of the sixth thin film transistor, the grid electrode of the seventh thin film transistor and the grid electrode of the eighth thin film transistor;
the source electrode of the fifth thin film transistor is electrically connected to the second clock signal source of the current stage;
the grid electrode of the sixth thin film transistor is electrically connected with the output end of the scanning line signal of the current stage; the source electrode of the sixth thin film transistor is electrically connected with the constant voltage low level source;
the source electrode of the seventh thin film transistor is electrically connected with the constant voltage low level source; the drain electrode of the seventh thin film transistor is electrically connected to the output end of the pull-up control module;
the source electrode of the eighth thin film transistor is electrically connected with the constant voltage low level source; the drain of the eighth thin film transistor is electrically connected to the output end of the scanning signal of the current stage.
In the GOA circuit of the present invention, the pull-up control module includes a ninth thin film transistor, a gate of the ninth thin film transistor is electrically connected to an output end of the previous scanning signal; the source electrode of the ninth thin film transistor is electrically connected with the constant-voltage high power supply; the drain electrode of the ninth thin film transistor is electrically connected to the output end of the pull-up control module.
In the GOA circuit, the pull-up module comprises a tenth thin film transistor, and the grid electrode of the tenth thin film transistor is electrically connected to the output end of the pull-up control module; the source electrode of the tenth thin film transistor is connected with the clock signal of the current stage; the drain of the tenth thin film transistor is electrically connected to the output end of the scanning signal of the current stage.
In the GOA circuit of the present invention, the pull-down module includes an eleventh thin film transistor and a twelfth thin film transistor;
the grid electrode of the eleventh thin film transistor is electrically connected with the output end of the scanning signal of the next stage; a source electrode of the eleventh thin film transistor is electrically connected to the constant voltage low power supply; the drain electrode of the eleventh thin film transistor is electrically connected with the output end of the pull-up control module;
the grid electrode of the twelfth thin film transistor is electrically connected with the output end of the scanning signal of the next stage; the source electrode of the twelfth thin film transistor is electrically connected with the constant-voltage low power supply; the drain of the twelfth thin film transistor is electrically connected to the output end of the scanning signal of the current stage.
In the GOA circuit, one end of a bootstrap capacitor is electrically connected to the output end of a pull-up control module; the other end of the bootstrap capacitor is electrically connected to the output end of the scanning signal of the current stage.
Compared with the existing GOA circuit, the GOA circuit provided by the invention has the advantages that the square wave signal generating module is arranged, the frequency of the generated square wave signal is between the low frequency and the high frequency, the influence of the over-high frequency or over-low frequency signal on the grid electrode of the thin film transistor can be effectively prevented, and the abnormal operation of the circuit can be avoided.
In order to make the aforementioned and other objects of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below:
drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic structural diagram of a conventional GOA circuit;
fig. 2 is a schematic structural diagram of a GOA circuit according to a first preferred embodiment of the present invention;
fig. 3 is a waveform diagram of square wave signal generation of the first preferred embodiment of the GOA circuit of the present invention;
fig. 4 is a signal waveform diagram of a first preferred embodiment of the GOA circuit of the present invention;
FIG. 5 is a schematic diagram of a second preferred embodiment of a GOA circuit according to the present invention;
fig. 6 is a waveform diagram of square wave signal generation of the second preferred embodiment of the GOA circuit of the present invention;
fig. 7 is a signal waveform diagram of a second preferred embodiment of the GOA circuit of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Fig. 2 is a schematic structural diagram of a GOA circuit according to a first preferred embodiment of the present invention;
the GOA circuit of the preferred embodiment includes a pull-up control module 201, a pull-up module 202, a pull-down module 203, a bootstrap capacitor Cbt, and a square wave signal generation module 204. A pull-up control module 201, configured to generate a scan level signal of a current stage according to control of a scan signal G (n-1) of a previous stage; a pull-up module 202, configured to pull up the scan signal g (n) according to the scan level signal of the current stage and the clock signal ck (n) of the current stage; a pull-down module 203, configured to pull down the scan level signal of the current stage according to the scan signal G (n +1) of the next stage; a square wave signal generating module 204, configured to generate a square wave signal p (n) to maintain the low level of the scanning level signal of the current stage and the scanning signal of the current stage; the bootstrap capacitor Cbt is disposed between the output end of the pull-up control module 201 and the output end of the scan signal g (n) of the current stage, and is used for generating a high level of the scan signal g (n) of the current stage;
the pull-up control module 201 is connected to the pull-up module 202, the pull-down module 203, and the square wave signal generating module 204, respectively.
The GOA circuit of the embodiment of the present invention further includes 4 second clock signal sources, where the second clock signal sources are electrically connected to the square wave signal generating module 204, and are configured to provide the second clock signal of the current stage to the square wave signal generating module to generate the square wave signal p (n) of the current stage.
It should be noted that the square wave signal generating module 204 of the 4k +1 th level GOA unit of the GOA circuit is electrically connected to the first second clock signal source, the square wave signal generating module 204 of the 4k +2 th level GOA unit of the GOA circuit is electrically connected to the second clock signal source, the square wave signal generating module 204 of the 4k +3 th level GOA unit of the GOA circuit is electrically connected to the third second clock signal source, and the square wave signal generating module 204 of the 4k +4 th level GOA unit of the GOA circuit is electrically connected to the fourth second clock signal source, where k is an integer not less than 0.
The pulses of the second clock signals provided by the 4 second clock signal sources are the same, and the time differences of the second clock signals provided by the adjacent second clock signal sources are the same.
The frequency of the second clock signal provided by the 4 second clock signal sources is 2-50 times of the frequency of the clock signal CK (n) of the current stage. In the preferred embodiment of the present invention, the GOA circuit of the embodiment of the present invention is more stable by adjusting the frequency of the second clock signal provided by the second clock signal source. Preferably, the frequency of the second clock signal provided by the 4 second clock signal sources of the GOA circuit of the embodiment of the present invention is 4 times the frequency of the clock signal ck (n) of this stage.
The square wave signal generating module 204 includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T6, a sixth thin film transistor T6, a seventh thin film transistor T7, and an eighth thin film transistor T8;
the gate of the first thin film transistor T7 is electrically connected to the output end of the square wave signal P (n-2) generating module of the n-2 th level GOA unit; the source of the first thin film transistor T1 is electrically connected to the constant voltage high level source VDD; the drain of the first thin film transistor T1 is electrically connected to the gate of the third thin film transistor T3, the gate of the fifth thin film transistor T5 and the drain of the second thin film transistor T2;
a gate of the second thin film transistor T2 is electrically connected to an output terminal of the square wave signal P (n +2) generating module of the (n +2) th-level GOA unit, and a source of the second thin film transistor T2 is electrically connected to a constant voltage low level source Vss;
the source of the third thin film transistor T3 is electrically connected to the second clock signal source CKH of the current stage; the drain of the third thin film transistor T3 is electrically connected to the output end of the square wave signal generating module p (n);
the gate of the fourth thin film transistor T4 is electrically connected to the output end of the square wave signal P (n +2) generating module of the (n +2) th-level GOA unit; the source of the fourth thin film transistor T4 is electrically connected to the constant voltage low level source Vss; a drain electrode of the fourth thin film transistor T4 is electrically connected to a drain electrode of the fifth thin film transistor T5, a drain electrode of the sixth thin film transistor T6, a gate electrode of the seventh thin film transistor T7 and a gate electrode of the eighth thin film transistor T8;
the source of the fifth thin film transistor T5 is electrically connected to the second clock signal source CKH of the current stage;
the gate of the sixth thin film transistor T6 is electrically connected to the output terminal of the present stage of the scan signal g (n); the source of the sixth thin film transistor T6 is electrically connected to the constant voltage low level source Vss;
the source of the seventh thin film transistor T7 is electrically connected to the constant voltage low level source Vss; the drain of the seventh thin film transistor T7 is electrically connected to the output terminal of the pull-up control module 201;
the source of the eighth thin film transistor T8 is electrically connected to the constant voltage low level source Vss; the drain of the eighth tft T8 is electrically connected to the output terminal of the present stage of the scan signal g (n).
The pull-up control module 201 includes a ninth thin film transistor T9, a gate of the ninth thin film transistor T9 is electrically connected to the output terminal of the previous scanning signal G (n-1); the source of the ninth thin film transistor T9 is electrically connected to the constant voltage high power supply VDD; the drain of the ninth thin film transistor T9 is electrically connected to the output terminal of the pull-up control module 201.
The pull-up module 202 includes a tenth tft T10, a gate of the tenth tft T10 is electrically connected to the output terminal of the pull-up control module 201; the source of the tenth thin film transistor T10 is connected to the clock signal ck (n) of the present stage; the drain of the tenth tft T10 is electrically connected to the output terminal of the present stage of the scan signal g (n).
The pull-down module 203 includes eleventh and twelfth thin film transistors T11 and T12;
a gate of the eleventh thin film transistor T11 is electrically connected to an output terminal of the next scanning signal G (n + 1); the source of the eleventh thin film transistor T11 is electrically connected to the constant voltage low power supply Vss; the drain of the eleventh thin film transistor T11 is electrically connected to the output terminal of the pull-up control module 201;
a gate of the twelfth thin film transistor T12 is electrically connected to the output terminal of the next scanning signal G (n + 1); the source of the twelfth thin film transistor T12 is electrically connected to the constant voltage low power supply Vss; the drain of the twelfth thin film transistor T12 is electrically connected to the output terminal of the present stage of the scan signal g (n).
One end of the bootstrap capacitor Cbt is electrically connected to the output end of the pull-up control module 201; the other end of the bootstrap capacitor Cbt is electrically connected to the output end of the scanning signal g (n) of the current stage.
Referring to fig. 2 and 3, fig. 3 is a waveform diagram of square wave signal generation of the first preferred embodiment of the GOA circuit of the present invention;
in a time period from T1 to T2, when the square wave signal P (n-2) output by the square wave signal generating module of the n-2 th level GOA unit is at a high level, the first thin film transistor T1 is turned on, the constant voltage high level provided by the constant voltage high level source VDD is transmitted to the gates of the third thin film transistor T3 and the fifth thin film transistor T5 through the first thin film transistor T1, the third thin film transistor T3 and the fifth thin film transistor T5 are turned on, at this time, the second clock signal CKH of the present level outputs a low level, and the square wave signal P (n) and the first reference point k (n) output by the present level GOA unit are at a low level through the third thin film transistor T3 and the fifth thin film transistor T5 to the output end of the square wave signal P (n) of the present level GOA unit and the first reference point k (n).
In the time period from T2 to T3, the square wave signal P (n-2) output by the square wave signal generating module of the n-2 th stage GOA unit turns to a low level, but at this time, due to the capacitive coupling effect of the gates of the third thin film transistor T3 and the fifth thin film transistor T5, the gates of the third thin film transistor T3 and the fifth thin film transistor T5 still maintain a high level, at this time, the third thin film transistor T3 and the fifth thin film transistor T5 are still in a conducting state, the corresponding second clock signal CKH of the present stage turns to a high level, and the square wave signal P (n) output by the present stage GOA unit and the first reference point k (n) turn to a high level through the third thin film transistor T3 and the fifth thin film transistor T5 to the output end of the square wave signal P (n) of the present stage GOA unit and the first reference point k (n).
In the time period from T3 to T4, when the square wave signal P (n +2) output by the square wave signal generating module of the n +2 th-level GOA unit is at a high level, the second thin film transistor T2 and the fourth thin film transistor T4 are turned on, and the constant voltage low level provided by the constant voltage low level source Vss is transmitted to the gate of the third thin film transistor T3, the gate of the fifth thin film transistor T5 and the first reference point k (n) through the second thin film transistor T2 and the fourth thin film transistor T4, so that the square wave signal P (n) output by the GOA unit at this level and the first reference point k (n) are turned to a low level.
In the time period from t4 to t5, the square wave signal P (n-2) output by the square wave signal generating module of the n-2 th-level GOA unit and the square wave signal P (n +2) output by the square wave signal generating module of the n +2 th-level GOA unit are at a low level, and the square wave signal P (n) output by the GOA unit of the current level and the first reference point k (n) are at a low level.
Referring to fig. 2 and 4, fig. 4 is a signal waveform diagram of a first preferred embodiment of the GOA circuit of the present invention;
when the GOA circuit of the preferred embodiment is in use, when the scanning signal G (n-1) of the previous stage is at a high level, the ninth thin film transistor T9 is turned on, and the constant voltage high level provided by the constant voltage high level source charges the bootstrap capacitor Cbt through the ninth thin film transistor T9, so that the second reference point q (n) rises to a higher level.
Then, the scan signal G (n-1) of the previous stage goes low, the ninth tft T9 is turned off, and the second reference point q (n) maintains a higher level through the bootstrap capacitor Cbt. Meanwhile, the clock signal ck (n) of the current stage is changed to a high level, the clock signal ck (n) continues to charge the bootstrap capacitor Cbt through the tenth thin film transistor T10, so that the second reference point q (n) reaches a higher level, and the scan signal g (n) of the current stage is changed to a high level.
When the next scanning signal G (n +1) is turned to the high level, the eleventh tft T11 and the twelfth tft T12 are turned on, the low level of the constant voltage generated by the constant voltage low level source Vss is transmitted to the second reference point q (n), the low level of the constant voltage generated by the constant voltage low level source Vss is transmitted to the output terminal of the scanning signal G (n) of the present stage, and the voltage at the second reference point q (n) and the scanning signal G (n) of the present stage are pulled down.
In the preferred embodiment, the square wave signal generated by the square wave signal generating module pulls down the output terminals of the second reference point q (n) and the scanning signal of the current stage 4 times, and maintains the low potential of the output terminals of the second reference point q (n) and the scanning signal g (n) of the current stage. Specifically, when the first reference point k (n) is at a high level, the seventh thin film transistor T7 and the eighth thin film transistor T8 are turned on, the constant voltage low level provided by the constant voltage low level source Vss is transmitted to the second reference point q (n) and the output terminal of the present stage of the scan signal g (n) through the seventh thin film transistor T7 and the eighth thin film transistor T8, and the low level of the second reference point q (n) and the output terminal of the present stage of the scan signal g (n) is maintained.
It is to be noted that, when the output terminal of the scan signal g (n) of the present stage is at a high level, the sixth tft T6 is turned on, and the constant voltage low level provided by the constant voltage low level source Vss is transmitted to the first reference point k (n) through the sixth tft T6, so that the first reference point k (n) is at a low level at this time, and the seventh tft T7 and the eighth tft T8 are turned off at this time.
The GOA circuit of the preferred embodiment is provided with the square wave signal generation module, and the frequency of the generated square wave signal is between the low frequency and the high frequency, so that the gate of the thin film transistor can be effectively prevented from being affected by the signal with too high frequency or too low frequency, and the circuit can not work abnormally.
Fig. 5 is a schematic structural diagram of a second preferred embodiment of the GOA circuit of the present invention;
the difference between the GOA circuit of the present preferred embodiment and the GOA circuit of the first preferred embodiment is that the number of the second clock signals connected to the GOA circuit is 8, which can further reduce power consumption and does not cause abnormal circuit operation.
The GOA circuit of the preferred embodiment includes a pull-up control module 301, a pull-up module 302, a pull-down module 303, a bootstrap capacitor Cbt, and a square wave signal generation module 304. A pull-up control module 301, configured to generate a scan level signal of a current stage according to control of a scan signal G (n-1) of a previous stage; a pull-up module 302 for pulling up the scan signal g (n) according to the scan level signal and the clock signal ck (n); a pull-down module 303, configured to pull down a scan level signal of a next stage according to a scan signal G (n +1) of the next stage; a square wave signal generating module 304, configured to generate a square wave signal p (n) to maintain the low level of the scanning level signal of the current stage and the scanning signal of the current stage; the bootstrap capacitor Cbt is disposed between the output end of the pull-up control module 301 and the output end of the scan signal g (n) of the current stage, and is used for generating a high level of the scan signal g (n) of the current stage;
the pull-up control module 301 is connected to the pull-up module 302, the pull-down module 303, and the square wave signal generating module 304.
The GOA circuit of the embodiment of the present invention is connected to 8 second clock signal sources CKH, and the second clock signal sources are electrically connected to the square wave signal generating module 304, and are configured to provide the second clock signal of the current stage to the square wave signal generating module to generate the square wave signal p (n) of the current stage.
It should be noted that the square wave signal generating module 304 of the 8k +1 level GOA unit of the GOA circuit is electrically connected to the first second clock signal source CKH, the square wave signal generating module 304 of the 8k +2 level GOA unit of the GOA circuit is electrically connected to the second clock signal source, the square wave signal generating module 304 of the 8k +3 level GOA unit of the GOA circuit is electrically connected to the third second clock signal source, the square wave signal generating module 304 of the 8k +4 level GOA unit of the GOA circuit is electrically connected to the fourth second clock signal source, the square wave signal generating module 304 of the 8k +5 level GOA unit of the GOA circuit is electrically connected to the fifth second clock signal source CKH, the square wave signal generating module 304 of the 8k +6 level GOA unit of the GOA circuit is electrically connected to the sixth second clock signal source CKH, the square wave signal generating module 304 of the 8k +7 level GOA unit of the GOA circuit is electrically connected to the seventh second clock signal source CKH, the square wave signal generating module 304 of the 8k +8 th level GOA unit of the GOA circuit is electrically connected to the eighth second clock signal source CKH, wherein k is an integer not less than 0.
The pulses of the second clock signals provided by the 8 second clock signal sources are the same, and the time differences of the second clock signals provided by the adjacent second clock signal sources are the same. .
The frequency of the second clock signal provided by the 8 second clock signal sources is 2-50 times of the frequency of the clock signal CK (n) of the current stage. In the preferred embodiment of the present invention, the GOA circuit of the embodiment of the present invention is more stable by adjusting the frequency of the second clock signal provided by the second clock signal source. Preferably, the frequency of the second clock signal provided by the 8 second clock signal sources of the GOA circuit of the embodiment of the present invention is 2 times the frequency of the clock signal ck (n) of this stage.
The square wave signal generating module 304 includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T6, a sixth thin film transistor T6, a seventh thin film transistor T7, and an eighth thin film transistor T8;
the grid of the first thin film transistor T7 is electrically connected to the output end of the square wave signal P (n-4) generating module of the n-4 th level GOA unit; the source of the first thin film transistor T1 is electrically connected to the constant voltage high level source VDD; the drain of the first thin film transistor T1 is electrically connected to the gate of the third thin film transistor T3, the gate of the fifth thin film transistor T5 and the drain of the second thin film transistor T2;
the gate of the second thin film transistor T2 is electrically connected to the output terminal of the square wave signal P (n +4) generating module of the n +4 th-level GOA unit, and the source of the second thin film transistor T2 is electrically connected to the constant voltage low level source Vss;
the source of the third thin film transistor T3 is electrically connected to the second clock signal source CKH of the current stage; the drain of the third thin film transistor T3 is electrically connected to the output end of the square wave signal generating module p (n);
the gate of the fourth thin film transistor T4 is electrically connected to the output end of the square wave signal P (n +4) generating module of the (n +4) th-level GOA unit; the source of the fourth thin film transistor T4 is electrically connected to the constant voltage low level source Vss; a drain electrode of the fourth thin film transistor T4 is electrically connected to a drain electrode of the fifth thin film transistor T5, a drain electrode of the sixth thin film transistor T6, a gate electrode of the seventh thin film transistor T7 and a gate electrode of the eighth thin film transistor T8;
the source of the fifth thin film transistor T5 is electrically connected to the second clock signal source CKH of the current stage;
the gate of the sixth thin film transistor T6 is electrically connected to the output terminal of the present stage of the scan signal g (n); the source of the sixth thin film transistor T6 is electrically connected to the constant voltage low level source Vss;
the source of the seventh thin film transistor T7 is electrically connected to the constant voltage low level source Vss; the drain of the seventh thin film transistor T7 is electrically connected to the output terminal of the pull-up control module 301;
the source of the eighth thin film transistor T8 is electrically connected to the constant voltage low level source Vss; the drain of the eighth tft T8 is electrically connected to the output terminal of the present stage of the scan signal g (n).
The pull-up control module 301 comprises a ninth thin film transistor T9, wherein a gate of the ninth thin film transistor T9 is electrically connected to an output terminal of the previous scanning signal G (n-1); the source of the ninth thin film transistor T9 is electrically connected to the constant voltage high power supply VDD; the drain of the ninth thin film transistor T9 is electrically connected to the output terminal of the pull-up control module 301.
The pull-up module 302 includes a tenth tft T10, a gate of the tenth tft T10 is electrically connected to the output terminal of the pull-up control module 301; the source of the tenth thin film transistor T10 is connected to the clock signal ck (n) of the present stage; the drain of the tenth tft T10 is electrically connected to the output terminal of the present stage of the scan signal g (n).
The pull-down module 303 includes an eleventh thin film transistor T11 and a twelfth thin film transistor T12;
a gate of the eleventh thin film transistor T11 is electrically connected to an output terminal of the next scanning signal G (n + 1); the source of the eleventh thin film transistor T11 is electrically connected to the constant voltage low power supply Vss; the drain of the eleventh thin film transistor T11 is electrically connected to the output terminal of the pull-up control module 301;
a gate of the twelfth thin film transistor T12 is electrically connected to the output terminal of the next scanning signal G (n + 1); the source of the twelfth thin film transistor T12 is electrically connected to the constant voltage low power supply Vss; the drain of the twelfth thin film transistor T12 is electrically connected to the output terminal of the present stage of the scan signal g (n).
One end of the bootstrap capacitor Cbt is electrically connected to the output end of the pull-up control module 301; the other end of the bootstrap capacitor Cbt is electrically connected to the output end of the scanning signal g (n) of the current stage.
Referring to fig. 5 and 6, fig. 6 is a waveform diagram of square wave signal generation of the second preferred embodiment of the GOA circuit of the present invention;
in a time period from T1 to T2, when the square wave signal P (n-4) output by the square wave signal generating module of the n-4 th stage GOA unit is at a high level, the first thin film transistor T1 is turned on, the constant voltage high level provided by the constant voltage high level source VDD is transmitted to the gates of the third thin film transistor T3 and the fifth thin film transistor T5 through the first thin film transistor T1, the third thin film transistor T3 and the fifth thin film transistor T5 are turned on, and at this time, the second clock signal CKH outputs a low level, which is transmitted to the output terminal of the square wave signal P (n) of the GOA unit of the present stage and the first reference point k (n) through the third thin film transistor T3 and the fifth thin film transistor T5, so that the signal P (n) output by the GOA unit of the present stage and the first reference point k (n) are at a low level.
In the time period from T2 to T3, the square wave signal P (n-4) output by the square wave signal generating module of the n-4 th stage GOA unit turns to a low level, but at this time, due to the capacitive coupling effect of the gates of the third thin film transistor T3 and the fifth thin film transistor T5, the gates of the third thin film transistor T3 and the fifth thin film transistor T5 still maintain a high potential, at this time, the third thin film transistor T3 and the fifth thin film transistor T5 are still in a conducting state, the corresponding second clock signal CKH of the present stage turns to a high level, and the square wave signal P (n) output by the present stage GOA unit and the first reference point k (n) turn to a high level through the third thin film transistor T3 and the fifth thin film transistor T5 to the output end of the square wave signal P (n) of the present stage GOA unit and the first reference point k (n).
In the time period from T3 to T4, when the square wave signal P (n +4) output by the square wave signal generating module of the n +4 th-level GOA unit is at a high level, the second thin film transistor T2 and the fourth thin film transistor T4 are turned on, and the constant voltage low level provided by the constant voltage low level source Vss is transmitted to the gate of the third thin film transistor T3, the gate of the fifth thin film transistor T5 and the first reference point k (n) through the second thin film transistor T2 and the fourth thin film transistor T4, so that the square wave signal P (n) output by the GOA unit at this level and the first reference point k (n) are turned to a low level.
In the time period from t4 to t5, the square wave signal P (n-4) output by the square wave signal generating module of the n-4 th-level GOA unit and the square wave signal P (n +4) output by the square wave signal generating module of the n +4 th-level GOA unit are at a low level, and the square wave signal P (n) output by the GOA unit of the current level and the first reference point k (n) are at a low level.
Referring to fig. 5 and 7, fig. 7 is a signal waveform diagram of a second preferred embodiment of the GOA circuit of the present invention;
when the GOA circuit of the preferred embodiment is in use, when the scanning signal G (n-1) of the previous stage is at a high level, the ninth thin film transistor T9 is turned on, and the constant voltage high level provided by the constant voltage high level source charges the bootstrap capacitor Cbt through the ninth thin film transistor T9, so that the second reference point q (n) rises to a higher level.
Then, the scan signal G (n-1) of the previous stage goes low, the ninth tft T9 is turned off, and the second reference point q (n) maintains a higher level through the bootstrap capacitor Cbt. Meanwhile, the clock signal ck (n) of the current stage is changed to a high level, the clock signal ck (n) continues to charge the bootstrap capacitor Cbt through the tenth thin film transistor T10, so that the second reference point q (n) reaches a higher level, and the scan signal g (n) of the current stage is changed to a high level.
When the next scanning signal G (n +1) is turned to the high level, the eleventh tft T11 and the twelfth tft T12 are turned on, the low level of the constant voltage generated by the constant voltage low level source Vss is transmitted to the second reference point q (n), the low level of the constant voltage generated by the constant voltage low level source Vss is transmitted to the output terminal of the scanning signal G (n) of the present stage, and the voltage at the second reference point q (n) and the scanning signal G (n) of the present stage are pulled down.
In the preferred embodiment, the square wave signal generated by the square wave signal generating module pulls down the second reference point q (n) and the output terminal of the scanning signal of the current stage for 2 times, and maintains the low potential of the second reference point q (n) and the output terminal of the scanning signal g (n) of the current stage. Specifically, when the first reference point k (n) is at a high level, the seventh thin film transistor T7 and the eighth thin film transistor T8 are turned on, the constant voltage low level provided by the constant voltage low level source Vss is transmitted to the second reference point q (n) and the output terminal of the present stage of the scan signal g (n) through the seventh thin film transistor T7 and the eighth thin film transistor T8, and the low level of the second reference point q (n) and the output terminal of the present stage of the scan signal g (n) is maintained.
It is to be noted that, when the output terminal of the scan signal g (n) of the present stage is at a high level, the sixth tft T6 is turned on, and the constant voltage low level provided by the constant voltage low level source Vss is transmitted to the first reference point k (n) through the sixth tft T6, so that the first reference point k (n) is at a low level at this time, and the seventh tft T7 and the eighth tft T8 are turned off at this time.
The GOA circuit of the preferred embodiment is provided with the square wave signal generation module, and the frequency of the generated square wave signal is between the low frequency and the high frequency, so that the gate of the thin film transistor can be effectively prevented from being affected by the signal with too high frequency or too low frequency, and the circuit can not work abnormally.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. A GOA circuit, comprising a cascade of n GOA units, each GOA unit comprising:
the pull-up control module is used for generating a scanning level signal of the current stage according to the control of the scanning signal of the previous stage;
the pull-up module is used for pulling up the scanning signal of the current stage according to the scanning level signal of the current stage and the clock signal of the current stage;
the pull-down module is used for pulling down the scanning level signal of the current stage according to the scanning signal of the next stage;
a bootstrap capacitor for generating a high level of the scan signal of the present stage; and the number of the first and second groups,
the square wave signal generating module is used for generating square wave signals to maintain the scanning level signals of the current stage and the low level of the scanning signals of the current stage; wherein,
the pull-up control module is respectively connected with the pull-up module, the pull-down module and the square wave signal generation module.
2. The GOA circuit of claim 1, further comprising 2m second clock signal sources electrically connected to the square wave signal generation module, configured to provide a second clock signal of a current stage to the square wave signal generation module to generate the square wave signal of the current stage, where m is a positive integer.
3. The GOA circuit of claim 2, wherein the square wave signal generation module of a 2mk + a level GOA unit is electrically connected to the a-th second clock signal source, where a is an integer less than or equal to 2m, and k is a positive integer greater than or equal to 0.
4. The GOA circuit of claim 2, wherein the pulses of the second clock signals provided by the 2m second clock signal sources are the same and the time differences of the second clock signals provided by adjacent second clock signal sources are the same.
5. The GOA circuit according to claim 2, wherein the frequency of the second clock signals provided by the 2m second clock signal sources is 2-50 times of the frequency of the clock signal of the current stage.
6. The GOA circuit according to claim 2, wherein the square wave signal generating module comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor and an eighth thin film transistor;
the grid electrode of the first thin film transistor is electrically connected to the output end of the square wave signal generating module of the nth-m grade GOA unit; the source electrode of the first thin film transistor is electrically connected with a constant voltage high-level source; the drain electrode of the first thin film transistor is electrically connected with the grid electrode of the third thin film transistor, the grid electrode of the fifth thin film transistor and the drain electrode of the second thin film transistor;
the grid electrode of the second thin film transistor is electrically connected to the output end of the square wave signal generation module of the (n + m) -th-level GOA unit circuit, and the source electrode of the second thin film transistor is electrically connected to the constant voltage low level source;
the source electrode of the third thin film transistor is electrically connected to the second clock signal source of the current stage; the drain electrode of the third thin film transistor is electrically connected to the output end of the square wave signal generation module;
the grid electrode of the fourth thin film transistor is electrically connected to the output end of the square wave signal generating module of the n + m-th-level GOA unit circuit; the source electrode of the fourth thin film transistor is electrically connected with the constant voltage low level source; the drain electrode of the fourth thin film transistor is electrically connected to the drain electrode of the fifth thin film transistor, the drain electrode of the sixth thin film transistor, the gate electrode of the seventh thin film transistor and the gate electrode of the eighth thin film transistor;
the source electrode of the fifth thin film transistor is electrically connected to the second clock signal source of the current stage;
the grid electrode of the sixth thin film transistor is electrically connected to the output end of the scanning line signal of the current stage; the source electrode of the sixth thin film transistor is electrically connected to the constant voltage low level source;
the source electrode of the seventh thin film transistor is electrically connected to the constant voltage low level source; the drain electrode of the seventh thin film transistor is electrically connected to the output end of the pull-up control module;
a source electrode of the eighth thin film transistor is electrically connected to the constant voltage low level source; and the drain electrode of the eighth thin film transistor is electrically connected to the output end of the scanning signal of the current stage.
7. The GOA circuit according to claim 1, wherein the pull-up control module comprises a ninth TFT, a gate of the ninth TFT being electrically connected to an output of a previous scanning signal; the source electrode of the ninth thin film transistor is electrically connected with a constant-voltage high power supply; and the drain electrode of the ninth thin film transistor is electrically connected to the output end of the pull-up control module.
8. The GOA circuit according to claim 1, wherein the pull-up module comprises a tenth TFT, a gate of the tenth TFT being electrically connected to the output terminal of the pull-up control module; the source electrode of the tenth thin film transistor is connected to the clock signal of the current stage; and the drain electrode of the tenth thin film transistor is electrically connected to the output end of the scanning signal of the current stage.
9. The GOA circuit of claim 1, wherein the pull-down module comprises an eleventh thin film transistor and a twelfth thin film transistor;
a grid electrode of the eleventh thin film transistor is electrically connected to the output end of the scanning signal of the next stage; a source electrode of the eleventh thin film transistor is electrically connected to a constant voltage low power supply; the drain electrode of the eleventh thin film transistor is electrically connected with the output end of the pull-up control module;
the grid electrode of the twelfth thin film transistor is electrically connected to the output end of the scanning signal of the next stage; a source electrode of the twelfth thin film transistor is electrically connected to a constant voltage low power supply; and the drain electrode of the twelfth thin film transistor is electrically connected to the output end of the scanning signal of the current stage.
10. The GOA circuit of claim 1, wherein one end of the bootstrap capacitor is electrically connected to an output end of the pull-up control module; the other end of the bootstrap capacitor is electrically connected to the output end of the scanning signal of the current stage.
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