CN106021041A - Finite state machine based multi-cycle non-flow line CPU debugging method - Google Patents

Abstract

The invention discloses a multi-cycle non-pipeline CPU debugging method based on a finite state machine. The method can "pause" the CPU work without changing the CPU register group, program counter, status register and other CPU operation sites. In this state, the state of the CPU can be read out to achieve the purpose of debugging; in addition, this solution introduces less additional circuits, and this function will not affect the operating state and efficiency of the CPU in the normal working mode.

Description

Multi-cycle non-pipelined CPU debugging method based on finite state machine

technical field

The invention relates to the technical field of computers, in particular to a multi-cycle non-pipeline CPU debugging method based on a finite state machine.

Background technique

In the processor design process, a lot of manpower and material resources are often spent to verify the correctness of the CPU. Once a problem occurs, a reliable means is needed to locate the problem.

However, in the prior art, it is necessary to introduce relatively complex circuits when debugging a running CPU, and at the same time, it also has a certain impact on the running state and efficiency of the CPU.

Contents of the invention

The purpose of the present invention is to provide a multi-cycle non-pipeline CPU debugging method based on a finite state machine, which introduces fewer additional circuits, and does not affect the operating state and efficiency of the CPU in the normal operating mode of the CPU.

The purpose of the present invention is achieved through the following technical solutions:

A multi-cycle non-pipeline CPU debugging method based on a finite state machine, comprising:

The steps for the CPU to process each instruction are instruction fetching, decoding, execution, memory access, and write-back in sequence, and the jump between steps is realized by a finite state machine;

Realize CPU debugging by introducing register A and register B, described register A is used for setting operation mode, and described register B is used for instruction counting; The steps of realizing CPU debugging are as follows:

In the initial state or after the current instruction executes the write-back step, the finite state machine judges the current operating mode according to the value of the register A;

If it is multi-step debugging mode, then enter the debugging state, and judge the value of register B; when register B is not zero, the value of register B is subtracted by 1, and this debugging state is skipped by described finite state machine, by CPU Continue to process the next instruction, so that after the value of register B is reduced to zero, the CPU is blocked in the debugging state by the finite state machine;

If it is a single-step debugging mode, the CPU is blocked in the debugging state by the finite state machine until the register B has a new instruction count to write, and the finite state machine controls to leave the debugging state, and at the same time, the value of the register B cleared.

Further, if it is determined according to the value of the register A that the current mode is in the normal working mode, the CPU continues to process the next instruction.

As can be seen from the technical solution provided by the present invention above, the CPU work can be "suspended" without changing the CPU register group, program counter, status register and other CPU operation sites, and the status of the CPU can be read in this state. In order to achieve the purpose of debugging; in addition, this solution introduces less additional circuits, and this function will not affect the running status and efficiency of the CPU in normal working mode.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings on the premise of not paying creative work.

FIG. 1 is a schematic diagram of CPU processing each instruction provided by an embodiment of the present invention;

2 is a schematic diagram of a multi-cycle non-pipeline CPU debugging method based on a finite state machine provided by an embodiment of the present invention;

FIG. 3 is a flow chart for implementing CPU debugging provided by an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

As shown in Figure 1, the steps for the CPU to process each instruction are fetching, decoding, executing, accessing memory, and writing back in sequence; the jump between steps is realized by a finite state machine;

In the embodiment of the present invention, CPU debugging is realized by introducing register A and register B, and at the same time, a decision state is inserted into the finite state machine, as shown in FIG. 2 .

In the embodiment of the present invention, the register A is used to set the running mode, and the register B is used to count instructions.

The steps to realize CPU debugging are shown in Figure 3, which mainly include:

In the initial state or after the current instruction executes the write-back step, the finite state machine judges the current operating mode according to the value of the register A;

If it is multi-step debugging mode, then enter the debugging state, and judge the value of register B; when register B is not zero, the value of register B is subtracted by 1, and this debugging state is skipped by described finite state machine, by CPU Continue to process the next instruction, so that after the value of register B is reduced to zero, the CPU is blocked in the debugging state by the finite state machine;

If it is a single-step debugging mode, the CPU is blocked in the debugging state by the finite state machine until the register B has a new instruction count to write, and the finite state machine controls to leave the debugging state, and at the same time, the value of the register B cleared.

After the finite state machine blocks the CPU in the debugging state, the state of the CPU can be read out to achieve the purpose of debugging.

In addition, if it is determined according to the value of the register A that the current operation mode is normal, the CPU will continue to process the next instruction.

It can be seen from the above process that the operating modes mainly include: normal working mode, multi-step debugging mode, and single-step debugging mode, and the values corresponding to each operating mode can be preset and stored in register A.

Exemplarily, the register A can take three values: 0, 1, and 2, 0 is the normal working mode (this mode is the default state), 1 is the single-step debugging mode, and 2 is the multi-step debugging mode.

The process of using the single-step debugging mode is as follows:

1) Set register A to 1 to enter the single-step debugging mode, and the CPU will block after executing the current instruction.

2) Write data to register B (don't care about the written value), and execute the next instruction.

3) Read the CPU state (PC, state register, register file and data RAM, etc.) through the debug interface.

4) Repeat steps 2 and 3 until the debugging is completed.

5) Set register A to 0, return to the normal working mode, and the CPU continues to work.

The process of using the multi-step debugging mode is as follows:

1) Set register A to 2 to enter the multi-step debugging mode. At this time, the value of register B should be 0, and the CPU will block after executing the current instruction.

2) Write data to register B.

3) The CPU continues to execute instructions, and every time an instruction is executed, the data in register B is decremented by 1 until the value of register B becomes 0, and then it will block.

4) Read the CPU status (PC, status register, register file and data RAM, etc.) through the debug interface

5) If you need to continue multi-step debugging, execute steps 2, 3, and 4; otherwise, execute step 6.

6) Set the value of register A to 0, return to the normal working mode, and the CPU continues to work.

In the above solution of the embodiment of the present invention, the CPU work can be "suspended" without changing the CPU register group, program counter, status register and other CPU operation sites. In this state, the state of the CPU can be read out to The purpose of debugging is achieved; in addition, this solution introduces less additional circuits, and this function will not affect the running state and efficiency of the CPU in the normal working mode.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person familiar with the technical field can easily conceive of changes or changes within the technical scope disclosed in the present invention. Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (2)

1. a multicycle nonpipeline CPU adjustment method based on finite state machine, it is characterised in that including:

CPU process the step of every instruction be followed successively by fetching, decode, perform, memory access and write-back, redirecting between step Realized by finite state machine；

Realizing CPU debugging by introducing depositor A and depositor B, described depositor A is used for arranging operational mode, institute State depositor B for instruction count；The step realizing CPU debugging is as follows:

After original state or present instruction have performed write back step, described finite state machine judges according to the value of depositor A Current operational mode；

If multistep debugging mode, then enter debugging mode, and judge the value of depositor B；When depositor B is not zero, The value of depositor B is subtracted 1, and is skipped this debugging mode by described finite state machine, CPU continue with next and refer to Order, so circulation are until after the value of depositor B is kept to zero, being blocked in debugging mode by described finite state machine by CPU；

If single-step debug pattern, described finite state machine CPU is blocked in debugging mode, until depositor B has new Instruction count writes, and is left debugging mode by described finite states machine control, the value of depositor B is reset meanwhile.

A kind of multicycle nonpipeline CPU adjustment method based on finite state machine the most according to claim 1, its Being characterised by, if judging according to the value of depositor A current for normal mode of operation, then being continued with next finger by CPU Order.