CN105990495A - Light-emitting unit and semiconductor light-emitting device - Google Patents

Abstract

Embodiments of the present invention provide a light-emitting unit capable of connecting a plurality of light-emitting elements in a multi-chip package by a simple structure, and a semiconductor light-emitting device. According to the embodiments, a semiconductor light-emitting device has a plurality of light-emitting elements each having two external terminals, and a resin layer supporting the plurality of light-emitting elements integrally. The plurality of light-emitting elements includes n light-emitting elements arranged in a first direction. The (2*n) external terminals of the n light-emitting elements are arranged in the first direction. Out of the (2*n) external terminals, the external terminal at one end in the first direction is bonded to a first pad, the external terminal at the other end in the first direction is bonded to a second pad, and the external terminal between the external terminal at one end and the external terminal at the other end is bonded to a third pad.

Description

Light emitting unit and semiconductor light emitting device

[Related applications]

This application enjoys the priority of Japanese Patent Application No. 2014-187250 (filing date: September 16, 2014) as the basic application. This application includes the entire content of the basic application by referring to this basic application.

technical field

Embodiments of the present invention relate to a light emitting unit and a semiconductor light emitting device.

Background technique

A semiconductor light emitting device having a chip size package structure in which a phosphor layer is provided on one side of a chip including a light emitting layer and an electrode, a wiring layer, and a resin layer are provided on the other side has been proposed. In addition, in a multi-chip package, a structure in which a plurality of chips are electrically connected by a wiring layer in the package has also been proposed.

Contents of the invention

Embodiments of the present invention provide a light emitting unit and a semiconductor light emitting device capable of connecting a plurality of light emitting elements in a multi-chip package with a simple structure.

According to an embodiment, a light emitting unit includes a mounting substrate and a semiconductor light emitting device. The mount substrate has a first pad, a second pad, and a third pad disposed between the first pad and the second pad. The semiconductor light emitting device includes: a plurality of light emitting elements each having two external terminals; and a resin layer integrally supporting the plurality of light emitting elements. The plurality of light emitting elements include n (n is an integer greater than or equal to 2) light emitting elements arranged along the first direction. The (2×n) external terminals of the n light emitting elements are arranged along the first direction. Among the (2×n) external terminals, an external terminal at one end in the first direction is bonded to the first pad, and an external terminal at the other end in the first direction is bonded to the second pad, so An external terminal between the external terminal at one end and the external terminal at the other end is joined to the third pad.

Description of drawings

FIG. 1 is a schematic plan view of a light emitting unit according to the embodiment.

Fig. 2(a) is a schematic plan view of a mounting substrate according to the embodiment, and Fig. 2(b) is a schematic plan view of the semiconductor light emitting device according to the embodiment.

Fig. 3 is a schematic cross-sectional view of the semiconductor light emitting device according to the embodiment.

4 is a schematic plan view showing an electrode layout of the semiconductor light emitting device according to the embodiment.

5 is a partial schematic cross-sectional view of the semiconductor light emitting device according to the embodiment.

Fig. 6 is a schematic plan view of the mounting substrate of the embodiment.

Fig. 7 is a schematic plan view of the light emitting unit of the embodiment.

Fig. 8(a) is a schematic plan view of a mounting substrate according to an embodiment, and Fig. 8(b) is a schematic plan view of a semiconductor light emitting device according to an embodiment.

Fig. 9 is a schematic plan view of the light emitting unit of the embodiment.

Fig. 10(a) is a schematic plan view of a mounting substrate according to the embodiment, and Fig. 10(b) is a schematic plan view of the semiconductor light emitting device according to the embodiment.

Fig. 11 is a schematic cross-sectional view of the semiconductor light emitting device of the embodiment.

Fig. 12 is a schematic plan view of the semiconductor light emitting device of the embodiment.

13 is a schematic cross-sectional view of a semiconductor light emitting device according to an embodiment.

14 is a schematic cross-sectional view of a semiconductor light emitting device according to an embodiment.

detailed description

Embodiments will be described below with reference to the drawings. In addition, in each drawing, the same code|symbol is attached|subjected to the same element.

FIG. 1 is a schematic plan view of a light emitting unit according to the embodiment.

FIG. 2( a ) is a schematic plan view of a mounting substrate 70 according to the embodiment.

Fig. 2(b) is a schematic plan view of the semiconductor light emitting device 1 of the embodiment.

FIG. 3 is a schematic cross-sectional view of the semiconductor light emitting device 1 according to the embodiment.

FIG. 2( b ) shows the mounting surface of the semiconductor light emitting device 1 and corresponds to the bottom view of the semiconductor light emitting device 1 shown in FIG. 3 .

1 shows that the semiconductor light emitting device 1 is mounted on the mounting substrate 70 with the mounting surface of the semiconductor light emitting device 1 shown in FIG. 2( b) facing the pads 81-83 of the mounting substrate 70 shown in FIG. 2( a). status. 1 is a schematic plan view of the semiconductor light emitting device 1 viewed from the upper surface side (the side opposite to the mounting surface) in a state where the semiconductor light emitting device 1 is mounted on a mounting substrate 70 .

The semiconductor light emitting device 1 has a plurality of light emitting elements 10 . In the example shown in FIG. 1 , FIG. 2( b ) and FIG. 3 , the semiconductor light emitting device 1 has, for example, two light emitting elements 10 . The plurality of light emitting elements 10 are encapsulated by the resin layer 25 at the wafer level, and the resin layer 25 supports the plurality of light emitting elements 10 integrally.

The outer shape of the semiconductor light emitting device 1 viewed from the upper surface or the mounting surface side opposite to the upper surface is, for example, a rectangle. For example, two light emitting elements 10 are arranged in the long side direction (first direction X) of the rectangle. Each light emitting element 10 has the same configuration.

As shown in FIG. 3 , the light emitting element 10 includes a semiconductor layer 15 including a light emitting layer 13 . The semiconductor layer 15 has one side (first side) 15a in the thickness direction and a second side 15b opposite to the first side 15a ( FIG. 4 ).

4 is a schematic plan view of the second side 15 b of the semiconductor layer 15 in one light emitting element 10 , and shows an example of the planar layout of the p-side electrode 16 and the n-side electrode 17 .

The second side 15b of the semiconductor layer 15 has a portion (light emitting region) 15e including the light emitting layer 13 and a portion 15f not including the light emitting layer 13 . The portion 15 e including the light emitting layer 13 is a portion of the semiconductor layer 15 on which the light emitting layer 13 is laminated. The portion 15f not containing the light emitting layer 13 is a portion of the semiconductor layer 15 where the light emitting layer 13 is not laminated. The portion 15e including the light emitting layer 13 represents a region having a laminated structure capable of extracting light emitted from the light emitting layer 13 to the outside.

On the second side 15b, a p-side electrode 16 is provided as a first electrode on a portion 15e including the luminescent layer 13, and an n-side electrode 17 is provided as a second electrode on a portion 15f not containing the luminescent layer.

In the example shown in FIG. 4 , a portion 15 f not containing the light emitting layer 13 surrounds a portion 15 e containing the light emitting layer 13 , and the n-side electrode 17 surrounds the p-side electrode 16 .

A current is supplied to the light-emitting layer 13 through the p-side electrode 16 and the n-side electrode 17, so that the light-emitting layer 13 emits light. Furthermore, the light emitted from the light emitting layer 13 is emitted to the outside of the semiconductor light emitting device 1 from the first side 15 a.

As shown in FIG. 3 , a support 100 is provided on the second side of the semiconductor layer 15 . The light emitting element 10 including the semiconductor layer 15 , the p-side electrode 16 and the n-side electrode 17 is supported by the support 100 provided on the second side.

On the first side 15 a of the semiconductor layer 15 , a phosphor layer 30 is provided as an optical layer that imparts desired optical characteristics to the emitted light of the semiconductor light emitting device 1 . Phosphor layer 30 includes a plurality of particulate phosphors 31 . Phosphor 31 is excited by the radiated light from light-emitting layer 13, and emits light having a wavelength different from the radiated light.

A plurality of phosphors 31 are integrated by a bonding material 32 . The bonding material 32 transmits the radiated light of the light emitting layer 13 and the radiated light of the phosphor 31 . Here, the term "transmission" is not limited to the case where the transmittance is 100%, but also includes the case where part of the light is absorbed.

The semiconductor layer 15 has a first semiconductor layer 11 , a second semiconductor layer 12 , and a light emitting layer 13 . The light emitting layer 13 is disposed between the first semiconductor layer 11 and the second semiconductor layer 12 . The first semiconductor layer 11 and the second semiconductor layer 12 include gallium nitride, for example.

The first semiconductor layer 11 includes, for example, a base buffer layer and an n-type GaN layer. The second semiconductor layer 12 includes, for example, a p-type GaN layer. The light-emitting layer 13 contains a material that emits blue, violet, blue-violet, ultraviolet, and the like. The emission peak wavelength of the light emitting layer 13 is, for example, 430 to 470 nm.

The second side of the semiconductor layer 15 is processed into a concave-convex shape. The convex portion is a portion 15e including the light emitting layer 13 , and the concave portion is a portion 15f not including the light emitting layer 13 . The surface of the portion 15 e including the light emitting layer 13 is the surface of the second semiconductor layer 12 , and the p-side electrode 16 is provided on the surface of the second semiconductor layer 12 . The surface of the portion 15 f not containing the light emitting layer 13 is the surface of the first semiconductor layer 11 , and the n-side electrode 17 is provided on the surface of the first semiconductor layer 11 .

On the second side of the semiconductor layer 15 , the area of the portion 15 e containing the light emitting layer 13 is larger than the area of the portion 15 f not containing the light emitting layer 13 . In addition, the area of p-side electrode 16 provided on the surface of portion 15 e including light emitting layer 13 is larger than the area of n-side electrode 17 provided on the surface of portion 15 f not including light emitting layer 13 . Thereby, a wide light-emitting surface can be obtained, so that the light output can be improved.

As shown in FIG. 4 , the n-side electrode 17 has, for example, four straight portions, and one of the straight portions is provided with a contact portion 17 c protruding in the width direction of the straight portion. As shown in FIG. 3, the via hole 22a of the n-side wiring layer 22 is connected to the surface of the contact portion 17c.

As shown in FIG. 3 , the second side of the semiconductor layer 15 , the p-side electrode 16 and the n-side electrode 17 are covered with an insulating film (first insulating film) 18 . The insulating film 18 is, for example, an inorganic insulating film such as a silicon oxide film. The insulating film 18 is also provided on the side surfaces of the light emitting layer 13 and the second semiconductor layer 12 to cover these side surfaces.

In addition, the insulating film 18 is also provided on a side surface (side surface of the first semiconductor layer 11 ) 15 c continuous from the first side 15 a in the semiconductor layer 15 , and covers the side surface 15 c.

Furthermore, the insulating film 18 is also provided on the outer peripheral portion of the chip around the side surface 15 c of the semiconductor layer 15 . The insulating film 18 provided on the outer peripheral portion of the chip extends on the first side 15a in a direction away from the side surface 15c.

On the insulating film 18 on the second side, a p-side wiring layer 21 as a first wiring layer and an n-side wiring layer 22 as a second wiring layer are provided separately from each other. A plurality of first openings leading to the p-side electrode 16 and second openings leading to the contact portion 17 c of the n-side electrode 17 are formed in the insulating film 18 .

The p-side wiring layer 21 is provided on the insulating film 18 and inside the first opening. The p-side wiring layer 21 is electrically connected to the p-side electrode 16 via the via hole 21 a provided in the first opening.

The n-side wiring layer 22 is provided on the insulating film 18 and inside the second opening. The n-side wiring layer 22 is electrically connected to the contact portion 17c of the n-side electrode 17 via the via hole 22a provided in the second opening.

The p-side wiring layer 21 and the n-side wiring layer 22 occupy most of the second-side area and spread over the insulating film 18 . The p-side wiring layer 21 is connected to the p-side electrode 16 via a plurality of via holes 21 a.

In addition, the reflective film 51 covers the side surface 15 c of the semiconductor layer 15 via the insulating film 18 . The reflective film 51 is not in contact with the side surface 15 c and is not electrically connected to the semiconductor layer 15 . The reflective film 51 is separated from the p-side wiring layer 21 and the n-side wiring layer 22 . The reflective film 51 is reflective to the radiated light of the light emitting layer 13 and the radiated light of the phosphor 31 .

The reflective film 51 , the p-side wiring layer 21 and the n-side wiring layer 22 include, for example, a copper film. The reflective film 51 , the p-side wiring layer 21 and the n-side wiring layer 22 are simultaneously formed on the common metal film 60 shown in FIG. 5 by, for example, a plating method. The reflective film 51 , the p-side wiring layer 21 , and the n-side wiring layer 22 are each thicker than the metal film 60 .

The metal film 60 has a base metal film 61 , an adhesive layer 62 , and a seed layer 63 laminated in this order from the insulating film 18 side.

The underlying metal film 61 is, for example, an aluminum film that has high reflectivity to light emitted from the light emitting layer 13 .

The seed layer 63 is a copper film for depositing copper by plating. The adhesion layer 62 is, for example, a titanium film having excellent wettability to both aluminum and copper.

In addition, the reflective film 51 may be formed from the metal film 60 instead of forming a plated film (copper film) on the metal film 60 on the outer peripheral portion of the chip adjacent to the side surface 15 c of the semiconductor layer 15 . The reflective film 51 includes at least the aluminum film 61 , thereby having a high reflectance with respect to the radiated light of the light-emitting layer 13 and the radiated light of the phosphor 31 .

In addition, since the underlying metal film (aluminum film) 61 remains under the p-side wiring layer 21 and the n-side wiring layer 22, the aluminum film 61 is spread over most of the second side. Thereby, the amount of light directed toward the phosphor layer 30 side can be increased.

On the surface of the p-side wiring layer 21 opposite to the semiconductor layer 15 , a p-side metal pillar 23 is provided as a first metal pillar. The p-side wiring layer 21 and the p-side metal pillar 23 form a p-side wiring portion (first wiring portion) 41 .

On the surface of the n-side wiring layer 22 opposite to the semiconductor layer 15 , an n-side metal pillar 24 is provided as a second metal pillar. The n-side wiring layer 22 and the n-side metal pillar 24 form an n-side wiring portion (second wiring portion) 43 .

A resin layer 25 is provided as a second insulating film between the p-side wiring portion 41 and the n-side wiring portion 43 . Resin layer 25 is provided between p-side metal pillar 23 and n-side metal pillar 24 so as to be in contact with side surfaces of p-side metal pillar 23 and n-side metal pillar 24 . That is, the resin layer 25 is filled between the p-side metal pillar 23 and the n-side metal pillar 24 .

In addition, resin layer 25 is provided between p-side wiring layer 21 and n-side wiring layer 22 , between p-side wiring layer 21 and reflective film 51 , and between n-side wiring layer 22 and reflective film 51 .

The resin layer 25 is disposed around the p-side metal pillar 23 and the n-side metal pillar 24 , and covers the side surfaces of the p-side metal pillar 23 and the n-side metal pillar 24 .

In addition, the resin layer 25 is also provided between the outer peripheral portion of the chip adjacent to the side surface 15 c of the semiconductor layer 15 and between the plurality of semiconductor layers 15 separated from each other, and covers the reflective film 51 .

The end (surface) of the p-side metal pillar 23 on the opposite side to the p-side wiring layer 21 is exposed from the resin layer 25 and functions as a p-side external terminal 23a connectable to an external circuit. The end (surface) of the n-side metal pillar 24 on the opposite side to the n-side wiring layer 22 is exposed from the resin layer 25 and functions as an n-side external terminal 24 a connectable to an external circuit. The p-side external terminal 23 a and the n-side external terminal 24 a are bonded to the pads 81 to 83 of the mounting substrate 70 shown in FIG. 2( a ) via, for example, solder or a conductive bonding material as described below.

As shown in FIG. 2( b ), p-side external terminal 23 a is formed in, for example, a rectangle, and n-side external terminal 24 a is formed in a shape in which two corners of a rectangle having the same dimensions as p-side external terminal 23 a are cut off. Thereby, the polarity of the external terminal can be distinguished. In addition, the n-side external terminal 24a may be formed in a rectangular shape, and the p-side external terminal 23a may be formed in a shape obtained by cutting off corners of the rectangle.

The distance between the p-side external terminal 23 a and the n-side external terminal 24 a is wider than the distance between the p-side wiring layer 21 and the n-side wiring layer 22 on the insulating film 18 . The distance between the p-side external terminal 23 a and the n-side external terminal 24 a is greater than the spreading width of the solder during mounting. Thereby, a short circuit between the p-side external terminal 23a and the n-side external terminal 24a passing through the solder can be prevented.

On the other hand, the distance between the p-side wiring layer 21 and the n-side wiring layer 22 can be narrowed to the processing limit. Therefore, the area of the p-side wiring layer 21 and the contact area between the p-side wiring layer 21 and the p-side metal pillar 23 can be enlarged. Thereby, dissipation of heat from the light emitting layer 13 can be promoted.

In addition, the area of the p-side wiring layer 21 in contact with the p-side electrode 16 through the plurality of via holes 21a is larger than the area of the n-side wiring layer 22 in contact with the n-side electrode 17 through the via holes 22a. Thereby, the distribution of the current flowing in the light emitting layer 13 can be made uniform.

The area of the n-side wiring layer 22 extending on the insulating film 18 may be larger than the area of the n-side electrode 17 . Furthermore, the area of the n-side metal pillar 24 provided on the n-side wiring layer 22 (the area of the n-side external terminal 24 a ) can be made larger than the n-side electrode 17 . Thereby, the area of the n-side external terminal 24a sufficient for mounting can be ensured, and the area of the n-side electrode 17 can be reduced. That is, the area of the portion 15f not containing the light-emitting layer 13 in the semiconductor layer 15 can be reduced, and the area of the portion (light-emitting region) 15e including the light-emitting layer 13 can be enlarged, thereby improving light output.

The first semiconductor layer 11 is electrically connected to the n-side metal pillar 24 via the n-side electrode 17 and the n-side wiring layer 22 . The second semiconductor layer 12 is electrically connected to the p-side metal pillar 23 via the p-side electrode 16 and the p-side wiring layer 21 .

The thickness of the p-side metal pillar 23 (the thickness in the direction connecting the p-side wiring layer 21 and the p-side external terminal 23 a ) is thicker than the thickness of the p-side wiring layer 21 . The thickness of the n-side metal pillar 24 (the thickness in the direction connecting the n-side wiring layer 22 and the n-side external terminal 24 a ) is thicker than the thickness of the n-side wiring layer 22 . Each of the p-side metal pillar 23 , the n-side metal pillar 24 , and the resin layer 25 is thicker than the semiconductor layer 15 .

The aspect ratio (ratio of the thickness to the planar size) of the metal pillars 23 and 24 may be 1 or more or less than 1. That is, the metal pillars 23 and 24 may be thicker or thinner than their planar dimensions.

The thickness of the support 100 including the p-side wiring layer 21, the n-side wiring layer 22, the p-side metal pillar 23, the n-side metal pillar 24, and the resin layer 25 is greater than that of the semiconductor layer 15, the p-side electrode 16, and the n-side electrode. The thickness of the light emitting element (LED (Light Emitting Diode, light emitting diode) chip) 10 of 17 is thick.

The semiconductor layer 15 is formed on an unillustrated substrate by an epitaxial growth method. The substrate is removed after formation of the carrier 100 , the semiconductor layer 15 being free of the substrate on the first side 15 a. The semiconductor layer 15 is not supported by a rigid plate substrate, but is supported by a support body 100 including a composite body of the metal pillars 23 and 24 and the resin layer 25 .

As the material of the p-side wiring portion 41 and the n-side wiring portion 43, for example, copper, gold, nickel, silver, or the like can be used. If copper among these materials is used, good thermal conductivity, high migration resistance, and adhesion to insulating materials can be improved.

The resin layer 25 reinforces the p-side metal pillar 23 and the n-side metal pillar 24 . For the resin layer 25 , it is desirable to use a resin layer having the same or close thermal expansion coefficient as that of the mounting substrate 70 . Examples of such resin layer 25 include resins mainly containing epoxy resins, resins mainly containing silicone resins, and resins mainly containing fluororesins.

In addition, the base resin in the resin layer 25 contains a light-shielding material (light absorber, light reflector, light-scatterer, etc.), and the resin layer 25 has light-shielding properties for light emitted by the light-emitting layer 13 . Thereby, light leakage from the side surface and mounting surface side of the support body 100 can be suppressed.

Due to the thermal cycle when the semiconductor light emitting device 1 is mounted on the mounting substrate 70, the stress due to the solder that joins the p-side external terminal 23a and the n-side external terminal 24a to the pads 81 to 83 of the mounting substrate 70 is applied. to the semiconductor layer 15. The p-side metal pillar 23, the n-side metal pillar 24, and the resin layer 25 absorb and relax the stress. In particular, by using the resin layer 25 softer than the semiconductor layer 15 as a part of the support 100, the stress relaxation effect can be enhanced.

The reflective film 51 is separated from the p-side wiring portion 41 and the n-side wiring portion 43 . Therefore, the stress applied to the p-side metal pillar 23 and the n-side metal pillar 24 during mounting is not transmitted to the reflective film 51 . Therefore, peeling of the reflective film 51 can be suppressed. In addition, stress applied to the side surface 15c of the semiconductor layer 15 can be suppressed.

The substrate for forming the semiconductor layer 15 is removed from the semiconductor layer 15 . As a result, the semiconductor light emitting device 1 has a low profile. In addition, by removing the substrate, fine unevenness can be formed on the first side 15a of the semiconductor layer 15, thereby improving the light extraction efficiency.

For example, wet etching using an alkaline solution is performed on the first side 15a to form minute unevenness. Thus, the total reflection component of the first side 15a can be reduced, thereby improving the light extraction efficiency.

After removing the substrate, the phosphor layer 30 is formed on the first side 15 a via the insulating film 19 . The insulating film 19 improves the adhesion between the semiconductor layer 15 and the phosphor layer 30 and is, for example, a silicon oxide film or a silicon nitride film.

Phosphor layer 30 has a structure in which a plurality of particulate phosphors 31 are dispersed in binder 32 . For the bonding material 32, for example, silicone resin can be used.

Phosphor layer 30 is also formed on the outer peripheral portion of the chip around side surface 15 c of semiconductor layer 15 and on the region between light emitting elements 10 and 10 . A phosphor layer 30 is provided on an insulating film (for example, a silicon oxide film) 18 in a region between the outer periphery of the chip and the light emitting element 10 .

In the region between the semiconductor layers 15 (inter-chip region), the insulating film 18 is not limited to being continuous, but may be divided as shown in FIG. 13 . Cracks may occur in the insulating film 18 depending on the coefficient of thermal expansion of the resin layer 25 , but the cracks can be suppressed by dividing the insulating film 18 in the interchip region by patterning as shown in FIG. 13 .

Phosphor layer 30 is limited to the upper region side of light emitting element 10 , and is formed without wrapping around the second side of semiconductor layer 15 , around metal pillars 23 , 24 , and the side surface of support 100 . The side surfaces of the phosphor layer 30 are aligned with the side surfaces of the support 100 (side surfaces of the resin layer 25 ).

On the side of the mounting surface where light is not extracted to the outside, the phosphor layer 30 is not redundantly formed, thereby achieving cost reduction. In addition, even if there is no substrate on the first side 15a, the heat of the light emitting layer 13 can be dissipated to the mounting substrate 70 side through the p-side wiring layer 21 and the n-side wiring layer 22 extending on the second side. Despite its small size, it has excellent heat dissipation.

In general flip-chip mounting, after mounting an LED chip on a mounting substrate via bumps or the like, a phosphor layer is formed so as to cover the entire chip. Alternatively, resin is underfilled between the bumps.

On the other hand, according to the embodiment, the resin layer 25 different from the phosphor layer 30 is provided around the p-side metal pillar 23 and around the n-side metal pillar 24 in the state before mounting, and the mounting surface side can be provided with a suitable surface. properties for stress relaxation. In addition, since the resin layer 25 is already provided on the mounting surface side, underfill after mounting is unnecessary.

A layer designed with priority in light extraction efficiency, color conversion efficiency, light distribution characteristics, etc. is provided on the first side 15a, and a layer with priority in stress relaxation during mounting or the characteristics of a support as a substitute substrate is provided on the mounting surface side. . For example, the resin layer 25 has a structure in which fillers such as silica particles are densely filled in a base resin, and is adjusted to have an appropriate hardness as a support.

The light emitted from the light emitting layer 13 toward the first side 15 a enters the phosphor layer 30 , a part of the light excites the phosphor 31 , and white light is obtained as mixed light of light from the light emitting layer 13 and light from the phosphor 31 .

Here, if there is a substrate on the first side 15a, light that does not enter the phosphor layer 30 and leaks to the outside from the side of the substrate occurs. That is, the light of the light-emitting layer 13 with a strong color leaks from the side of the substrate, which may cause a phenomenon such as color separation or a phenomenon in which a blue halo can be seen on the outer edge side when the phosphor layer 30 is viewed from the upper surface. Uneven color.

On the other hand, according to the embodiment, since there is no substrate for the growth of the semiconductor layer 15 between the first side 15a and the phosphor layer 30, it is possible to prevent the strong color of light from the light emitting layer 13 from Color separation or color unevenness caused by leakage from the side of the substrate.

Furthermore, according to the embodiment, the reflective film 51 is provided on the side surface 15 c of the semiconductor layer 15 via the insulating film 18 . Light from the light emitting layer 13 toward the side surface 15 c of the semiconductor layer 15 is reflected by the reflective film 51 without leaking to the outside. Therefore, complementary to the feature of no substrate on the first side 15a, color separation or color unevenness due to light leakage from the side surfaces of the semiconductor light emitting device can be prevented.

The insulating film 18 provided between the reflective film 51 and the side surface 15 c of the semiconductor layer 15 prevents metal contained in the reflective film 51 from diffusing into the semiconductor layer 15 . Thereby, metal contamination of the semiconductor layer 15 such as GaN can be prevented, and deterioration of the semiconductor layer 15 can be prevented.

In addition, the insulating film 18 provided between the reflective film 51 and the phosphor layer 30 and between the resin layer 25 and the phosphor layer 30 improves the adhesion between the reflective film 51 and the phosphor layer 30 and the adhesion between the resin layer 25 and the phosphor layer. Adhesiveness of layer 30.

The insulating film 18 is, for example, an inorganic insulating film such as a silicon oxide film or a silicon nitride film. That is, the first side 15a, the second side, the side surface 15c of the first semiconductor layer 11, the side surface of the second semiconductor layer 12, and the side surface of the light emitting layer 13 of the semiconductor layer 15 are covered with an inorganic insulating film. The inorganic insulating film surrounds the semiconductor layer 15 and seals the semiconductor layer 15 from metal, moisture, and the like.

Phosphor layer 30 extends across the plurality of light emitting elements 10 . A lens 50 is optionally provided on the phosphor layer 30 . The lens 50 is formed of, for example, transparent resin. Although a convex lens is illustrated in FIG. 3 , a concave lens may also be used.

A plurality of light emitting elements 10 are encapsulated by a common resin layer 25 . Therefore, an integral lens can be formed so as to cover the plurality of light emitting elements 10 . According to the multi-chip package of the embodiment, it is possible to control the light distribution characteristics using the shape of the lens, which cannot be realized by forming the lens on the individual package separated for each light emitting element.

The steps of forming the light-emitting element 10 , the support 100 , the phosphor layer 30 and the lens 50 are performed in the state of a wafer including a plurality of semiconductor layers 15 . After that, the wafer is separated into a plurality of semiconductor light emitting devices 1 including at least two light emitting elements 10 (semiconductor layers 15). Cutting is performed in a region (cut region) between the semiconductor layer 15 and the semiconductor layer 15 . By arbitrarily selecting the dicing area, the number of light-emitting elements 10 (semiconductor layers 15 ) included in one semiconductor light-emitting device can be selected.

Since the steps up to dicing are collectively performed in the wafer state, it is not necessary to form a wiring layer, form a pillar, encapsulate with a resin layer, and form a phosphor layer for each semiconductor light emitting device obtained after separation. Formation can greatly reduce the cost.

After forming the support body 100 and the phosphor layer 30 in a wafer state, they are cut so that the side faces of the phosphor layer 30 are aligned with the side faces of the support body 100 (the side faces of the resin layer 25 ), and these side faces form the separated semiconductor light emitting diodes. Side of device 1. Therefore, it is also possible to provide a small semiconductor light-emitting device in conjunction with the absence of a substrate.

According to an embodiment, an optical layer is arranged on the first side 15 a of the semiconductor layer 15 . The light emitting element 10 including the semiconductor layer 15 and the electrodes 16 and 17 is provided between the optical layer and the mounting surface (the surface on which the external terminals 23 a and 24 a are provided).

The optical layer is not limited to a phosphor layer, and may be a scattering layer. The scattering layer includes a plurality of particulate scattering materials (such as a titanium compound) that scatters the radiated light of the luminescent layer 13, and a bonding material (such as a resin layer) that integrates the plurality of scattering materials and transmits the radiated light of the luminescent layer 13. ).

The semiconductor light emitting device 1 is mounted on a mounting substrate 70 shown in FIG. 2( a ). The mounting substrate 70 has a first pad 81 , a second pad 82 , and a third pad 83 . The first pad 81 , the second pad 82 and the third pad 83 are formed of metal (such as copper). The first pad 81, the second pad 82, and the third pad 83 are formed on the insulator. Surroundings of the first pad 81 , the second pad 82 and the third pad 83 are respectively surrounded by insulators.

The first pad 81 , the second pad 82 and the third pad 83 are spaced apart from each other in the first direction X. A third pad 83 is provided between the first pad 81 and the second pad 82 .

The first pad 81 is in a congruent pattern relationship with the p-side external terminal 23a of the semiconductor light emitting device 1 , and the second pad 82 is in a congruent pattern relationship with the n-side external terminal 24a of the semiconductor light emitting device 1 .

The first pad 81 is formed in a rectangle having a long side extending in a second direction Y orthogonal to the first direction X. As shown in FIG. The second pad 82 is formed in a shape obtained by cutting two corners of a rectangle having the same size as the rectangle of the first pad 81 . Thereby, the polarity of the pad can be distinguished.

In addition, when the n-side external terminal 24a of the semiconductor light emitting device 1 is formed into a rectangle, and the p-side external terminal 23a is formed into a shape obtained by cutting off the corners of the rectangle, the second pad 82 can be formed into a rectangle, and the first pad 82 can be formed into a rectangle. The pad 81 has a shape obtained by cutting off corners of a rectangle.

The third pad 83 is formed in, for example, a quadrangular shape. The area of the third pad 83 is larger than the area of the first pad 81 and the area of the second pad 82 . The first pad 81 and the second pad 82 are arranged symmetrically with respect to the center line C that divides the third pad 83 into two equal parts in the first direction X.

As shown in FIG. 2( b ), in the semiconductor light emitting device 1 , two light emitting elements 10 are arranged along the first direction X. As shown in FIG. Each light emitting element 10 has one p-side external terminal 23a and one n-side external terminal 24a. In one light emitting element 10 , the p-side external terminal 23 a and the n-side external terminal 24 a are arranged along the first direction X.

Therefore, the four external terminals 23a, 24a of the two light emitting elements 10 are arranged along the first direction X. As shown in FIG. The p-side external terminals 23 a and the n-side external terminals 24 a are alternately arranged along the first direction X.

In FIG. 2( b ), the p-side external terminal 23a of the light-emitting element 10 on the left is connected to the p-side electrode 16 of the light-emitting element 10 on the left, and the n-side external terminal 24a of the light-emitting element 10 on the left is connected to the left side. The n-side electrode 17 of the light emitting element 10.

In FIG. 2( b ), the p-side external terminal 23a of the light-emitting element 10 on the right is connected to the p-side electrode 16 of the light-emitting element 10 on the right, and the n-side external terminal 24a of the light-emitting element 10 on the right is connected to the right side. The n-side electrode 17 of the light emitting element 10.

Among the four external terminals 23a and 24a arranged in the first direction X, the p-side external terminal 23a at one end in the first direction X is bonded to the first pad 81 of the mounting substrate 70 via, for example, solder. That is, in FIG. 2( b ), the p-side external terminal 23 a of the light emitting element 10 on the left is bonded to the first pad 81 .

Among the four external terminals 23a and 24a, the n-side external terminal 24a at the other end in the first direction X is bonded to the second pad 82 of the mounting substrate 70 via, for example, solder. That is, in FIG. 2( b ), the n-side external terminal 24 a of the light emitting element 10 on the right is bonded to the second pad 82 .

The two external terminals 23a, 24a between the p-side external terminal 23a bonded to the left end of the first pad 81 and the n-side external terminal 24a bonded to the right end of the second pad 82 are connected to the third terminal of the mounting substrate 70 via solder. Pad 83 engages. These two external terminals 23a, 24a are bonded to a common third pad 83 .

Therefore, among the two adjacent light emitting elements 10 in the first direction X, the n-side external terminal 24a of the light emitting element 10 of one (the left side in FIG. ) The p-side external terminal 23 a of the light emitting element 10 on the right side is bonded to the common third pad 83 .

An anode potential is applied to the first pad 81 through an unillustrated wiring formed on the mounting substrate 70 . A cathode potential lower than an anode potential is given to the second pad 82 by an unillustrated wiring formed on the mounting substrate 70 .

The third pad 83 is not electrically connected to any one, and the potential of the third pad 83 floats. The n-side external terminal 24 a of one (left) light emitting element 10 and the p-side external terminal 23 a of the other (right) light emitting element 10 are electrically connected via the third pad 83 .

The current passes through the first pad 81, the p-side external terminal 23a at the left end bonded to the first pad 81, the p-side metal post 23 of the light-emitting element 10 on the left, the p-side wiring layer 21, the p-side electrode 16, and the first pad 81. The second semiconductor layer 12 is supplied to the light-emitting layer 13, and then flows through the first semiconductor layer 11, the n-side electrode 17, the n-side wiring layer 22, the n-side metal column 24, and the n-side external terminal of the light-emitting element 10 on the left. 24a.

Furthermore, the current is supplied to the right side through the third pad 83, the p-side external terminal 23a of the light-emitting element 10 on the right side, the p-side metal post 23, the p-side wiring layer 21, the p-side electrode 16, and the second semiconductor layer 12. The light-emitting layer 13 of the light-emitting element 10 on the right side, and then flows through the first semiconductor layer 11, the n-side electrode 17, the n-side wiring layer 22, the n-side metal pillar 24, the n-side external terminal 24a, And the second pad 82 to which the n-side external terminal 24a is bonded.

That is, two light emitting elements 10 are connected in series between the first pad 81 and the second pad 82 as schematically represented by a circuit symbol of a diode in FIG. 1 .

The two light emitting elements 10 are electrically connected through the third pad 83 formed on the mounting substrate 70 . The structure of the semiconductor light-emitting device 1 in a multi-chip package can be easily formed without connecting the two light-emitting elements 10 through a wiring layer in the package.

The area of the third pad 83 is larger than the area of the first pad 81 and the area of the second pad 82 . In addition, the area of the third pad 83 is larger than the area obtained by adding the area of the first pad 81 and the area of the second pad 82 . Furthermore, the area of the third pad 83 is larger than the area obtained by adding the area of one p-side external terminal 23a and the area of one n-side external terminal 24a. With such a wide third pad 83 , the heat of the semiconductor light emitting device 1 can be efficiently dissipated to the mounting substrate 70 side.

In order not to easily cause a short circuit via solder, the distance between the first pad 81 and the third pad 83, that is, the distance between the p-side external terminal 23a and the n-side external terminal 24a of the light-emitting element 10 on the left in FIG. The distance is preferably 200 μm or more. Similarly, the distance between the second pad 82 and the third pad 83, that is, the p-side external terminal 23a and the n-side external terminal 24a of the light-emitting element 10 on the right side in FIG. The distance between them is also preferably 200 μm or more.

On the other hand, since the n-side external terminal 24a of one (left) light emitting element 10 and the p-side external terminal 23a of the other (right) light emitting element 10 are bonded to the common third pad 83, these adjacent The distance between the adjacent external terminals 23a and 24a of the light emitting element 10 is not restricted, and the degree of freedom in design is high.

When two semiconductor light-emitting devices of a single-chip structure including one light-emitting element are adjacently mounted on a mounting substrate in a package, there must be a gap between the mounted semiconductor light-emitting devices so that the semiconductor light-emitting devices can be kept. The collet does not collide with adjacent semiconductor light emitting devices. Therefore, even if the size of the package of each semiconductor light emitting device is miniaturized, the mounting space is still limited by the size of the collet.

On the other hand, according to the embodiment, since a plurality of light emitting elements 10 can be brought close together in one package, the mounting space on the mounting substrate can be reduced compared to mounting a plurality of singulated light emitting elements one by one.

Fig. 6 is a schematic plan view showing another example of the pad of the mounting substrate.

According to FIG. 6 , the fourth pad 84 is provided integrally with the third pad 83 , so that the heat dissipation area is larger than that shown in FIG. 2( a ). The fourth pad 84 extends from the third pad 83 in the second direction Y so as to avoid the first pad 81 and the second pad 82 .

Fig. 7 is a schematic top view of a light emitting unit according to another embodiment.

FIG. 8( a ) is a schematic plan view of a mounting substrate 70 according to another embodiment.

Fig. 8(b) is a schematic plan view of a semiconductor light emitting device 1 according to another embodiment.

FIG. 7 , FIG. 8( a ) and FIG. 8( b ) are diagrams respectively corresponding to FIG. 1 , FIG. 2( a ) and FIG. 2( b ), and the same symbols are attached to the same elements.

The semiconductor light emitting device 1 shown in FIG. 8( b ) has, for example, four light emitting elements 10 . The four light emitting elements 10 are encapsulated by the resin layer 25 at the wafer level, and the resin layer 25 integrally supports the four light emitting elements 10 .

Two groups (rows) of light emitting elements 10 arranged in the first direction X are arranged in two rows in the second direction Y perpendicular to the first direction X.

In a group (column) of two light emitting elements 10 arranged in the first direction X, p-side external terminals 23 a and n-side external terminals 24 a are arranged in the first direction X alternately.

One first pad 81 , one second pad 82 , and two third pads 83 are formed on the mounting substrate 70 .

The two third pads 83 are spaced apart from each other along the second direction Y between the first pad 81 and the second pad 82 .

Among the four external terminals 23a and 24a arranged in a row along the first direction X, the p-side external terminal 23a at one end in the first direction X is bonded to the first pad 81 of the mounting substrate 70 via, for example, solder. That is, in FIG. 8( b ), the two p-side external terminals 23 a of the two light emitting elements 10 on the left are bonded to the first pad 81 .

Among the four external terminals 23a and 24a arranged in a row along the first direction X, the n-side external terminal 24a at the other end in the first direction X is bonded to the second pad 82 of the mounting substrate 70 via, for example, solder. That is, in FIG. 8( b ), the two n-side external terminals 24 a of the two light emitting elements 10 on the right are bonded to the second pad 82 .

The external terminals 23a, 24a between the p-side external terminal 23a bonded to the left end of the first pad 81 and the n-side external terminal 24a bonded to the right end of the second pad 82 are connected to the third pad 83 of the mounting substrate 70 via solder. join.

In FIG. 8( b ), among the two light-emitting elements 10 adjacent in the first direction X in the upper column, the n-side external terminal 24a of one (left side) light-emitting element 10 and the other (right side) ) The p-side external terminal 23 a of the light emitting element 10 is bonded to one of the two third pads 83 .

In FIG. 8( b ), among the two light-emitting elements 10 adjacent in the first direction X in the lower column, the n-side external terminal 24a of one (left side) light-emitting element 10 and the other (right side) ) The p-side external terminal 23 a of the light emitting element 10 is bonded to the other of the two third pads 83 .

An anode potential is applied to the first pad 81 through an unillustrated wiring formed on the mounting substrate 70 . A cathode potential lower than an anode potential is given to the second pad 82 by an unillustrated wiring formed on the mounting substrate 70 .

The third pad 83 is not electrically connected to any one, and the potential of the third pad 83 floats. The n-side external terminal 24 a of one (left) light emitting element 10 adjacent in the first direction X is electrically connected to the p-side external terminal 23 a of the other (right) light emitting element 10 via the third pad 83 .

Therefore, two light emitting elements 10 arranged in the first direction X are connected in series between the first pad 81 and the second pad 82 as schematically indicated by a circuit symbol of a diode in FIG. 7 . In addition, the upper row and the lower row are connected in parallel between the first pad 81 and the second pad 82 .

Because the n-side external terminal 24a of one (left) light-emitting element 10 adjacent in the first direction X and the p-side external terminal 23a of the other (right) light-emitting element 10 are bonded to the common third pad 83 Therefore, the distance between the adjacent external terminals 23a, 24a of these adjacent light-emitting elements 10 is not restricted, and the degree of freedom in design is high.

In addition, since a plurality of light emitting elements 10 can be brought close together in one package, the mounting space on the mounting substrate can be reduced compared to mounting a plurality of singulated light emitting elements one by one.

Fig. 9 is a schematic plan view of a light emitting unit according to yet another embodiment.

Fig. 10(a) is a schematic plan view of a mounting substrate 70 according to still another embodiment.

Fig. 10(b) is a schematic plan view of a semiconductor light emitting device 1 according to still another embodiment.

FIG. 9 , FIG. 10( a ) and FIG. 10( b ) are diagrams respectively corresponding to FIG. 7 , FIG. 8( a ) and FIG. 8( b ), and the same reference numerals are attached to the same elements.

The semiconductor light emitting device 1 shown in FIG. 10( b ) has, for example, six light emitting elements 10 . The six light emitting elements 10 are encapsulated by the resin layer 25 at the wafer level, and the resin layer 25 integrally supports the six light emitting elements 10 .

Three light emitting elements 10 are arranged in the first direction X. Groups (rows) of three light emitting elements 10 arranged in the first direction X are arranged in two rows in a second direction Y perpendicular to the first direction X. FIG.

In a group (column) of three light emitting elements 10 arranged in the first direction X, p-side external terminals 23 a and n-side external terminals 24 a are arranged in the first direction X alternately.

Two first pads 81 , two second pads 82 , and four third pads 83 are formed on the mounting substrate 70 .

The two first pads 81 are arranged spaced apart from each other in the second direction Y. The two second pads 82 are arranged spaced apart from each other in the second direction Y. Alternatively, one first pad 81 connected in the second direction Y and one second pad 82 connected in the second direction Y may be used like the example shown in FIG. 8( a ). In this case, the pad area increases and heat dissipation improves.

Between the first pad 81 and the second pad 82, four third pads 83 are provided by combining two third pads 83 arranged in the first direction X and two third pads 83 arranged in the second direction Y. .

Among the six external terminals 23a, 24a of the three light emitting elements 10 arranged in a row along the first direction X, the p-side external terminal 23a at one end in the first direction X is connected to the first pad 81 of the mounting substrate 70 via, for example, solder. join. That is, in FIG. 10( b ), the two p-side external terminals 23 a of the left end two light emitting elements 10 arranged in the second direction Y are bonded to the first pad 81 .

Among the six external terminals 23a and 24a arranged in a row along the first direction X, the n-side external terminal 24a at the other end in the first direction X is bonded to the second pad 82 of the mounting substrate 70 via, for example, solder. That is, in FIG. 10( b ), the two n-side external terminals 24 a of the two light emitting elements 10 at the right end arranged in the second direction Y are bonded to the second pad 82 .

The external terminals 23a, 24a between the p-side external terminal 23a bonded to the left end of the first pad 81 and the n-side external terminal 24a bonded to the right end of the second pad 82 are connected to the third pad 83 of the mounting substrate 70 via solder. join.

In FIG. 10( b ), among the two light-emitting elements 10 adjacent to the left end of the upper row and its right side, the n-side external terminal 24a of one (left side) light-emitting element 10 and the other (right side) The p-side external terminal 23a of the light emitting element 10 is bonded to one of the two third pads 83 next to the first pad 81 shown in FIG. 10( a ).

In Fig. 10(b), among the two light-emitting elements 10 adjacent to the left end and the right side of the lower column, the n-side external terminal 24a of one (left side) light-emitting element 10, and the other (right side) The p-side external terminal 23 a of the light emitting element 10 is bonded to the other of the two third pads 83 next to the first pad 81 shown in FIG. 10( a ).

In FIG. 10( b ), among the two light-emitting elements 10 adjacent to the right end of the upper column and its left side, the n-side external terminal 24a of one (left side) light-emitting element 10 and the other (right side) The p-side external terminal 23 a of the light emitting element 10 is bonded to one of the two third pads 83 next to the second pad 82 shown in FIG. 10( a ).

In FIG. 10( b ), among the two light-emitting elements 10 adjacent to the right end and left side of the lower column, the n-side external terminal 24a of one (left side) light-emitting element 10 and the other (right side) The p-side external terminal 23 a of the light emitting element 10 is bonded to the other of the two third pads 83 next to the second pad 82 shown in FIG. 10( a ).

An anode potential is applied to the first pad 81 through an unillustrated wiring formed on the mounting substrate 70 . A cathode potential lower than an anode potential is given to the second pad 82 by an unillustrated wiring formed on the mounting substrate 70 .

The third pad 83 is not electrically connected to any one, and the potential of the third pad 83 floats. The n-side external terminal 24a (p-side external terminal 23a) of one of the two light-emitting elements 10 adjacent in the first direction X is connected to the p-side external terminal 23a (n-side external terminal 23a) of the other light-emitting element 10. 24a) is electrically connected via the third pad 83 .

Therefore, three light emitting elements 10 arranged in the first direction X are connected in series between the first pad 81 and the second pad 82 as schematically indicated by the circuit symbols of diodes in FIG. 9 .

Because the n-side external terminal 24a (p-side external terminal 23a) of one of the light-emitting elements 10 adjacent in the first direction X and the p-side external terminal 23a (n-side external terminal 24a) of the other light-emitting element 10 are connected to the common Therefore, the distance between the adjacent external terminals 23a, 24a of these adjacent light-emitting elements 10 is not restricted, and the degree of freedom in design is high.

In addition, since a plurality of light emitting elements 10 can be brought close together in one package, the mounting space on the mounting substrate can be reduced compared to mounting a plurality of singulated light emitting elements one by one.

FIG. 11 is a schematic cross-sectional view of a semiconductor light emitting device 2 according to another embodiment.

FIG. 12 is a schematic plan view of the semiconductor light emitting device 2 . FIG. 12 shows the mounting surface of the semiconductor light emitting device 2 and corresponds to the bottom view of the semiconductor light emitting device 2 shown in FIG. 11 .

The semiconductor light emitting device 2 is different from the semiconductor light emitting device 1 of the above-mentioned embodiment in that it has the third metal pillar 26 and the third external terminal 26a. In the semiconductor light emitting device 2 , the same elements as those in the semiconductor light emitting device 1 are denoted by the same reference numerals, and detailed descriptions of the elements are omitted.

The semiconductor light emitting device 2 has a plurality of light emitting elements 10 . In the example shown in FIGS. 11 and 12 , the semiconductor light emitting device 2 has, for example, two light emitting elements 10 . The plurality of light emitting elements 10 are encapsulated by the resin layer 25 at the wafer level, and the resin layer 25 integrally supports the plurality of light emitting elements 10 .

The outer shape of the semiconductor light emitting device 2 viewed from the upper surface or the mounting surface side opposite to the upper surface is, for example, a rectangle. For example, two light emitting elements 10 are arranged in the long side direction (first direction X) of the rectangle.

One of the two light-emitting elements 10 adjacent in the first direction X has a p-side metal pillar 23 and a p-side external terminal 23a, but does not have an n-side metal pillar 24 and an n-side external terminal 24a. In contrast, the other light emitting element 10 does not have the p-side metal pillar 23 and the p-side external terminal 23a, but has the n-side metal pillar 24 and the n-side external terminal 24a.

Two adjacent light emitting elements 10 in the first direction X share the third metal post 26 . The third metal post 26 is formed of the same material as the p-side metal post 23 and the n-side metal post 24 , and is formed simultaneously by the same method (eg, plating method).

The third metal pillar 26 connects the n-side wiring layer 22 of one of the two light-emitting elements 10 adjacent in the first direction X to the p-side wiring layer 21 of the other light-emitting element 10 .

The end portion (lower surface in FIG. 11 ) of the third metal post 26 is exposed from the resin layer 25 and functions as a third external terminal 26a.

As shown in FIG. 12 , two light emitting elements 10 are arranged along the first direction X. As shown in FIG. The p-side external terminal 23a of one light emitting element 10 is disposed at one end in the first direction X, and the n-side external terminal 24a of the other light emitting element 10 is disposed at the other end in the first direction X. The third external terminal 26 a is provided between the p-side external terminal 23 a and the n-side external terminal 24 a at both ends in the first direction X.

The third external terminal 26a is formed in, for example, a quadrangular shape. The area of the third external terminal 26a is larger than the area of the p-side external terminal 23a and the area of the n-side external terminal 24a. The p-side external terminal 23 a and the n-side external terminal 24 a are arranged symmetrically with respect to the center line C that divides the third external terminal 26 a into two equal parts in the first direction X.

In FIGS. 11 and 12, the p-side external terminal 23a of the left light-emitting element 10 is connected to the p-side electrode 16 of the left light-emitting element 10, and the n-side electrode 17 of the left light-emitting element 10 is connected to the third external terminal. 26a.

In FIGS. 11 and 12, the n-side external terminal 24a of the right light-emitting element 10 is connected to the n-side electrode 17 of the right light-emitting element 10, and the p-side electrode 16 of the right light-emitting element 10 is connected to the third external terminal. 26a.

The semiconductor light emitting device 2 shown in FIGS. 11 and 12 can be mounted on, for example, a mounting substrate as shown in FIG. 2( a ).

The p-side external terminal 23 a is bonded to the first pad 81 of the mounting substrate 70 via, for example, solder. The n-side external terminal 24 a is bonded to the second pad 82 of the mounting substrate 70 via, for example, solder. The third external terminal 26 a between the p-side external terminal 23 a and the n-side external terminal 24 a is bonded to the third pad 83 of the mounting substrate 70 via solder.

An anode potential is applied to the first pad 81 through an unillustrated wiring formed on the mounting substrate 70 . A cathode potential lower than an anode potential is given to the second pad 82 by an unillustrated wiring formed on the mounting substrate 70 .

The third pad 83 is not electrically connected to any one, and the potential of the third pad 83 floats. The n-side electrode 17 of one (left) light-emitting element 10 is electrically connected to the p-side electrode 16 of the other (right) light-emitting element 10 via the third metal pillar 26, the third external terminal 26a, and the third pad 83 .

The current passes through the first pad 81, the p-side external terminal 23a of one of the light emitting elements 10 bonded to the first pad 81, the p-side metal post 23, the p-side wiring layer 21, the p-side electrode 16, and the second semiconductor layer. 12 is supplied to the light-emitting layer 13, and then flows through the first semiconductor layer 11, the n-side electrode 17, the n-side wiring layer 22, the third metal pillar 26, and the third external terminal 26a of one of the light-emitting elements 10.

Furthermore, the current is supplied to the light emitting layer 13 of the other light emitting element 10 via the third pad 83, the p-side wiring layer 21 of the other light emitting element 10, the p-side electrode 16, and the second semiconductor layer 12, and then flows through the other light emitting element 10. The first semiconductor layer 11 , the n-side electrode 17 , the n-side wiring layer 22 , the n-side metal pillar 24 , the n-side external terminal 24 a , and the second pad 82 of one light emitting element 10 .

That is, the two light emitting elements 10 of the semiconductor light emitting device 2 are connected in series between the first pad 81 and the second pad 82 as schematically indicated by the circuit symbol of a diode in FIG. 12 .

The two light emitting elements 10 are electrically connected by the third metal post 26 including the third external terminal 26a. When the two light emitting elements 10 are not mounted on the mounting substrate 70 , they are electrically connected by the third metal pillar 26 formed of, for example, copper, which has higher thermal conductivity than solder, without solder. Furthermore, the two light emitting elements 10 are connected by the third metal pillar 26 thicker than the wiring layers 21 and 22 in the package.

That is, a plurality of chips are connected by thick metal pillars 26 having better heat dissipation than solder or a thinner wiring layer. Therefore, the difference in temperature characteristics (difference in light emission characteristics) among a plurality of chips (semiconductor layer 15 ) can be made small.

In addition, the heat of the light emitting element 10 can be efficiently released to the mounting substrate 70 side through the third external terminal 26a and the third pad 83 that are larger than the p-side external terminal 23a and the n-side external terminal 24a.

In addition, since a plurality of light emitting elements 10 can be brought close together in one package, the mounting space on the mounting substrate can be reduced compared to mounting a plurality of singulated light emitting elements one by one.

The number of light emitting elements 10 (semiconductor layers 15 ) included in one semiconductor light emitting device having a multi-chip package structure is not limited to the number shown in the above embodiment, and can be arbitrarily selected by selecting a dicing area.

In the structure of FIG. 11 , the insulating film 18 is not limited to be continuous in the region between the semiconductor layers 15 (inter-chip region), but may be divided as shown in FIG. 14 . Cracks can be suppressed by dividing the insulating film 18 in the interchip region by patterning.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope or gist of the invention, and are included in the invention described in the claims and their equivalents.

[explanation of the symbol]

1, 2 semiconductor light emitting device

10 light emitting elements

13 luminous layer

15 semiconductor layer

16 p side electrode

17 n side electrode

23a p side external terminal

24a n-side external terminal

25 layers of resin

26a Third external terminal

30 phosphor layer

70 mounting substrate

81 first pad

82 second pad

83 third pad

Claims (9)

1. A light-emitting unit, characterized in that it comprises: a mounting substrate having a first pad, a second pad, and a third pad disposed between the first pad and the second pad; and A semiconductor light emitting device including a plurality of light emitting elements each having two external terminals, and a resin layer integrally supporting the plurality of light emitting elements; and The plurality of light emitting elements include n light emitting elements arranged in a first direction, where n is an integer greater than 2; The 2×n external terminals of the n light emitting elements are arranged in the first direction; Among the 2×n external terminals, an external terminal at one end in the first direction is bonded to the first pad, an external terminal at the other end in the first direction is bonded to the second pad, and the one end An external terminal between the external terminal at the other end and the external terminal at the other end is engaged with the third pad. 2. The light emitting unit according to claim 1, characterized in that: each of the light emitting elements has a first electrode and a second electrode; The 2×n external terminals of the n light emitting elements have n first external terminals connected to the first electrodes, and n second external terminals connected to the second electrodes; The first external terminals and the second external terminals are arranged alternately in the first direction. 3. The light emitting unit according to claim 2, characterized in that: among two light emitting elements adjacent in the first direction, the first external terminal of one light emitting element and the second external terminal of the other light emitting element Two external terminals are bonded to the common third pad. 4. The light-emitting unit according to any one of claims 1 to 3, characterized in that: the group of n light-emitting elements arranged in the first direction is at an angle perpendicular to the first direction A plurality are arranged in the second direction. 5. The light emitting unit according to any one of claims 1 to 3, characterized in that: the area of the third pad is larger than the area of the first pad and the area of the second pad. 6. The lighting unit according to any one of claims 1 to 3, characterized in that: The semiconductor light emitting device includes: phosphor layer; and The semiconductor layer is provided between the phosphor layer and the external terminal, and has a light emitting layer. 7. A semiconductor light emitting device, characterized in that it comprises: A plurality of light emitting elements, respectively having a first electrode and a second electrode, and arranged in a first direction; a resin layer integrally supporting the plurality of light emitting elements; a first external terminal connected to the first electrode of a light emitting element at one end in the first direction among the plurality of light emitting elements; a second external terminal connected to the second electrode of the light emitting element at the other end in the first direction among the plurality of light emitting elements; and The third external terminal is provided between the first external terminal and the second external terminal, and is provided in common with a plurality of light emitting elements adjacent in the first direction. 8 . The semiconductor light emitting device according to claim 7 , wherein an area of the third external terminal is larger than an area of the first external terminal and an area of the second external terminal. 9. The semiconductor light emitting device according to claim 7 or 8, further comprising: phosphor layer; and The semiconductor layer is provided between the phosphor layer and the first electrode, and between the phosphor layer and the second electrode, and has a light emitting layer.