CN105990243A - Memory element and method for manufacturing the same - Google Patents

Abstract

The invention provides a memory element and a method of manufacturing the same. The memory element comprises a plurality of stacked structures, a plurality of first stepped contact windows and a plurality of second stepped contact windows. The plurality of stacked structures extend in a first direction and include a first semiconductor layer and a second semiconductor layer, wherein the second semiconductor layer is located above the first semiconductor layer. The first step-shaped contact windows extend in the second direction, and the bottom surfaces of the first step-shaped contact windows are electrically connected with the first semiconductor layers of the (i + 1) th stacked structure and the (i + 2) th stacked structure, wherein i is an odd number. The second stepped contact windows extend in the second direction, and the bottom surfaces of the second stepped contact windows are electrically connected with the second semiconductor layers of the ith stacked structure and the (i + 1) th stacked structure. The first direction is different from the second direction.

Description

Memory element and its manufacturing method

technical field

The present invention relates to a semiconductor element and its manufacturing method, and in particular to a memory element and its manufacturing method.

Background technique

Memory can be divided into two types: volatile memory and non-volatile memory. After the power supply of volatile memory is interrupted, the data stored in the memory will disappear; even if the power supply of non-volatile memory is interrupted, the data stored in the memory will not disappear, and the data stored in the memory can be read after re-powering The data. Therefore, the non-volatile memory can be widely used in electronic products, especially portable products.

With the increasing density and shrinking of memory elements, the short channel effect of horizontal memory elements becomes more and more serious, which leads to more serious problems of second bit effect and program disturbance between adjacent memory cells. . As a result, vertical memory devices have gradually been developed. However, the interconnection of vertical memory devices is another challenge.

If the interconnect layout of the vertical memory device is directly connected to the source or drain of the memory device, the source and drain interconnects will be electrically connected to each other, which will cause the operation of the memory device to fail. On the other hand, if the interconnection layout of the vertical storage device is pulled to the peripheral region before being connected to the source or drain of the storage device, the resistance value of the bit line will increase. Therefore, how to solve the interconnection problem of the vertical memory device without sacrificing the resistance value of the bit line and the chip area will become a very important subject in the future.

Contents of the invention

The invention provides a memory element and its manufacturing method, which can solve the problem of interconnection of the vertical memory element without affecting the resistance value of the bit line and the chip area.

The invention provides a method for manufacturing a memory element, the steps of which include: providing a substrate, the substrate includes a plurality of first blocks and a plurality of second blocks, the first blocks and the second blocks alternate with each other, and each first block A block includes two first areas and a second area, and the second area is located between the two first areas. A plurality of stacked structures are formed on the substrate on the first block and the second block, each stacked structure extends in a first direction, and includes the first semiconductor layer on a part of the substrate. The second semiconductor layer is located above the first semiconductor layer. A plurality of word lines are formed on the base of each first region, and each word line extends in a second direction, covering part of side surfaces and part of top surfaces of each stack structure, and the first direction is different from the second direction. A charge storage layer is formed between the stacked structure and the word line. Part of the stacked structure on the second block is removed to expose the first semiconductor layer. A plurality of first stepped contact windows are formed in the second block, and the bottom surface of each first stepped contact window is electrically connected to the first semiconductor layer of the (i+1)th stacked structure and the (i+2)th stacked structure, And the area of the top surface of each first stepped contact window is smaller than the area of the bottom surface, wherein i is an odd number. A plurality of second stepped contact windows are formed in the second region, the bottom surface of each stepped second contact window is electrically connected to the second semiconductor layer of the i-th stacked structure and the (i+1)-th stacked structure, and each The area of the top surface of the second stepped contact window is smaller than the area of the bottom surface. A plurality of first conductive wires and a plurality of second conductive wires are formed alternately on the substrate, each first conductive wire extends in a first direction, and is connected with the first semiconductor of the (i+1)th stacked structure and the (i+2)th stacked structure The top surface of the first stepped contact window that is electrically connected to the layers is electrically connected, and each second wire extends in the first direction, and is electrically connected to the second semiconductor layer of the i-th stacked structure and the i+1-th stacked structure. The top surface of the connected second stepped contact window is electrically connected.

In an embodiment of the present invention, the steps of forming the first stepped contact window in the second area and forming the second stepped contact window in the second area include: forming a plurality of first stepped contact windows in the second area A conductor plug, each first conductor plug is electrically connected to the first semiconductor layer of the (i+1)th stacked structure and the (i+2)th stacked structure, and a plurality of second conductor plugs are formed in the second region , each second conductor plug is electrically connected to the i-th stack structure and the second semiconductor layer of the i+1-th stack structure. A plurality of third conductor plugs are formed on the first conductor plug, and a plurality of fourth conductor plugs are formed on the second conductor plug, wherein the first conductor plug and the third conductor plug form a first stepped contact window, the second conductor plug and the fourth conductor plug form a second stepped contact window.

In an embodiment of the present invention, it further includes forming spacers on the sides of each word line and each stack structure. Before removing part of the stacking structure on the second block, part of the spacer on the second block is removed. A lining layer and a first dielectric layer are formed on the base. removing a portion of the first dielectric layer and a portion of the liner to form a plurality of first contact openings in the second block, each of the first contact openings exposing the i+1th stack structure and the i+2th stack structure a stacked structure of the first semiconductor layer, and a plurality of second contact openings are formed in the second region, and each second contact opening exposes the second semiconductor layer of the i-th stacked structure and the i+1-th stacked structure layer. A first conductor plug and a second conductor plug are respectively formed in the first contact window opening and the second contact window opening. A second dielectric layer is formed on the substrate. Part of the second dielectric layer is removed to form a plurality of third contact openings in the second block, each third contact opening is located between the i+1th stack structure and the i+2th stack structure and expose the corresponding first conductor plug, and form a plurality of fourth contact window openings in the second region, each fourth contact window opening is located between the i-th stack structure and the i+1-th stack structure, And the corresponding second conductor plug is exposed. A third conductor plug and a fourth conductor plug are respectively formed in the third contact opening and the fourth contact opening.

In an embodiment of the present invention, each of the above-mentioned first wires is located between the i+1th stacked structure and the i+2th stacked structure, and each second wire is located between the ith stacked structure and the i+1th stacked structure. between stacked structures.

In an embodiment of the present invention, the above-mentioned step of forming a stack structure includes: forming a first semiconductor layer on a substrate. A first barrier layer is formed on the first semiconductor layer. A base layer is formed on the first barrier layer. A second barrier layer is formed on the base layer. A second semiconductor layer is formed on the second barrier layer. The second semiconductor layer, the second barrier layer, the base layer, the first barrier layer and the first semiconductor layer are patterned to form a stack structure.

The present invention provides a memory element, comprising: a substrate, multiple stacked structures, multiple word lines, a charge storage layer, multiple first stepped contact windows, multiple second stepped contact windows, multiple first wires and a plurality of second conductors. The above-mentioned substrate includes a plurality of first blocks and a plurality of second blocks, the first blocks and the second blocks alternate with each other, each first block includes two first blocks and a second block, and the second block is located at Between the two first districts. The above stacked structure is located on the base. Each stacked structure extends in a first direction. Each stacked structure includes: the first semiconductor layer is located above part of the substrates of the first block and the second block. The second semiconductor layer is located above a portion of the base of the first block and above the first semiconductor layer. The above-mentioned word lines are located on the base of each first region, and each word line extends in a second direction, covering part of side surfaces and part of top surfaces of each stacked structure, and the first direction is different from the second direction. The charge storage layer is located between the stack structure and the word line. The above-mentioned first stepped contact windows are located in the second block, and the bottom surface of each first stepped contact window is electrically connected to the first semiconductor layer of the (i+1)th stacked structure and the (i+2)th stacked structure, and each The area of the top surface of a first stepped contact window is smaller than the area of the bottom surface, wherein i is an odd number. The above-mentioned second ladder-shaped contact windows are located in the second region, and the bottom surface of each ladder-shaped second contact window is electrically connected to the second semiconductor layer of the i-th stack structure and the (i+1)-th stack structure, and each second The area of the top surface of the stepped contact window is smaller than the area of the bottom surface. The above-mentioned first wires and the above-mentioned second wires are alternately located on the base, each first wire extends in a first direction, and is electrically connected to the i+1th stack structure and the i+2th stack structure. The top surface of the first stepped contact window of a semiconductor layer is electrically connected, each second wire extends in the first direction, and is electrically connected with the second semiconductor layer of the i-th stack structure and the i+1-th stack structure The top surface of the second stepped contact window is electrically connected.

In an embodiment of the present invention, the above-mentioned first stepped contact window includes: a plurality of first conductor plugs located in the second block, and each first conductor plug is electrically connected to the i+1th stack structure and The first semiconductor layer of the i+2th stacked structure. A plurality of third conductor plugs are located on the first conductor plug, wherein the area of the top surface of each third conductor plug is smaller than the area of the bottom surface of the corresponding first conductor plug. The above-mentioned second stepped contact window includes: a plurality of second conductor plugs located in the second region, and each second conductor plug is electrically connected to the second semiconductor layer of the i-th stack structure and the i+1-th stack structure . A plurality of fourth conductor plugs are located on the second conductor plug, wherein the area of the top surface of each fourth conductor plug is smaller than the area of the bottom surface of the corresponding second conductor plug.

In one embodiment of the present invention, the width of each of the above-mentioned first wires is smaller than the width of the bottom surface of any corresponding first conductor plug, and the width of each second wire is smaller than that of any corresponding second conductor plug. The width of the base.

In an embodiment of the present invention, each of the above-mentioned first wires is located between the i+1th stacked structure and the i+2th stacked structure, and each second wire is located between the ith stacked structure and the i+1th stacked structure. between stacked structures.

In an embodiment of the present invention, each of the above stacked structures includes: a base layer located between the first semiconductor layer and the second semiconductor layer of the first block. The first barrier layer is located between the base layer and the first semiconductor layer. The second barrier layer is located between the base layer and the second semiconductor layer.

Based on the above, the present invention utilizes the bottom of the first stepped contact window to be electrically connected to the first semiconductor layer of the (i+1)th stacked structure and the (i+2)th stacked structure, and utilizes the bottom of the stepped second contact window to The i-th stack structure is electrically connected to the second semiconductor layer of the (i+1)-th stack structure (i is an odd number), so that the first semiconductor layer (such as a source) and the second semiconductor layer (such as a drain) of the stack structure poles) are electrically isolated from each other. In this way, the present invention can solve the problem of the interconnection layout of the vertical storage element without sacrificing the resistance value of the bit line and the chip area.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1A to FIG. 1F are schematic top views illustrating a manufacturing process of a storage device according to an embodiment of the present invention.

2A to 2F are schematic cross-sectional views along line A-A' of FIGS. 1A to 1F respectively.

3A to 3F are schematic cross-sectional views along the line B-B' in FIGS. 1A to 1F .

4A to 4F are schematic cross-sectional views along line C-C' in FIGS. 1A to 1F .

Fig. 5 is a schematic cross-sectional view along line D-D' of Fig. 1A.

6A to 6D are schematic cross-sectional views along line E-E' of FIG. 1C to FIG. 1F respectively.

7A to 7C are schematic cross-sectional views along the line F-F' of FIG. 1D to FIG. 1F .

FIG. 8A is a schematic diagram of a memory array structure according to an embodiment of the present invention.

FIG. 8B is a schematic diagram of operations for reading a memory cell.

FIG. 8C is a schematic diagram of operations for programming memory cells.

FIG. 8D is a schematic diagram of operations for erasing memory cells.

【Symbol Description】

10: base

11, 11a, 11b, 11c: stacked structure

12: The first semiconductor layer

14: The first barrier layer

16: substrate layer

18: Second barrier layer

20: Second semiconductor layer

22: Charge storage layer

24: word line

26: spacer wall

28: channel

30: lining

32, 36: dielectric layer

34a: First conductor plug

34b: Second conductor plug

38a: Third conductor plug

38b: Fourth conductor plug

40a: first stepped contact window

40b: second stepped contact window

42a: First wire

42b: Second wire

801: memory cell string

B1: the first block

B2: the second block

BL ₁ ~ BL ₇ : Bit lines

BLT ₁ ~ BLT ₇ : bit line transistors

Bu1, Bu2: bottom surface

D1: first direction

D2: Second direction

GBL ₁ ~ GBL ₃ : Global bit line

M: storage unit

R1: Region 1

R2: second zone

T1, T2: top surface

V ₁ , V ₂ , V _d , V _g , V _s : Voltage

W1, W2, W3, W4: Width

WL ₁ ~ WL ₁₂₈ : word line

detailed description

FIG. 1A to FIG. 1F are schematic top views illustrating a manufacturing process of a storage device according to an embodiment of the present invention. 2A to 2F are schematic cross-sectional views along line A-A' of FIGS. 1A to 1F respectively. 3A to 3F are schematic cross-sectional views along the line B-B' in FIGS. 1A to 1F . 4A to 4F are schematic cross-sectional views along line C-C' in FIGS. 1A to 1F . Fig. 5 is a schematic cross-sectional view along line D-D' of Fig. 1A. 6A to 6D are schematic cross-sectional views along line E-E' of FIG. 1C to FIG. 1F respectively. 7A to 7C are schematic cross-sectional views along the line F-F' of FIG. 1D to FIG. 1F .

Referring to FIG. 1A , a substrate 10 is provided. The substrate 10 includes a plurality of first blocks B1 and a plurality of second blocks B2. The first block B1 and the second block B1 alternate with each other. In FIG. 1A to FIG. 1F , two first blocks B1 and one second block B2 are represented. Each first block B1 includes two first regions R1 and one second region R2. The first region R1 is adjacent to the second block B2; the second region R2 is located between the two first regions R1. The substrate 10 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor over insulator (SOI) substrate. Semiconductors are, for example, atoms of group IVA, such as silicon or germanium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of group IVA, such as silicon carbide or germanium silicide, or a semiconductor compound formed of atoms of group IIIA and group VA, such as gallium arsenide.

Referring to FIG. 1A , FIG. 2A , FIG. 3A , FIG. 4A and FIG. 5 , a plurality of stacked structures 11 are formed on the substrate 10 . Each stack structure 11 extends in the first direction D1. In another embodiment, the stack structure 11 sequentially includes the first semiconductor layer 12 , the base layer 16 and the second semiconductor layer 20 . The first semiconductor layer 12 /base layer 16 /second semiconductor layer 20 are, for example, source/base/drain. The first semiconductor layer 12 and the second semiconductor layer 20 can be doped layers of the first conductivity type; and the base layer 16 can be doped layers of the second conductivity type. In an exemplary embodiment, the first semiconductor layer 12 /base layer 16 /second semiconductor layer 20 may be, for example, an N+/P/N+ doped layer, a P+/N/P+ doped layer or a SiGe/Si/SiGe layer. In another embodiment, the stack structure 11 sequentially includes a first semiconductor layer 12 , a first barrier layer 14 , a base layer 16 , a second barrier layer 18 and a second semiconductor layer 20 . The thicknesses of the first barrier layer 14 and the second barrier layer 18 should be able to block the diffusion of dopants in the first semiconductor layer 12 , the base layer 16 and the second semiconductor layer 20 and direct charge tunneling. In one embodiment, the materials of the first barrier layer 14 and the second barrier layer 18 include oxide, nitride or oxynitride. The first barrier layer 14 and the second barrier layer 18 may be the same or different materials. The thicknesses of the first barrier layer 14 and the second barrier layer 18 are, for example, 10 to 20 angstroms. In one embodiment, the method of forming the stacked structure 11 is, for example, firstly forming a semiconductor material layer, a barrier material layer, a base material layer, another barrier material layer, and another semiconductor material layer. Afterwards, photolithography and etching processes are performed to form the stack structure 11 . The above semiconductor material layer, barrier material layer, base material layer, barrier material layer and another semiconductor material layer can be formed by chemical vapor deposition or physical vapor deposition.

Afterwards, a charge storage layer 22 is formed on the substrate 10 . The charge storage layer 22 is conformally formed along the top and side surfaces of the stack structure 11 . In the storage element of the present invention, since the charge storage layer 22 is located on the top and side surfaces of the stacked structure 11, the charge storage layer 22 not only has the function of storing charges, but also has the function of connecting the first semiconductor layer 12, the second semiconductor layer 20 and the The word line 24 (as shown in FIG. 5 ) in the subsequent process is electrically isolated. In one embodiment, the charge storage layer 22 is, for example, a composite layer composed of oxide layer/nitride layer/oxide layer (Oxide-Nitride-Oxide, ONO). This composite layer may be three or more layers. The invention is not limited thereto, and its forming method may be chemical vapor deposition, thermal oxidation, etc.

Then, a word line material layer (not shown) is formed on the charge storage layer 22 , and the word line material layer is conformally formed along the top surface and side surfaces of the charge storage layer 22 . Next, the word line material layer is patterned to form a plurality of word lines 24 (for example, as control gates) in the first region R1 , exposing the top surface of the charge storage layer 22 . Each word line 24 extends in the second direction D2, covering part of the side and part of the top surface of each charge storage layer 22 in the first region R1. In an embodiment, the above-mentioned first direction D1 is different from the second direction D2. In an exemplary embodiment, the first direction D1 and the second direction D2 are substantially perpendicular.

As shown in FIG. 5 , since the word line 24 covers both sides of the stack structure 11, the word line 24 can use the two sides of the stack structure 11 to control the operation of the storage element of the present invention in a double gate structure, compared with a single-side In terms of control, the memory element of the present invention utilizes double-side control on both sides of the stack structure 11 to make the operation of the memory element more precise.

Please refer to FIG. 1B , FIG. 2B , FIG. 3B and FIG. 4B at the same time. Spacers 26 are respectively formed on the sides of each word line 24 and each stack structure 11 . Specifically, a spacer material layer (not shown) is conformally formed on the substrate 10 to cover the stacked structure 11 . The material of the spacer material layer is, for example, silicon oxide, silicon nitride or a combination thereof, which can be formed by chemical vapor deposition. Then, an anisotropic etching process is performed to remove part of the spacer material layer, so as to form spacers 26 on the sides of each word line 24 and each stacked structure 11 .

Please refer to FIG. 1C, FIG. 2C, FIG. 3C, FIG. 4C and FIG. 6A at the same time, perform photolithography and etching process, and remove part of the stack structure 11 and part of the spacer 26 on the second block B2 to form the channel 28 (as shown in FIG. 2C and FIG. 3C ), the first semiconductor layer 12 is exposed (as shown in FIGS. 2C-4C ). Next, a liner 30 is conformally formed on the substrate 10 to cover the stack structure 11 and the word lines 24 . The material of the liner 30 can be silicon oxide, silicon oxynitride, silicon nitride or a combination thereof. Its formation method can be formed by chemical vapor deposition or physical vapor deposition.

Referring to FIG. 1D , FIG. 2D , FIG. 3D , FIG. 4D , FIG. 6B and FIG. 7A simultaneously, a dielectric layer 32 is formed on the substrate 10 . Then, a part of the dielectric layer 32 and a part of the liner layer 30 are removed by photolithography and etching process, so as to form a plurality of first contact openings 33a in the second region B2 and a plurality of contact openings 33a in the second region R2. The second contact window opening 33b. Each first contact opening 33a exposes the first semiconductor layer 12 of the i+1th stack structure 11b and the i+2th stack structure 11c ( FIGS. 1D and 4D ). Each second contact opening 33b exposes the second semiconductor layer 20 of the i-th stack structure 11a and the (i+1)-th stack structure 11b ( FIGS. 1D and 6B ). i is an odd number. Since the liner 30 conformally covers the stacked structure 11 and the word line 24, it makes the liner 30 even if there is a problem of misalignment when forming the first contact opening 33a and the second contact opening 33b. The stacked structure 11 and the word line 24 can be protected from being damaged by etching, which may result in a short circuit between the subsequently formed contact window and the stacked structure 11 and the word line 24 .

After that, a first conductor plug 34a and a second conductor plug 34b are respectively formed in the first contact window opening 33a and the second contact window opening 33b. Each first conductor plug 34a is electrically connected to the first semiconductor layer 12 of the i+1th stack structure 11b and the i+2th stack structure 11c; and each second conductor plug 34b is electrically connected to the ith The stack structure 11a and the second semiconductor layer 20 of the (i+1)th stack structure 11b. i is an odd number. For example, when i is 1, the first conductor plug 34a is electrically connected to the first semiconductor layer 12 of the second stack structure 11b and the third stack structure 11c; and the second conductor plug 34b is electrically connected to the first semiconductor layer 12 of the third stack structure 11c One stack structure 11a and the second semiconductor layer 20 of the second stack structure 11b, and so on, will not be described in detail later. Since the first conductor plug 34a and the second conductor plug 34b can respectively connect the first semiconductor layer 12 and the second semiconductor layer 20, and the first conductor plug 34a and the second conductor plug 34b are electrically connected to each other through the dielectric layer 32. Therefore, the first semiconductor layer 12 and the second semiconductor layer 20 are also electrically isolated from each other. In this way, the layout of the first semiconductor layer 12 and the second semiconductor layer 20 can be completed through the interconnection of the memory cell region (Cell region), without sacrificing the resistance value of the bit line and the chip area. The method for forming the first conductor plug 34 a and the second conductor plug 34 b is, for example, to form a conductor material layer on the substrate 10 first. The conductive material layer is, for example, tungsten, aluminum, copper or alloys thereof. The forming method may be a physical vapor deposition method, such as a sputtering method. Afterwards, the portion other than the first contact opening 33 a and the second contact opening 33 b can be removed by chemical mechanical polishing or etching back.

Referring to FIG. 1E , FIG. 2E , FIG. 3E , FIG. 4E , FIG. 6C and FIG. 7B simultaneously, a dielectric layer 36 is formed on the substrate 10 . Then, using photolithography and etching process, part of the dielectric layer 36 is removed to form a plurality of third contact openings 37a in the second region B2 (FIG. 1E and FIG. 4E), and in the second region R2 A plurality of fourth contact openings 37b are formed (FIG. 1E and FIG. 6C). Each third contact opening 37a is located between the i+1th stack structure 11b and the i+2th stack structure 11c and exposes the corresponding first conductor plug 34a. Each fourth contact opening 37b is located between the i-th stack structure 11a and the i+1-th stack structure 11b, and exposes the corresponding second conductor plug 34b. Next, a third conductor plug 38a and a fourth conductor plug 38b are respectively formed in the third contact opening 37a and the fourth contact opening 37b. The third conductor plug 38 a and the fourth conductor plug 38 b are formed by, for example, firstly forming a conductor material layer on the substrate 10 . The conductive material layer is, for example, tungsten, aluminum, copper or alloys thereof. The forming method may be a physical vapor deposition method, such as a sputtering method. Afterwards, the excess portion other than the third contact opening 37 a and the fourth contact opening 37 b is removed by chemical mechanical polishing or etching back.

As shown in FIG. 4E and FIG. 6C , the third conductor plug 38 a and the first conductor plug 34 a form a first stepped contact window 40 a. The fourth conductor plug 38b and the second conductor plug 34b form a second stepped contact window 40b. A plurality of first stepped contacts 40a are located in the second block B2. The bottom surface Bu1 of each first stepped contact window 40a is electrically connected to the first semiconductor layer 12 of the (i+1)th stack structure 11b and the (i+2)th stacked structure 11c, and each first stepped contact window 40a The area of the top surface T1 is smaller than the area of its bottom surface Bu1. And a plurality of second stepped contact windows 40b are located in the second region R2. The bottom surface Bu2 of each ladder-shaped second contact window 40b is electrically connected to the second semiconductor layer 20 of the i-th stack structure 11a and the i+1-th stack structure 11b, and the top surface of each second ladder-shaped contact window 40b The area of T2 is smaller than the area of its bottom surface Bu2.

Please refer to FIG. 1F, FIG. 2F, FIG. 3F, FIG. 4F, FIG. 6D and FIG. 7C at the same time, forming a conductive material layer (not shown) on the substrate 10, and then patterning the conductive material layer to form a plurality of alternating The first wire 42a and the plurality of second wires 42b serve as bit lines. Each first wire 42a extends in the first direction D1 and is electrically connected to the top surface T1 of the first stepped contact window 40a; each second wire 42b extends in the first direction D1 and is electrically connected to the second stepped contact window 40b The top surface T2 is electrically connected. In other words, each first wire 42a is electrically connected to the first semiconductor layer 12 of the i+1th stack structure 11b and the i+2th stack structure 11c; and each second wire 42b is connected to the ith stack structure The structure 11a is electrically connected to the second semiconductor layer 20 of the (i+1)th stacked structure 11b. Moreover, each first conducting wire 42a is located between the i+1th stacking structure 11b and the i+2th stacking structure 11c, and each second conducting wire 42b is located between the i'th stacking structure 11a and the i+1th stacking structure 11b between. The material of the conductive material layer is, for example, tungsten, aluminum, copper or alloys thereof, and its forming method can be formed by physical vapor deposition, such as sputtering. The width W1 of each first wire 42a is smaller than the width W2 of the bottom surface of any corresponding first conductor plug 34a; the width W3 of each second wire 42b is smaller than the width of any corresponding bottom surface of the second conductor plug 34b W4. In this way, insufficient process window of the wire can be avoided.

Please refer to FIG. 1F , FIG. 4F and FIG. 6D , the storage element according to an embodiment of the present invention includes: a substrate 10 , a plurality of stacked structures 11 , a plurality of word lines 24 , a charge storage layer 22 , a first stepped contact window 40a, The second stepped contact window 40b, a plurality of first conductive lines 42a and a plurality of second conductive lines 42b (eg, as bit lines).

Referring to FIGS. 1F and 4F , the substrate 10 includes a plurality of first blocks B1 and a plurality of second blocks B2 . The first block B1 and the second block B1 alternate with each other. In FIG. 1F , two first blocks B1 and one second block B2 are represented. Each first block B1 includes two first regions R1 and one second region R2. The first region R1 is adjacent to the second block B2; the second region R2 is located between the two first regions R1.

Referring to FIG. 6D , a plurality of stacked structures 11 are located on the substrate 10 . Each stacked structure 11 extends in a first direction D1 , wherein each stacked structure 11 includes: a first semiconductor layer 12 , a base layer 16 and a second semiconductor layer 20 . The first semiconductor layer 12 is located above part of the substrate 10 of the first block B1 and the second block B2. The second semiconductor layer 20 is located above a part of the substrate 10 of the first block B1 and is located above the first semiconductor layer 12 . The base layer 16 is located between the first semiconductor layer 12 and the second semiconductor layer 20 of the first block B1.

Referring to FIGS. 1D and 1F , a plurality of word lines 24 are located on the substrate 10 of each first region R1 , and each word line 24 extends in the second direction D2 to cover part of the side and part of the top of each stack structure 11 . The first direction D1 is different from the second direction D2. The charge storage layer 22 is located between the stack structure 11 and the word line 24 (as shown in FIG. 5 ).

Referring to FIG. 4F and FIG. 6D, a plurality of first stepped contact windows 40a are located in the second block B2. The bottom surface Bu1 of each first stepped contact window 40a is electrically connected to the first semiconductor layer 12 of the (i+1)th stack structure 11b and the (i+2)th stacked structure 11c, and each first stepped contact window 40a The area of the top surface T1 is smaller than the area of its bottom surface Bu1, where i is an odd number. A plurality of second stepped contact windows 40b are located in the second region R2. The bottom surface Bu2 of each ladder-shaped second contact window 40b is electrically connected to the second semiconductor layer 20 of the i-th stack structure 11a and the i+1-th stack structure 11b, and the top surface of each second ladder-shaped contact window 40b The area of T2 is smaller than the area of its bottom surface Bu2. A plurality of first wires 42 a and a plurality of second wires 42 b alternate with each other and are located on the substrate 10 . Each first wire 42a extends in the first direction D1, and is connected to the first stepped contact window 40a (electrically connected to the first semiconductor layer 12 of the i+1th stack structure 11b and the i+2th stack structure 11c). The top surface T1 is electrically connected. Each second wire 42b extends in the first direction D1, and is connected to the top surface T2 of the second stepped contact window 40b (electrically connecting the i-th stack structure 11a and the second semiconductor layer 20 of the i+1-th stack structure 11b). electrical connection.

The first wire 42a (electrically connected to the first semiconductor layer 12 of the i+1th stack structure 11b and the i+2th stack structure 11c) can be used as bit lines BL ₁ , BL ₃ . . . BL _2n-1 , Where n is an integer greater than 1 (as shown in FIG. 8A below). Likewise, the second wire 42b (electrically connected to the second semiconductor layer 20 of the i-th stack structure 11a and the (i+1)-th stack structure 11b ) can serve as bit lines BL ₂ , BL ₄ . . . BL _2n .

FIG. 8A is a schematic diagram of a memory array including the storage device shown in FIG. 1F according to an embodiment of the present invention.

Please refer to FIG. 8A , which shows a plurality of memory cell strings (Cell strings) 801 . These memory cell strings (Cell strings) 801 are connected in series via a plurality of bit lines BL ₁ -BL _2n (where n is an integer greater than 1) and a plurality of word lines WL ₁ -WL _2m (where m is an integer greater than 1), A memory array (Memory array) can be arranged in the column direction and the row direction. In one embodiment, in each first region R1, a plurality of memory cell strings 801 are arranged in parallel. In one embodiment, each memory cell string 801 may include 32 memory cells or more. For the sake of clarity, FIG. 8A only shows that the memory cell strings 801 are connected in series via a plurality of bit lines BL ₁ -BL ₇ and a plurality of word lines WL ₁ -WL ₁₂₈ , but the present invention is not limited thereto.

The bit lines BL ₁ , BL ₃ . . . BL _2n-1 can be coupled to the above-mentioned plurality of first conductive wires 42a (as shown in FIG. is the first semiconductor layer 12 of FIG. 4F). The bit lines BL ₂ , BL ₄ . . . BL _2n can be coupled to the above-mentioned second wire 42b (as shown in FIG. layer 20). In one embodiment, the bit lines BL ₁ , BL ₃ . . . BL _2n-1 may be respectively coupled to the bit line transistors BLT ₁ , BLT ₃ . . . BLT _2n-1 . The bit lines BL ₁ and BL ₃ can be coupled to a global bit line (Global bit line) GBL ₁ . The bit lines BL ₂ and BL ₄ can be coupled to the global bit line GBL ₂ . Bit lines BL ₅ and BL ₇ can be coupled to global bit line GBL ₃ . The control voltage V ₂ is applied to the bit lines BL ₂ and BL ₄ via the global bit line GBL ₂ through on/off of the bit line transistors BLT ₂ and BLT ₄ .

FIG. 8B is a schematic diagram of reading a memory cell.

Referring to FIG. 8B , in one embodiment, when the memory cell M is read (Read), corresponding voltages are applied to the gate, source, and drain of the memory cell M. Referring to FIG. For example, applying a voltage of 10V to the bit line transistor BLT ₂ turns it on, so that the control voltage V ₂ (for example, V ₂ =0V) applied to the global bit line GBL ₂ is transmitted through the bit line transistor BLT ₂ and the bit line BL ₂ , is provided to the source of the memory cell M as the source voltage V _s . In addition, a voltage of 10V is applied to the bit line transistor BLT ₁ to turn it on, so that the control voltage V ₁ (for example, V ₁ =1.6V) applied to the global bit line GBL ₁ is transmitted through the bit line transistor BLT ₁ and the bit line BL ₁ , provided to the drain of the memory cell M as the drain voltage V _d . At the same time, a voltage of, for example, 0V to 10V is applied to the word line WL _i connected to the gate of the memory cell M as the gate voltage _Vg . In this way, the operation of reading the memory cell M can be performed. It should be noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can adjust the voltages to achieve the desired operation for reading each memory cell.

FIG. 8C is a schematic diagram for programming memory cells.

Please refer to FIG. 8C. In one embodiment, when programming the memory cell M, a voltage of 10V is applied to the bit line transistor BLT ₂ to turn it on, so that the control voltage V ₂ applied to the global bit line GBL ₂ (for example V ₂ =0V), provided to the source of the memory cell M via the bit line transistor BLT ₂ and the bit line BL ₂ as the source voltage V _s . In addition, a voltage of 10V is applied to the bit line transistor BLT ₁ to turn it on, so that the control voltage V ₁ (for example, V ₁ =3V) applied to the global bit line GBL ₁ is transmitted through the bit line transistor BLT ₁ and the bit line BL ₁ , is provided to the drain of the memory cell M as the drain voltage V _d . At the same time, a voltage of, for example, 13V is applied to the word line WL _i connected to the gate of the memory cell M as the gate voltage V _g . In this way, the operation of programming the memory cell M can be performed. It should be noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can adjust the voltages to achieve the operation required to program each memory cell.

FIG. 8D is a schematic diagram for erasing a memory cell.

Please refer to FIG. 8D , in one embodiment, when erasing (Erase) the memory cell M, a voltage of 10V is applied to the bit line transistor BLT ₂ to turn it on, so that the control voltage V applied to the global bit line GBL _{2 2} (for example, V ₂ =0V), provided to the source of the memory cell M via the bit line transistor BLT ₂ and the bit line BL ₂ as the source voltage V _s . In addition, a voltage of 10V is applied to the bit line transistor BLT ₁ to turn it on, so that the control voltage V ₁ (for example, V ₁ =5V) applied to the global bit line GBL ₁ is transmitted through the bit line transistor BLT ₁ and the bit line BL ₁ , is provided to the drain of the memory cell M as the drain voltage V _d . At the same time, _a voltage of -10V, for example, is applied to the word line WL1 connected to the gate of the memory cell M as the gate voltage V _g . In this way, the operation of reading the memory cell M can be performed. It should be noted that the scope of the present invention is not limited to the specific voltages described above. One of ordinary skill in the art can adjust the voltages to achieve the desired operation for erasing each memory cell.

In summary, the present invention utilizes the first stepped contact window/the second stepped contact window to respectively connect the drains/sources of two adjacent rows of memory cells in series without sacrificing the resistance value of the bit line and the chip area. On the premise of solving the problem of interconnection layout of the vertical storage element.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make partial changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention should be defined by the claims.

Claims (10)

1. A method for manufacturing a memory element, comprising: A base is provided, the base includes a plurality of first blocks and a plurality of second blocks, the first blocks and the second blocks alternate with each other, and each first block includes two first blocks and two a second zone located between the two first zones; A plurality of stacked structures are formed on the substrate on the first blocks and the second blocks, and each stacked structure extends in a first direction, including: a first semiconductor layer on a portion of the substrate; and a second semiconductor layer located above the first semiconductor layer; A plurality of word lines are formed on the base of each first region, each word line extends in a second direction, covering part of the side surfaces and part of the top surfaces of each of the stacked structures, the first direction and the second direction different; forming a charge storage layer between the stacked structures and the word lines; removing parts of the stacked structures on the second blocks to expose the first semiconductor layers; A plurality of first stepped contact holes are formed in the second blocks, and the bottom surface of each first stepped contact hole is electrically connected to the i+1th stacked structure and the i+2th stacked structure. a semiconductor layer, and the area of the top surface of each first stepped contact window is smaller than the area of the bottom surface thereof, wherein i is an odd number; A plurality of second stepped contact windows are formed in the second regions, and the bottom surface of each stepped second contact window is electrically connected to the i-th stacked structure and the second semiconductors of the i+1-th stacked structure layer, and the area of the top surface of each second stepped contact window is smaller than the area of its bottom surface; and A plurality of first conductive wires and a plurality of second conductive wires are formed alternately on the substrate, each first conductive wire extends in the first direction, and is connected with the i+1th stacked structure and the i+2th stacked structure The top surfaces of the first stepped contact windows electrically connected to the first semiconductor layers are electrically connected, each second wire extends in the first direction, and is connected to the ith stacked structure and the i+th stacked structure. The top surfaces of the second stepped contact windows electrically connected to the second semiconductor layers of a stacked structure are electrically connected. 2. The manufacturing method of the memory device according to claim 1, wherein the first stepped contact windows are formed in the second regions and the second stepped contact windows are formed in the second regions The steps include: A plurality of first conductor plugs are formed in the second blocks, and each first conductor plug is electrically connected to the i+1th stack structure and the first semiconductors of the i+2th stack structure layer, and form a plurality of second conductor plugs in the second regions, each second conductor plug electrically connects the i-th stack structure and the i+1-th stack structure with the second semiconductors layers; and A plurality of third conductor plugs are formed on the first conductor plugs, and a plurality of fourth conductor plugs are formed on the second conductor plugs, wherein the first conductor plugs and the third conductor plugs The plugs form the first stepped contact windows, and the second conductor plugs and the fourth conductor plugs form the second stepped contact windows. 3. The manufacturing method of the memory element according to claim 2, further comprising: A spacer is formed on each word line and the side of each stack structure; Before removing part of the stacked structures on the second blocks, removing part of the spacers on the second blocks; forming a lining layer and a first dielectric layer on the base; removing part of the first dielectric layer and part of the liner layer to form a plurality of first contact openings in the second regions, each first contact opening exposing the i+1th stacked structure and the first semiconductor layers of the i+2th stacked structure, and form a plurality of second contact window openings in the second regions, each second contact window opening exposes the ith stacked structure and the The second semiconductor layers of the i+1th stack structure; forming the first conductor plugs and the second conductor plugs in the first contact openings and the second contact openings respectively; forming a second dielectric layer on the substrate; Part of the second dielectric layer is removed to form a plurality of third contact openings in the second blocks, and each third contact opening is located between the i+1th stacked structure and the i+2th stacking structure. The corresponding first conductor plugs are exposed between the stacked structures, and a plurality of fourth contact openings are formed in the second regions, and each fourth contact opening is located between the ith stacked structure and the i-th stacked structure. The exposed corresponding second conductor plugs between the (i+1)th stacked structures; and The third conductor plugs and the fourth conductor plugs are respectively formed in the third contact window openings and the fourth contact window openings. 4. The manufacturing method of the memory element according to claim 1, wherein each first wire is located between the (i+1)th stacked structure and the (i+2)th stacked structure, and each second wire is located between the (i+2)th stacked structure. between the i stacked structure and the i+1th stacked structure. 5. The manufacturing method of the memory element according to claim 1, wherein the step of forming the stacked structures comprises: forming the first semiconductor layer on the substrate; forming a first barrier layer on the first semiconductor layer; forming a base layer on the first barrier layer; forming a second barrier layer on the base layer; forming the second semiconductor layer on the second barrier layer; and The second semiconductor layer, the second barrier layer, the base layer, the first barrier layer and the first semiconductor layer are patterned to form the stacked structures. 6. A storage element, characterized in that it comprises: A base, the base includes a plurality of first blocks and a plurality of second blocks, the first blocks alternate with the second blocks, each of the first blocks includes two first blocks and a a second zone located between the two first zones; A plurality of stacked structures located on the base, wherein each stacked structure extends in a first direction, and each stacked structure includes: a first semiconductor layer overlying portions of the substrate in the first blocks and the second blocks; and a second semiconductor layer located over portions of the base of the first blocks and over the first semiconductor layer; a plurality of word lines, located on the base of each first region, each word line extending in a second direction, covering part of the side surfaces and part of the top surface of each of the stacked structures, the first direction and the second direction different; a charge storage layer located between the stacked structures and the word lines; A plurality of first stepped contact holes are located in the second blocks, and the bottom surface of each first stepped contact hole is electrically connected to the i+1th stacked structure and the i+2th stacked structure. a semiconductor layer, and the area of the top surface of each first stepped contact window is smaller than the area of the bottom surface thereof, wherein i is an odd number; A plurality of second stepped contact windows are located in the second regions, and the bottom surface of each stepped second contact window is electrically connected to the i-th stacked structure and the second semiconductors of the i+1-th stacked structure layer, and the area of the top surface of each second stepped contact window is smaller than the area of its bottom surface; and A plurality of first conductive wires and a plurality of second conductive wires are alternately located on the base, each first conductive wire extends in the first direction, and is electrically connected to the i+1th stacked structure and the i+th The top surfaces of the first stepped contact windows of the first semiconductor layers of the two stacked structures are electrically connected, each second wire extends in the first direction, and is electrically connected to the ith stacked structure and The top surfaces of the second stepped contact windows of the second semiconductor layers of the (i+1)th stacked structure are electrically connected. 7. The memory element of claim 6, wherein: The first stepped contacts include: A plurality of first conductor plugs are located in the second blocks, and each first conductor plug is electrically connected to the first semiconductors of the (i+1)th stack structure and the (i+2)th stack structure layers; and a plurality of third conductor plugs located on the first conductor plugs, wherein the area of the top surface of each third conductor plug is smaller than the area of the bottom surface of the corresponding first conductor plug; and The second stepped contacts include: a plurality of second conductor plugs located in the second regions, each second conductor plug electrically connecting the i-th stack structure and the second semiconductor layers of the i+1-th stack structure; and A plurality of fourth conductor plugs are located on the second conductor plugs, wherein the area of the top surface of each fourth conductor plug is smaller than the area of the bottom surface of the corresponding second conductor plug. 8. The memory element according to claim 6, wherein the width of each first wire is smaller than the width of any corresponding bottom surface of the first conductor plugs, and the width of each second wire is smaller than any corresponding one The width of the bottom surface of the second conductor plugs. 9. The memory element according to claim 6, wherein each first conducting wire is located between the i+1th stack structure and the i+2th stacking structure, and each second conducting wire is located in the ith stacking structure structure and the i+1th stacked structure. 10. The memory element according to claim 6, wherein each stack structure comprises: a base layer located between the first semiconductor layer and the second semiconductor layer of the first blocks; a first barrier layer located between the base layer and the first semiconductor layer; and A second barrier layer is located between the base layer and the second semiconductor layer.