CN105990094B - A kind of preparation method of PSM alignment mark structure - Google Patents
A kind of preparation method of PSM alignment mark structure Download PDFInfo
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- CN105990094B CN105990094B CN201510061273.1A CN201510061273A CN105990094B CN 105990094 B CN105990094 B CN 105990094B CN 201510061273 A CN201510061273 A CN 201510061273A CN 105990094 B CN105990094 B CN 105990094B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 29
- 238000002955 isolation Methods 0.000 claims abstract description 18
- 238000000227 grinding Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 10
- 238000000576 coating method Methods 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 8
- 238000011049 filling Methods 0.000 claims description 6
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 230000000717 retained effect Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 26
- 238000005516 engineering process Methods 0.000 description 8
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000010363 phase shift Effects 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- OPTOQCQBJWTWPN-UHFFFAOYSA-N [Si].[Ge].[Si] Chemical compound [Si].[Ge].[Si] OPTOQCQBJWTWPN-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of preparation method of PSM alignment mark structure, by the way that sample grid are arranged above fleet plough groove isolation structure, exposure mask stacking is prepared at the top of the sample grid, and in the technique of high-dielectric constant metal grid pole, since the step height of fleet plough groove isolation structure and active area retains part exposure mask stacking, and nationality stacks the second sample grid of guarantee during the grinding process from damage by being located at the remaining exposure mask on the sample grid, so that the thickness of the sample grid is completely retained, and then improve the alignment quality of contact hole and metal gate, and the simple process is convenient, it is strong with the compatibility of traditional handicraft, with very strong practicability.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of preparation methods of PSM alignment mark structure.
Background technique
With the continuous development of technology, semiconductor technology has infiltrated into the every field in life, such as space flight, medical treatment
Device is guarded against, mobile communication all be unable to do without chip prepared by semiconductor.
Many chips were all using silica as gate dielectric in the past, but since 65nm, due to technology section
Point very little, can not allow gate dielectric continue to shorten it is thinning, while with the continuous diminution of transistor size, source electrode and leakage
The distance between pole is also smaller and smaller, and then be easy to cause short-channel effect.Therefore, in view of the above-mentioned problems, those skilled in the art
Through unremitting research, HKMG (High-K Metal Gate, Gao Jie electricity metal gate) technique is developed member.It is using one kind
Gate dielectric with high dielectric constant (or high K), and prepared as grid using HKMG technique using metal material
Device compare for traditional devices, be greatly reduced leakage current, while effectively improving driving current, thus HKMG at
Mainstream technology used by current high-performance transistor.
Especially in the HKMG technique of 28nm, as shown in Figure 1, the quality and metal gate (Metal of contact hole alignment
Gate, abbreviation MG) thickness have very strong correlation, and contact hole be aligned metal gate, metal gate phase shift exposure mask (phase
Shift mask, abbreviation PSM) label thickness become influence wafer quality a vital factor it is vital because
Element, in Fig. 1, abscissa indicates metal gate thickness (MG thickness), and ordinate indicates wafer quality (wafer
Quality), 1 signified region indicates bit line performance (BL performance).Currently, existing PSM alignment mark is passing through
After ILD CMP and DPRM and AL-CMP, thickness is greatly reduced, and then influences the alignment quality of contact hole and metal gate.
For example, in pressure after technology (Stress proximity technology, abbreviation SPT), sample grid
With a thickness of 670 angstroms, but due to blocking layer of metal silicide (Salicide block, abbreviation SAB) and PMOS germanium silicon silicon nitride
Layer (PMOS SiGe Nitride, abbreviation PSR) exposure mask layer open is moved in interlayer dielectric layer CMP (ILD CMP) and sample grid
After filling metal except (Dummy poly remove, abbreviation DPRM) and carry out CMP, thickness is greatly reduced, only residue 200
Izod is right, this will will affect the alignment quality of contact hole and metal gate, this is that those skilled in the art do not expect to see.
Summary of the invention
In view of the above problems, the present invention discloses a kind of preparation method of PSM alignment mark structure, existing to solve
After the step of passing through ILD CMP and DPRM and metal CMP, thickness greatly reduces the design of PSM alignment mark in technology,
And then the problem of alignment quality of influence contact hole and metal gate.
To achieve the goals above, the present invention provides a kind of preparation methods of PSM alignment mark structure, are applied to Gao Jie
In dielectric constant metal grid technology, wherein include the following steps:
Step S1 provides a substrate with fleet plough groove isolation structure and active area, and the surface of the substrate is provided with Jie
Matter layer, be formed in the dielectric layer positioned at the active region first grid slot and be located on the fleet plough groove isolation structure
The second gate slot of side is provided with first sample grid in the first grid slot, the second sample grid is provided in the second gate slot, and
The length of the first sample grid is equal to the depth of the first grid slot, and the length of the second sample grid is less than the second gate
The depth of slot；
Step S2, the folded top for being covered on the first sample grid and the second sample grid of one mask stack of preparation, and will
Clearance space in the second gate slot on the second sample grid is filled completely；
Step S3, it removes completely the exposure mask on first sample grid to stack, while removing on the second sample grid
A part of exposure mask stacks and retains part mask stack on the second sample grid and folds；
Step S4, the dielectric layer is ground, with remove the part first sample grid and to the second sample grid it
On remaining exposure mask stack carry out part removal；
Step S5, etching is to remove completely remaining first sample grid in first grid slot；
Step S6, it fills in metal to first grid slot and is ground, nationality is by the remaining exposure mask on the second sample grid
It stacks and ensures the second sample grid during the grinding process from damage.
The preparation method of above-mentioned PSM alignment mark structure, wherein it includes oxide skin(coating) and covering institute that the exposure mask, which stacks,
State the silicon nitride layer of oxide skin(coating).
The preparation method of above-mentioned PSM alignment mark structure, wherein in the step S3, remove the second sample grid it
On a part of mask stack poststack, retain on the second sample grid part mask stack it is folded in, the silicon nitride layer with a thickness of
450-500 angstroms, oxide skin(coating) with a thickness of 50-90 angstroms.
The preparation method of above-mentioned PSM alignment mark structure, wherein in the step S4, on the second sample grid
Remaining exposure mask stack and carry out part removal after, remaining silicon nitride layer on the second sample grid with a thickness of 50-
100 angstroms.
The preparation method of above-mentioned PSM alignment mark structure, wherein the depth of the fleet plough groove isolation structure is 150-
250 angstroms.
The preparation method of above-mentioned PSM alignment mark structure, wherein the material of the dielectric layer is oxide.
The preparation method of above-mentioned PSM alignment mark structure, wherein in step S4 and step S6, the grinding is
Chemical mechanical grinding.
The preparation method of above-mentioned PSM alignment mark structure, wherein the sample grid are polysilicon or amorphous carbon.
The preparation method of above-mentioned PSM alignment mark structure, wherein the metal is Al.
The preparation method of above-mentioned PSM alignment mark structure, wherein after removing first sample grid, and in filling gold
Before category, the surface that one layer of high k dielectric layer is covered on the exposure of first grid slot is first prepared.
The preparation method of above-mentioned PSM alignment mark structure, wherein the method is applied to 28nm high dielectric constant metal
In the technique of grid.
The invention discloses a kind of preparation methods of PSM alignment mark structure, by fleet plough groove isolation structure
Sample grid are set above (shallow trench isolation, abbreviation STI), prepare mask stack at the top of the sample grid
It is folded, and in the technique of high-dielectric constant metal grid pole, since the step height of fleet plough groove isolation structure and active area makes portion
Exposure mask stacking is divided to be retained, and nationality ensures that the second sample grid are being ground by being located at the remaining exposure mask stacking on the sample grid
From damage during mill, so that the thickness of the sample grid is completely retained, and then contact hole and metal gate are improved
Alignment quality.
Specific Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent.Identical label indicates identical part in all the attached drawings.Not can according to than
Example draws attached drawing, it is preferred that emphasis is shows the gist of the present invention.
Fig. 1 is the relation schematic diagram of metal gate thickness and wafer quality in background of invention；
Fig. 2 is the flow chart of the preparation method of PSM alignment mark structure in the embodiment of the present invention；
Fig. 3 a-3g is the flowage structure schematic diagram of the preparation method of PSM alignment mark structure in the embodiment of the present invention.
Specific embodiment
The present invention is further illustrated with specific embodiment with reference to the accompanying drawing, but not as limit of the invention
It is fixed.
As shown in Fig. 2, the present embodiment is related to a kind of preparation method of PSM alignment mark structure, it is normal to can be applied to high dielectric
In number metal gate process, it is particularly applied in the technique of 28nm high-dielectric constant metal grid pole, specifically, this method includes
Following steps:
Step 1, firstly, provide one be provided with fleet plough groove isolation structure 22 and active area 21 substrate (substrate not in
Shown in figure), and the height for being located at the upper surface of substrate of fleet plough groove isolation structure 22 is lower than the table on the substrate of active area 21
The height in face, it should be noted that height described herein refers to the upper surface of substrate positioned at fleet plough groove isolation structure 22
Height with the upper surface of substrate positioned at active area 21 relative to same level.
Secondly, in preparing dielectric layer of the upper surface in same level on substrate (dielectric layer is not shown in figure)
Afterwards, eatch-back part dielectric layer is to the upper surface of substrate, to form several grid slots for running through dielectric layer；Several grid slots include position
Several second gate slots 32 above fleet plough groove isolation structure 22 and several first grid slots 31 above active area 21, and the
One grid slot 31 is concordant with the upper surface of second gate slot 32, it is clear that, the depth of first grid slot 31 is less than second gate slot 32
Depth；Form structure as shown in Figure 3a.
Again, sample grid material is filled in several grid slots, to form first sample grid 41 in the first grid slot 31,
The second sample grid 42 are formed in second gate slot 32, and first sample grid 41 are from bottom end face to the length L1 between top end surface
(i.e. the length of first sample grid 41) and the second sample grid 42 are from bottom end face to length L2 (i.e. the second sample between top end surface
The length of this grid 42) it is identical, since the depth of first grid slot 31 is less than the depth of second gate slot 32, and first sample grid 41 and the
The length of two sample grid 42 is again identical, so allow for the second sample grid 42 when being set on substrate, upper surface relative to
The height of the top surface positioned at same level of substrate will be different, that is to say, that the top end surface of first sample grid 41
Height h1 relative to substrate is greater than height h2 of 42 top end surface of the second sample grid relative to substrate, i.e. first sample grid 41
Length be equal to the depth of first grid slot 31, the length of the second sample grid 42 is less than the depth of second gate slot 32, as shown in Figure 3b
Structure.
In a preferred embodiment of the invention, the difference of the depth of second gate slot 32 and the length of the second sample grid 42
(height for being located at the clearance space on the second sample grid 42) is just equal to the depth of fleet plough groove isolation structure 22.
Preferably, the depth of fleet plough groove isolation structure 22 is 150-250 angstroms (such as 150 angstroms, 200 angstroms, 210 angstroms or 250
Angstrom), then the difference of the depth of second gate slot 32 and the length of the second sample grid 42 is 150-250 angstroms of (such as 150 angstroms, 200 angstroms, 210
Angstrom or 250 angstroms).
Preferably, the material of first sample grid 41 and the second sample grid 42 is polysilicon or amorphous carbon.
Preferably, the material of above-mentioned dielectric layer is oxide.
Step 2: one exposure mask of preparation stacks 5 tops for being covered on first sample grid 41 and the second sample grid 42, and by second
Clearance space in grid slot 32 on the second sample grid 42 is filled completely, in a preferred embodiment of the invention
In, exposure mask stacks 5 silicon nitride layers including oxide skin(coating) and covering oxide skin(coating), and (oxide skin(coating) and silicon nitride layer be not in figure
In identify)；Structure as shown in Figure 3c.
Optionally, exposure mask stacking 5 is prepared using the method for chemical vapor deposition and is covered on first sample grid 41 and second
The top of sample grid 42.
Step 3: removing completely the exposure mask on first sample grid 41 using etching technics stacks 5, while removing the
A part of exposure mask on two sample grid 42 stacks 5 and retains part mask stack folded 5 on the second sample grid 42；Such as Fig. 3 d institute
The structure shown.
In a preferred embodiment of the invention, in step 3, removes a part on the second sample grid 42 and cover
After membrane stack, retain on the second sample grid 42 in part mask stack folded 5, silicon nitride layer with a thickness of 450-550 angstroms (such as
450 angstroms, 490 angstroms, 500 angstroms perhaps 550 angstroms etc.) oxide skin(coating) with a thickness of 50-90 angstroms (such as 50 angstroms, 65 angstroms, 70 angstroms or
90 angstroms etc.).
Optionally, the exposure mask on first sample grid 41 is removed completely using dry etch process and stacks 5, same to time shift
5 are stacked except a part of exposure mask on the second sample grid 42 and retain part mask stack folded 5 on the second sample grid 42.
Step 4: (ILD CMP) is ground to dielectric layer, to remove part first sample grid 41 and to the second sample grid
Remaining exposure mask on 42 stacks 5 and carries out part removal, structure as shown in Figure 3 e.
In a preferred embodiment of the invention, in step 4, to the remaining exposure mask on the second sample grid 42
Stack 5 carry out part removals after, remaining silicon nitride layer on the second sample grid with a thickness of 50-100 angstroms (such as 50 angstroms,
70 angstroms, 80 angstroms or 100 angstroms etc.).
Optionally, dielectric layer is ground using chemical mechanical milling tech, removal part first sample grid 41 simultaneously will
Remaining exposure mask on second sample grid 42 stacks 5 and carries out part removal.
Step 5: etch to remove completely remaining first sample grid 41 (DPRM) in first grid slot 31, in the process,
Due to the difference of different material etch rates, remaining exposure mask stacks 5 and is only partially removed on the second sample grid 42, due to
Remaining exposure mask stacks 5 protection, and the second sample grid 42 are fully retained, and forms structure as illustrated in figure 3f.
In a preferred embodiment of the invention, use dry etch process etching to remove completely in first grid slot 31
Remaining first sample grid 41.It should be noted that use dry etch process be for 41 material of first sample grid for
It is carried out in the case where polysilicon, if sample grid are amorphous carbon, sample grid is removed using ashing processing.
Step 6: in filling metal to first grid slot 31 and being ground, nationality is by remaining on the second sample grid 42
Exposure mask stacks 5 the second sample grid 42 of guarantee during the grinding process from damage, and then is forming metal gates 6, and forming gold
Second sample grid 42 are completely retained during belonging to grid 6.
In a preferred embodiment of the invention, fills in metal to first grid slot 31 and ground used by being ground
Grinding process is chemical mechanical grinding.
In a preferred embodiment of the invention, the material of the metal is Al.
In a preferred embodiment of the invention, after removing first sample grid 41, and before filling metal, first
The surface that one layer of high k dielectric layer is covered on the exposure of first grid slot 31 is prepared, with after filling metal, the shape in first grid slot 31
At high-K metal gate.
The invention discloses a kind of preparation methods of PSM alignment mark structure, by setting above fleet plough groove isolation structure
Sample grid are set, exposure mask stacking are prepared at the top of the sample grid, and in the technique of high-dielectric constant metal grid pole, due to shallow ridges
The step height of recess isolating structure and active area retains part exposure mask stacking, and nationality is by being located on the sample grid
Remaining exposure mask stack ensure the second sample grid during the grinding process from damage so that the thickness of the sample grid is able to
It is complete to retain, and then the alignment quality of contact hole and metal gate is improved, and the simple process is convenient, it is compatible with traditional handicraft
Property it is strong, have very strong practicability.
It should be appreciated by those skilled in the art that those skilled in the art are combining the prior art and above-described embodiment can be with
Realize change case, this will not be repeated here.Such change case does not affect the essence of the present invention, and it will not be described here.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, devices and structures not described in detail herein should be understood as gives reality with the common mode in this field
It applies；Anyone skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, anything that does not depart from the technical scheme of the invention, foundation
Technical spirit of the invention any simple modifications, equivalents, and modifications made to the above embodiment, still fall within the present invention
In the range of technical solution protection.
Claims (11)
1. a kind of preparation method of PSM alignment mark structure is applied in the technique of high-dielectric constant metal grid pole, feature exists
In including the following steps:
Step S1, a substrate with fleet plough groove isolation structure and active area is provided, the surface of the substrate is provided with dielectric layer,
It is formed in the dielectric layer positioned at the first grid slot of the active region and above the fleet plough groove isolation structure
Second gate slot is provided with first sample grid in the first grid slot, the second sample grid is provided in the second gate slot, and described
The length of first sample grid is equal to the depth of the first grid slot, and the length of the second sample grid is less than the second gate slot
Depth；
Step S2, the folded top for being covered on the first sample grid and the second sample grid of one mask stack of preparation, and will be described
Clearance space in second gate slot on the second sample grid is filled completely；
Step S3, it removes completely the exposure mask on first sample grid to stack, while removing one on the second sample grid
Divide exposure mask to stack and retain part mask stack on the second sample grid to fold；
Step S4, the dielectric layer is ground, with remove the part first sample grid and to the second sample grid on
Remaining exposure mask, which stacks, carries out part removal；
Step S5, etching is to remove completely remaining first sample grid in first grid slot；
Step S6, it fills in metal to first grid slot and is ground, nationality is stacked by the remaining exposure mask on the second sample grid
Ensure the second sample grid during the grinding process from damage.
2. the preparation method of PSM alignment mark structure as described in claim 1, which is characterized in that the exposure mask, which stacks, includes
Oxide skin(coating) and the silicon nitride layer for covering the oxide skin(coating).
3. the preparation method of PSM alignment mark structure as claimed in claim 2, which is characterized in that in the step S3, move
Except a part of mask stack poststack on the second sample grid, retain on the second sample grid part mask stack it is folded in, the nitrogen
SiClx layer with a thickness of 450-500 angstroms, oxide skin(coating) with a thickness of 50-90 angstroms.
4. the preparation method of PSM alignment mark structure as claimed in claim 2, which is characterized in that right in the step S4
After remaining exposure mask on second sample grid stacks progress part removal, the remaining silicon nitride on the second sample grid
Layer with a thickness of 50-100 angstroms.
5. the preparation method of PSM alignment mark structure as described in claim 1, which is characterized in that the shallow trench isolation knot
The depth of structure is 150-250 angstroms.
6. the preparation method of PSM alignment mark structure as described in claim 1, which is characterized in that the material of the dielectric layer
For oxide.
7. the preparation method of PSM alignment mark structure as described in claim 1, which is characterized in that in step S4 and step S6
In, the grinding is chemical mechanical grinding.
8. the preparation method of PSM alignment mark structure as described in claim 1, which is characterized in that the first sample grid and
The second sample grid are for polysilicon or are amorphous carbon.
9. the preparation method of PSM alignment mark structure as described in claim 1, which is characterized in that the metal is Al.
10. the preparation method of PSM alignment mark structure as described in claim 1, which is characterized in that removing first sample grid
Later, and before filling metal, the surface that one layer of high k dielectric layer is covered on the exposure of first grid slot is first prepared.
11. the preparation method of PSM alignment mark structure as described in claim 1, which is characterized in that the method is applied to
In the technique of 28nm high-dielectric constant metal grid pole.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103137657A (en) * | 2011-11-25 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor integrated device and forming method thereof |
| CN103854987A (en) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Dummy gate forming method, silicon selective deposition method and plug forming method |
| CN104037118A (en) * | 2013-03-04 | 2014-09-10 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
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| JP4768469B2 (en) * | 2006-02-21 | 2011-09-07 | 株式会社東芝 | Manufacturing method of semiconductor device |
| US8334184B2 (en) * | 2009-12-23 | 2012-12-18 | Intel Corporation | Polish to remove topography in sacrificial gate layer prior to gate patterning |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137657A (en) * | 2011-11-25 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor integrated device and forming method thereof |
| CN103854987A (en) * | 2012-12-04 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Dummy gate forming method, silicon selective deposition method and plug forming method |
| CN104037118A (en) * | 2013-03-04 | 2014-09-10 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
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