CN105989886A - Nonvolatile semiconductor memory device - Google Patents

Abstract

The present invention provides a nonvolatile semiconductor memory device, which is used to suppress the breakdown of low voltage transistors constituting a bit line selection circuit. In a P-well, a NAND string unit (NU) and transistors (BLSe, BLSo, BIASe, BIASo) constituting the bit line selection circuit are formed. During an erase operation, the transistors (BLSe, BLSo, BIASe, BIASo) are set to a floating state, and when an erase voltage is applied to the P-well, the transistors (BLSe, BLSo, BIASe, BIASo) are boosted. When the erase voltage is discharged from the P-well, the gates of the transistors (BLSe, BLSo, BIASe, BIASo) are connected to a reference potential through a discharge circuit (410), and the gate voltage is discharged in a manner that follows the P-well voltage.

Description

non-volatile semiconductor storage device

technical field

The present invention relates to a non-volatile semiconductor storage device, in particular to a NotAND (NAND for short) type flash memory (flash memory).

Background technique

The NAND flash memory is composed of a memory block array, and the memory block array is formed by arranging a plurality of NAND strings along the column direction. The NAND string is composed of a plurality of memory cells connected in series and selection transistors (transistors) connected to both ends thereof, one end of which is connected to the bit line through a selection transistor on the bit line side, and the other One end is connected to the source line via a source line selection transistor. Data (data) is read or programmed (program) (written) through bit lines connected to the NAND strings.

FIG. 1 is a block diagram showing a bit line selection circuit of a conventional NAND flash memory. Here, a pair of bit lines of an even bit line BLe and an odd bit line BLo is shown. The bit line selection circuit 10 has: a first selection unit 20 including a bit line selection transistor BLC for connecting an even bit line BLe or an odd bit line BLo to a readout (sence) circuit; The selection unit 30 includes an even bias transistor (bias transistor) BIASe and an odd bias transistor BIASo, an even bit line selection transistor BLSe, and an odd bit line selection transistor BLSo, and the even bias transistor BIASe and the odd bias transistor BIASo are used for The bias voltage VPRE is applied to the even bit line BLe and the odd bit line BLo, the even bit line selection transistor BLSe is used to connect the even bit line BLe to the bit line selection transistor BLS, and the odd bit line selection transistor BLSo is used to connect the odd bit line BLo is connected to the bit line selection transistor BLC. Such a bit line selection circuit 10 is connected to a readout circuit 40 . Here, the second selection part 30 is formed on a P substrate different from the P well region forming the cell array (cell array). , so that all bit lines are boosted to the erase voltage. On the other hand, since the P substrate is 0V (Ground (GND, GND for short)), the even-numbered bias transistor BIASe and the odd-numbered bias transistor BIASo, the even-numbered bit line selection transistor BLSe, and the odd-numbered bit line selection transistor constituting the second selection unit 30 The transistor BLSo includes a high voltage (High Voltage, HV for short) transistor having a thick gate oxide film, a long gate length, and a high withstand voltage.

In Patent Document 1, Patent Document 2, and Non-Patent Document 1, as shown in FIG. 2 , the second selection section 30A of the bit line selection circuit 10A includes a low voltage (Low Voltage, LV for short) transistor, and the second selection section Between 30A and the first selection unit 20, a relay unit 32 including a high voltage (HV) transistor BLS is provided. The transistors BIASe, BIASo, BLSe, and BLSo constituting the second selection unit 30A are formed in the block 50 of the memory array (memory array) forming the NAND string unit NU, that is, in the P well 60, and the transistors BIASe, BIASo, BLSe, and BLSo are in the P well 60. A low-voltage (LV) transistor formed in the same process as a memory cell, with a short gate length and a thin gate oxide film. The transistor BLS of the relay part 32 is arranged outside the P well 60 forming the memory cell array, and the transistor BLC of the first selection part 20 is separated from the transistor of the second selection part 30A. By configuring the second selection unit 30A as a low-voltage transistor, the layout area occupied by the second selection unit 30A can be reduced, and the overall memory size can be reduced. On the other hand, during the erasing operation, an erasing voltage or an erasing pulse (pulse) of about 20 V is applied to the P well 60, but at this time, the gates of all the transistors constituting the second selection portion 30A are set to float ( floating), the gate of the transistor is boosted to near the erasing voltage due to capacitive coupling with the P well 60 . Therefore, a large potential difference is not applied to the gate oxide films of the transistors BIASe, BIASo, BLSe, and BLSo, thereby avoiding break down of the gate oxide films.

prior art literature

patent documents

Patent Document 1: Japanese Patent No. 5550609

Patent Document 2: Japanese Patent Laid-Open No. 2011-23661

Non-Patent Literature 1: K. Fukuda.Et al., "151mm ² 64GbMLC NAND Memory Using 24n CMOS Technology", IEEE International Solid-State Circuits Conference, Technical Literature Abstracts P198-199, No. 11, 2011 (K.Fukuda.Et al., "A 151mm ² 64Gb MLC NAND Memory in 24n, CMOS Technology", IEEE International Solid-State Circuit Conference, Digest of Technical Paper P198-199, Session 11, 2011)

Contents of the invention

[Problem to be Solved by the Invention]

As described above, by forming the transistors BIASe, BIASo, BLSe, and BLSo of the second selection unit 30A in the P well 60 which is the block 50 of the memory array, the occupied area of the second selection unit 30A can be reduced. However, such a configuration of the second selection unit 30A causes the following problems.

During the erase operation, the transistors BIASe, BIASo, BLSe, and BLSo of the second selection unit 30A are set to a floating state, and the gate voltage Vgate of the transistors BIASe, BIASo, BLSe, and BLSo is equal to the erase voltage Vers applied to the P well 60 . When rising, the voltage is gradually boosted due to the capacitive coupling with the P-well voltage Vpw. The peak value of the applied erasing voltage Vers is, for example, about 20 V, and the erasing voltage Vers maintains the peak voltage for a fixed period so that electrons are sufficiently released from the memory cell to the P well 60 . When the application of the erasing voltage Vers ends, the P-well voltage Vpw is discharged, and accordingly, the gate voltage Vgate of the transistor also gradually decreases.

However, wiring extending beyond the P well 60 is connected to the gates of the transistors BIASe, BIASo, BLSe, and BLSo. Therefore, the gate voltage Vgate may be affected by the P-type silicon substrate or other wells located directly below the wiring. Influenced by the parasitic capacitance between the wirings and the parasitic capacitance between adjacent wirings, it does not decrease following the decrease of the P well voltage Vpw.

FIG. 3 is a graph schematically showing the P-well voltage Vpw and the gate voltage Vgate of the transistors BIASe, BIASo, BLSe, and BLSo. The P-well voltage Vpw is indicated by a solid line, and the gate voltage Vgate is indicated by a dotted line. At time t0, 0 V is applied to the word line (word line) WL of the selected block, and the transistors BIASe, BIASo, BLSe, and BLSo are brought into a floating state. At time T1 , erase voltage Vers is applied to P well 60 . For example, an erase pulse whose voltage is gradually increased is applied to the P well. In response to the application of the erase pulse, the P-well voltage Vpw starts to increase. At the same time, the gate voltage Vgate of the transistors BIASe, BIASo, BLSe, BLSo coupled with the P-well capacitance is boosted. At time T2, P-well voltage Vpw is boosted to approximately 20V, and electrons are extracted from the floating gate to P-well 60 while maintaining a constant time required for erasing during time T2 to T3.

During erasing periods T2 to T3 , the gate voltages Vgate of the transistors BIASe, BIASo, BLSe, and BLSo are set to a fixed potential or lower in accordance with the coupling ratio with the P well 60 . As shown in FIG. 3, unless the potential difference Va between the P-well voltage Vpw and the gate voltage Vgate of the transistor is set below a fixed value, the transistor will suffer from time-dependent breakdown due to time-dependent dielectric breakdown characteristics (TimeDependent Dielectric Breakdown). Breakdown, TDDB for short). TDDB is a phenomenon in which a transistor breaks down if a voltage is applied for a long time even if a high voltage is not applied to the gate of the transistor. Therefore, the coupling ratio between the transistor and the P well is set so that Va<TDDB is satisfied.

At time T3, the application of the erase voltage Vers ends, and the P well voltage Vpw is discharged. When discharge starts, a discharge path is connected to the P well 60 , and charges are discharged through the discharge path, so the P well voltage Vpw drops relatively quickly. On the other hand, the gates of the transistors BIASe, BIASo, BLSe, and BLSo are not connected to a discharge path for discharging their charges, and furthermore, wirings having parasitic capacitances are connected to the gates, so the gate voltage Vgate The discharge speed is slower than the P-well voltage Vpw. As a result, at time T4, when the P-well voltage Vpw reaches 0V, the gate voltage Vgate of the transistor is still at the voltage Vb. If Vb>TDDB, the transistors BIASe, BIASo, BLSe, and BLSo may be broken down.

Therefore, an object of the present invention is to solve the problems of the prior art described above, and to provide a semiconductor memory device capable of suppressing breakdown of low-voltage transistors constituting a bit line selection circuit.

[Technical means to solve the problem]

The semiconductor storage device of the present invention comprises: a memory cell array, forming a plurality of NAND strings, and the NAND strings are electrically rewritable memory cells connected in series; an erasing unit for erasing the memory cell array memory cells in the selected block; and a bit line selection circuit, which selects the bit lines respectively connected in series with the NAND, at least one bit line selection transistor constituting the bit line selection circuit is formed in the well, The well forms a memory cell, and the erasing unit includes: a first unit for applying an erasing voltage to the well of the selected block; a second unit for applying the at least 1 The bit line selection transistors are placed in a floating state; and the third means discharges the gate of the at least one bit line selection transistor to a reference potential when discharging the voltage of the well of the selected block.

Preferably, the third member forms a discharge path between the gate of the at least one bit line selection transistor and a reference potential.

Preferably, the third component includes a first discharge transistor for generating a discharge path between the gate of the at least one bit line selection transistor and a reference potential, and the first The discharge transistor is turned on when the voltage of the well is discharged.

Preferably, the third member includes at least one diode connected in series to the first discharge transistor between the gate of the at least one bit line selection transistor and a reference potential.

Preferably, the at least one diode generates a fixed potential difference between the gate of the at least one bit line selection transistor and the well during the discharge period, and the fixed potential difference is smaller than the at least 1 Time-dependent dielectric breakdown of a bit line select transistor.

Preferably, the third component includes a second discharge transistor and a third discharge transistor, the second discharge transistor is used to generate a discharge path between the well and a reference potential, and the third discharge transistor is used to generate a discharge path between the well and a reference potential. A discharge path is generated between the source line commonly connected to the NAND string of the well and the reference potential, and a common discharge enable signal is supplied to each gate of the first discharge transistor, the second discharge transistor, and the third discharge transistor .

Preferably, when the voltage of the well and the voltage of the source line are discharged to a reference potential through the second discharge transistor and the third discharge transistor, the at least one diode has a voltage higher than that of the at least one bit. The threshold of the line select transistor is large.

Preferably, the at least one bit line selection transistor includes an even bit line selection transistor for selecting an even bit line, and an odd bit line selection transistor for selecting an odd bit line, the even bit line selection transistor and the The odd-numbered bit line selection transistor is turned on so that the voltage at the common node of both is discharged to the reference potential.

Preferably, the at least one diode includes a transistor having a withstand voltage higher than that of the at least one bit line selection transistor.

Preferably, the bit line selection circuit includes an even bias transistor for applying a bias voltage to an even bit line, and an odd bias transistor for applying a bias voltage to an odd bit line, and the third component makes the even bias transistor and the respective gates of the odd bias transistors are discharged.

(effect of invention)

According to the present invention, a discharge path is generated between the gate of at least one bit line selection transistor and the reference potential, so the gate voltage of the bit line selection transistor follows the erase voltage of the P well, even if the bit line selection transistor is set to The low voltage structure can also avoid its breakdown.

Description of drawings

Fig. 1 is the structure diagram that represents the bit line selection circuit of the NAND type flash memory of prior art;

Fig. 2 is the structure diagram that represents the bit line selection circuit of the NAND type flash memory of prior art;

3 is a graph showing the P well voltage and the gate voltage of the transistor of the bit line selection circuit in the prior art NAND flash memory;

Fig. 4 is a block diagram showing an example of the overall structure of the NAND type flash memory of the embodiment of the present invention;

5 is an equivalent circuit diagram representing a NAND string;

6 is a schematic cross-sectional view showing the structure of a memory cell array;

FIG. 7 is a structural schematic diagram showing floating and discharging of even-numbered bit line selection transistors constituting the bit line selection circuit;

8 is a time chart (time chart) illustrating the time relationship between the erasing voltage and the discharge during the erasing operation;

FIG. 9 is a graph showing the relationship between the gate voltage of transistors constituting the bit line selection circuit and the P well voltage.

Explanation of reference signs:

10, 10A: bit line selection circuit;

20: 1st choice part;

30, 30A: the second option;

32: relay unit;

40: readout circuit;

50. BLK(0)～BLK(m): block;

60, 230: P well;

100: flash memory;

110: memory array;

120: input/output buffer;

130: address register;

140: cache memory;

150: controller;

160: word line selection circuit;

170: page buffer/readout circuit;

180: column selection circuit;

190: Internal voltage generating circuit;

200: system clock generating circuit;

210: silicon substrate;

220: N well;

222: n+ diffusion area;

250, 260: n-type diffusion regions;

270: p+ diffusion area;

280: contact part;

290, 292: diffusion area;

300: drive circuit;

400: discharge circuit;

410: the first discharge circuit;

420: the second discharge circuit;

Ax: row address information;

Ay: column address information;

BIASe: even bias transistor;

BIASo: Odd Bias Transistor;

BL0～BLn: bit lines;

BLC: bit line selection transistor;

BLe: even bit line;

BLo: Odd bit line;

BLS: bit line select transistor;

BLSe: even bit line select transistor;

BLSo: Odd bit line select transistor;

C1, C2, C3: control signal;

CLK: internal system clock;

D1, D2: Diodes;

DEN: discharge enable signal;

FEN: floating enable signal;

H, L: level;

L1, L2: Wiring;

MC0～MC31: storage unit;

N: node;

NU: NAND string unit;

Q1: drive transistor;

Q2, Q3, Q4, Q5: discharge transistors;

SGD, SGS: select the gate line;

SL: source line;

T0, T1, T2, T3, T4: time;

TD: bit line side selection transistor;

TS: source line side selection transistor;

WL0～WL31: word line;

Va: potential difference;

Vb: voltage;

Vers: erase voltage;

Vgate: gate voltage;

Vpass: pass voltage;

VPRE: imaginary potential;

Vprog: programming voltage;

Vpw: P well voltage;

Vread: read voltage;

Vth: Threshold.

detailed description

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, it should be noted that in the drawings, each part is emphasized for easy understanding, and the scale of the actual device (device) is not the same.

FIG. 4 is a block diagram showing a configuration example of a NAND-type flash memory according to an embodiment of the present invention. As shown in FIG. 4 , the flash memory 100 includes: a memory array 110 formed with a plurality of memory cells arranged in a matrix; an input/output buffer (buffer) 120 connected to an external input/output terminal I/O; An address register (address register) 130 receives address data from the input/output buffer 120; a cache memory (cache memory) 140 keeps input/output data; a controller 150 generates control signals C1, C2, C3, etc. The control signals C1, C2, C3, etc. are based on command data (command data) from the input/output buffer 120 and external control signals (not shown chip enable or address latch enable (address latch enable), etc.) The word line selection circuit 160 decodes (decodes) the row address information Ax from the address register 130, and performs block selection and word line selection based on the decoding result; page buffer/readout The circuit 170 holds the data read out through the bit line, or holds the programming data through the bit line, etc.; the column selection circuit 180 decodes the column address information Ay from the address register 130, and performs bit line selection based on the decoding result. selection, etc.; the internal voltage generating circuit 190 generates voltages required for data reading, programming (writing) and erasing (programming voltage Vprog, pass voltage Vpass, readout voltage Vread, erase erasing voltage Vers (including erasing pulse, etc.); and a system clock generating circuit 200 for generating an internal system clock CLK.

The memory array 110 has a plurality of blocks BLK(0), BLK(1), . . . , BLK(m) arranged in the column direction. At one end of the block, a page buffer/read circuit 170 is arranged. However, the page buffer/read circuit 170 may be arranged at the other end of the block or at both ends.

In one block, as shown in Figure 5, a plurality of NAND string units NU formed by connecting multiple memory cells in series are formed, and in one block, n+1 string units are arranged along the row direction Nu. The string unit NU includes: a plurality of memory cells MCi (i=0, 1, . TS is connected to the other end of the memory cell MC0, the drain of the bit line side selection transistor TD is connected to a corresponding bit line BL, and the source of the source line side selection transistor TS is connected to a common source Polar Line SL. The control gate of memory cell MCi is connected to word line WLi, the gate of selection transistor TD on the bit line side is connected to selection gate line SGD, and the selection transistor TS on the source line side is connected to selection gate line SGS. When selecting a block based on the row address Ax, the word line selection circuit 160 selectively drives the selection transistors TD, TS through the selection gate lines SGS, SGD of the block.

The memory cell typically has a Metal Oxide Semiconductor (MOS) structure, and the MOS structure includes: a source/drain as an N-type diffusion region formed in a P well; a tunnel (tunnel) oxide film, Formed on a channel between source/drain electrodes; a floating gate (charge accumulating layer) formed on a tunnel oxide film; and a control gate formed on the floating gate through a dielectric film. When there is no charge accumulated in the floating gate, that is, when data "1" is written, the threshold is in a negative state, and the control gate of the memory cell is turned on at 0V. When electrons are accumulated in the floating gate, that is, when data "0" is written, the threshold shift (shift) is positive, and the control gate of the memory cell is turned off at 0V. Wherein, the storage unit is not limited to storing a single bit, but may also store multiple bits.

Column selection circuit 180 includes bit line selection circuit 30A shown in FIG. 2 . The bit line selection circuit 30A is formed in a P well forming a memory cell as will be described later. Preferably, the bit line selection circuits 30A are formed in the P wells of the respective blocks. The operation of the bit line selection circuit 30A is controlled by the controller 150 during reading, programming, and erasing. For example, when reading the selected page, when the even bit line BLe is selected, the odd bit line BLo is not selected, the even bit line selection transistor BLSe and the bit line selection transistor BLS are turned on, and the odd bit line The selection transistor BLSo is turned off, the even bias transistor BIASe is turned off, the odd bias transistor BIASo is turned on, and a shield potential is supplied from the virtual power supply VPRE. Moreover, when the odd bit line BLo is selected, the even bit line BLe is not selected, the odd bit line selection transistor BLSo and the bit line selection transistor BLS are turned on, the even bit line selection transistor BLSe is turned off, and the odd bias transistor BIASo is turned off. , the even-numbered bias transistor BIASe is turned on, and the shield potential is supplied from the virtual power supply VPRE. During programming, the odd-numbered bias transistor BIASo and the even-numbered bias transistor BIASe can supply a program inhibit voltage from the virtual power supply VPRE to a write-inhibited bit line.

The following table is a table showing an example of the bias voltage applied at each operation of the flash memory:

In the read operation, a certain positive voltage is applied to the bit line, a certain voltage (such as 0V) is applied to the selected word line, a pass voltage Vpass (such as 4.5V) is applied to the non-selected word line, and a certain voltage (such as 4.5V) is applied to the selected gate line SGD, SGS applies a positive voltage (for example, 4.5V) to turn on the selection transistor TD on the bit line side and the selection transistor TS on the source line side, and applies 0V to the common source line. During the programming (writing) operation, a high-voltage programming voltage Vprog (15V to 20V) is applied to the selected word line, and an intermediate potential (for example, 10V) is applied to the unselected word line to turn on the selection transistor TD on the bit line side. When turned on, the source line side select transistor TS is turned off, and a potential corresponding to the data of "0" or "1" is supplied to the bit line BL. During the erasing operation, 0V is applied to the selected word line in the block, and a high voltage (such as 20V) is applied to the P well as the erasing voltage Vers, and the electrons in the floating gate are extracted to the substrate, thereby using the block as a unit to erase data.

6 is a schematic cross-sectional view showing a memory cell array. It should be noted that only the NAND string unit NU connected to the even bit line BLe, the even bit line selection transistor BLSe and the even bit line selection transistor BLSe constituting the bit line selection circuit 30A are illustrated here. Bias transistor BIASe. An N well 220 is formed in a P-type silicon substrate 210 , and a P well 230 is formed in the N well 220 . One P well 230 corresponds to one block, and transistors constituting the NAND string unit NU are formed in the P well 230 . Furthermore, in the P well 230, the even bit line selection transistor BLSe and the even bias transistor BIASe constituting the second selection section 30A shown in FIG. 2 are formed.

The source line SL is connected to the n-type diffusion region 250 of the source line selection transistor TS, and the even bit line BLe is connected to the n-type diffusion region 260 of the bit line selection transistor TD. The p+ diffusion region 270 of the P well 230 and the n+ diffusion region 222 of the N well 220 are connected to a contact 280 shared by N well/P well. The common contact portion 280 is connected to the internal voltage generating circuit 190 , and is applied with the erase voltage Vers during the erase operation, or the voltage of the P-well is discharged through the contact portion 280 . Furthermore, the even bit line BLe is connected to the diffusion region 290 which forms a common node between the even bit line selection transistor BLSe and the even bias transistor BIASe formed in the P well 230, and the virtual power supply VPRE is connected to the even bias transistor BIASe. Another diffusion region 292 of . The even bit line selection transistor BLSe and the even bias transistor BIASe are low-voltage N-type MOS transistors formed by the same process as the memory cell.

FIG. 7 is a diagram showing a discharge circuit and a drive circuit connected to a bit line selection circuit. It should be noted that only the discharge circuit and drive circuit connected to the even-numbered bit line selection transistor BLSe constituting the bit line selection circuit 30A are shown here. PW in FIG. 7 refers to a P well. The odd bit line selection transistor BLSo, the even bias transistor BIASe, and the odd bias transistor BIASo constituting the bit line selection circuit 30A are connected to the same discharge circuit and drive circuit as the even bit line selection transistor BLSe.

The column selection circuit 180 includes a driving circuit 300 and a discharging circuit 400 . The drive circuit 300 and the discharge circuit 400 are formed in a P-type silicon substrate, or formed in a well different from the P well 230 . The drive circuit 300 is connected to the node N connected to the gate of the even-numbered bit line selection transistor BLSe via the line L1. The driving circuit 300 includes an N-type driving transistor Q1 connected to a node N. The gate of the driving transistor Q1 is connected to the floating enable signal FEN, and during the erasing operation, the floating enabling signal FEN transitions to L level, and the driving transistor Q1 is turned off. As a result, the even-numbered bit line selection transistor BLSe is set in a floating state. In addition, the driving circuit 300 properly drives the driving transistor Q1 at the time of reading or programming, but the description thereof is omitted here.

Furthermore, a discharge circuit 400 is connected to the gate of the even bit line selection transistor BLSe via a line L2. The discharge circuit 400 includes a first discharge circuit 410 for discharging the gate of the even-numbered bit line selection transistor BLSe and a second discharge circuit 420 for discharging the nodes of the P well 230 , source line SL, and virtual power supply VPRE during an erase operation.

The first discharge circuit 410 includes two diodes D1 and D2 connected in series to the gate of the even bit line selection transistor BLSe and a discharge transistor Q2. The discharge transistor Q2 is connected between the diode D2 and the reference potential (GND), and a discharge enable signal DEN is connected to its gate. When the discharge enable signal DEN is at the H level, the discharge transistor Q2 is turned on, and the gate of the even bit line selection transistor BLSe is electrically connected to the reference potential through the line L2 to form a discharge path between the node N and the reference potential.

The diodes D1 and D2 each have a threshold value Vth, and by connecting the two diodes D1 and D2 in series, a bias voltage shifted by 2 Vth from the reference potential is applied to the gate of the even-numbered bit line selection transistor BLSe. When the P-well voltage Vpw is discharged, the diodes D1 and D2 make the voltage of the node N follow the P-well voltage Vpw so as to decrease from the P-well voltage Vpw by approximately 2Vth, and when the P-well voltage Vpw is discharged to approximately 0V, the even-numbered bits The line selection transistor BLSe is turned on. In this example, two diodes D1 and D2 are connected in series, but this is just an example, and the number of diodes is not necessarily limited to this. The number of diodes is sufficient as long as the difference between the node N and P well voltage Vpw is equal to or less than the breakdown voltage of TDDB and greater than the threshold value of the even-numbered bit line selection transistor BLSe. In addition, the diodes D1 and D2 and the discharge transistor Q2 include transistors having a voltage higher than that of the even-numbered bit line selection transistor BLSe.

The second discharge circuit 420 includes a discharge transistor Q3 connected to the P well 230 , a discharge transistor Q4 connected to the source line SL, and a discharge transistor Q5 connected to the virtual power supply VPRE. The gates of the discharge transistors Q3, Q4, and Q5 are jointly connected with the discharge enable signal DEN. When the discharge enable signal DEN is at H level, the discharge transistors Q3, Q4, and Q5 are turned on, and the P well 230, the source The line SL and the virtual potential VPRE are electrically connected to the reference potential and discharged. The discharge transistors Q3, Q4, and Q5 include transistors having a higher voltage than the even-numbered bit line selection transistor BLSe.

Next, the erase operation of this embodiment will be described with reference to the time chart of FIG. 8 . When an erase command, a row address, etc. are sent to the flash memory 100 from an external host device, the controller 150 selects a block to be erased and executes an erase sequence. At time T0 , the driving circuit 300 transitions the floating enable signal FEN to L level to turn off the driving transistor Q1 . As a result, the transistors BIASe, BIASo, BLSe, and BLSo in the P-well 230 of the selected block are brought into a floating state. Then, the bit line selection transistor TD and the source line selection transistor TS of the selected block are set in a floating state, and 0 V is applied to the word line. Then, at time T1 , the erase voltage Vers generated by the internal voltage generating circuit 190 is applied to the P well 230 and the N well 220 through the contact portion 280 . With the application of the erasing voltage Vers, the P well voltage Vpw reaches approximately 20V at times T2 to T3, during which time the memory cells of the selected block are erased. At time T3, the application of the erasing voltage Vers ends, and at time T3-T4, the discharge enable signal DEN transitions to H level, and the discharge transistors Q2, Q3, Q4, and Q5 are turned on. Thus, a discharge path is generated between each gate of the transistors BIASe, BIASo, BLSe, and BLSo and the reference potential, and further, a discharge path is generated between the P well 230, the source line SL, the virtual power supply VPRE, and the reference potential, and the transistor Each gate of BIASe, BIASo, BLSe, BLSo, P well, source line SL, and virtual power supply VPRE are discharged through each discharge path.

FIG. 9 is a graph showing the relationship between the P well voltage Vpw and the gate voltage Vgate of the transistors BIASe, BIASo, BLSe, and BLSo. As illustrated in FIG. 8, at time T3, the application of the erasing voltage Vers ends, and at the same time, the discharge enable signal DEN becomes active, and the P well, the source line SL, the virtual power supply VPRE, and the transistors BIASe, BIASo, Charges of the respective gates of BLSe and BLSo are discharged to the reference potential through the discharge path.

The gate voltage Vgate of the transistors BIASe, BIASo, BLSe, and BLSo drops due to capacitive coupling with the P well 230 , and discharge is promoted by creation of a discharge path through the wiring L2 , diodes D1 , D2 , and the discharge transistor Q2 . The gate voltage Vgate follows the P-well voltage Vpw so that the potential difference with the P-well 230 does not exceed about 2Vth. That is, the discharge slope of the gate voltage Vgate is substantially similar to the discharge slope of the P-well voltage Vpw, and follows the P-well voltage Vpw with a difference of 2Vth. Therefore, during the discharge period, the voltage applied to the transistors BIASe, BIASo, BLSe, and BLSo is controlled so as to be smaller than the breakdown voltage of TDDB.

Then, at time T4, the nodes of the P-well voltage Vpw, the source line SL, and the virtual power supply VPRE are discharged to approximately 0V. On the other hand, the gate voltage Vgate of the transistors BIASe, BIASo, BLSe, and BLSo is discharged to about 2Vth through the diodes D1, D2. Here, if the common node BLn of the even bit line selection transistor BLSe and the odd bit line selection transistor BLSo discharges slowly so that its voltage remains high, the low voltage even bit line selection transistor BLSe and the odd bit line selection transistor BLSo has the possibility of breakdown. However, if the P well voltage Vpw becomes 0V, the voltage of the bit line BL will also become 0V, and if the gate voltage Vgate is 2Vth, the even bit line selection transistor BLSe and the odd bit line selection transistor BLSo are turned on, so the common The node BLn is electrically connected to GND, so the voltage of the common node BLn can be discharged to about 0V.

Thus, according to this embodiment, during the erasing operation, each gate of the transistors BIASe, BIASo, BLSe, and BLSo of the bit line selection circuit 30A is boosted by capacitive coupling with the P well 230, and then the P well When the voltage is discharged, each gate is discharged through the discharge path so as to follow the discharge of the P well voltage, so that the breakdown phenomenon of the transistors BIASe, BIASo, BLSe, and BLSo due to TDDB and the like can be suppressed.

In addition, in the above-mentioned embodiments, an example in which the memory cell stores 1-bit data is shown, but the memory cell may also store multi-bit data. Furthermore, in the above-mentioned embodiments, an example in which the NAND strings are formed on the surface of the substrate is shown, but the NAND strings may also be formed three-dimensionally on the surface of the substrate.

As mentioned above, although the preferred embodiment of this invention was described in detail, this invention is not limited to a specific embodiment, Various deformation|transformation and changes are possible within the range of the summary of this invention.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (10)

1. A semiconductor storage device, characterized in that, comprising: The memory cell array is formed with a plurality of NAND strings, and the NAND strings are electrically rewritable memory cells connected in series; an erasing unit for erasing memory cells in a selected block of the memory cell array; and a bit line selection circuit that selects the bit lines respectively connected in series with the NAND, at least one bit line selection transistor constituting the bit line selection circuit is formed in a well, the well forms a memory cell, The erasing components include: The first component applies an erasing voltage to the well of the selected block; A second means of setting the at least one bit line selection transistor formed in the well of the selected block to a floating state; and The third means discharges the gate of the at least one bit line selection transistor to the reference potential when the voltage of the well of the selected block is discharged. 2. The semiconductor memory device according to claim 1, wherein: The third means creates a discharge path between the gate of the at least one bit line selection transistor and a reference potential. 3. The semiconductor memory device according to claim 1 or 2, wherein: The third component includes a first discharge transistor for generating a discharge path between the gate of the at least one bit line selection transistor and a reference potential, and the first discharge transistor is connected between the gate and the reference potential. The well is turned on when the voltage of the well is discharged. 4. The semiconductor memory device according to claim 3, wherein: The third member includes at least one diode connected in series to the first discharge transistor between the gate of the at least one bit line selection transistor and a reference potential. 5. The semiconductor memory device according to claim 4, wherein: The at least one diode generates a fixed potential difference between the gate of the at least one bit line selection transistor and the well during the discharge period, and the fixed potential difference is smaller than that of the at least one bit line selection transistor. Dielectric breakdown of transistors over time. 6. The semiconductor memory device according to claim 1 or 2, wherein: The third component includes a second discharge transistor and a third discharge transistor, the second discharge transistor is used to generate a discharge path between the well and a reference potential, and the third discharge transistor is used to connect to the well A discharge path is formed between the source line commonly connected to the NAND string and the reference potential, and a common discharge enable signal is supplied to each gate of the first discharge transistor, the second discharge transistor, and the third discharge transistor. 7. The semiconductor memory device according to claim 6, wherein: When the voltage of the well and the voltage of the source line are discharged to the reference potential through the second discharge transistor and the third discharge transistor, the at least one diode has a voltage higher than that of the at least one bit line selection transistor. Threshold large threshold. 8. The semiconductor memory device according to claim 6, wherein: The at least one bit line selection transistor includes an even bit line selection transistor for selecting an even bit line and an odd bit line selection transistor for selecting an odd bit line, the even bit line selection transistor and the odd bit line The selection transistor is turned on so that the voltage of the common node of both is discharged to the reference potential. 9. The semiconductor memory device according to claim 1 or 2, wherein: The at least one diode includes a transistor having a withstand voltage higher than that of the at least one bit line selection transistor. 10. The semiconductor memory device according to claim 1 or 2, wherein: The bit line selection circuit includes an even bias transistor for applying a bias voltage to an even bit line, and an odd bias transistor for applying a bias voltage to an odd bit line, and the third part makes the even bias transistor and the odd bias transistor Each gate of the bias transistor is discharged.