CN105977265B - Array substrate and its manufacturing method - Google Patents

Abstract

The invention discloses a kind of array substrate and its manufacturing methods.Method includes: to provide a glass substrate, and deposit the first metal layer on the glass substrate；It is sequentially depositing gate insulation layer and semiconductor layer on the first metal layer；ITO layer is set on the semiconductor layer；Protective layer and second metal layer are set gradually on the ito layer, wherein second metal layer are arranged using mask plate identical with protective layer on the protection layer, second metal layer is connect by second metal layer by a contact hole with ITO layer.In the above manner, the present invention can reduce by a mask plate process, the process time is saved while cost is reduced.

Description

Array substrate and manufacturing method thereof

technical field

The present invention relates to the technical field of display panels, in particular to an array substrate and a manufacturing method thereof.

Background technique

Active Matrix (AMLCDs) uses thin film transistors (ThinFilm Transistor, TFT) as a switch structure when driving liquid crystal pixels. Generally, Metal1 is used as a gate (gate), and Metal2 is used as a corresponding source (source) and drain (drain), forming a TFT switch. At the same time, the two metal layers of Metal1 and Metal2 are respectively used for scanning lines and data lines for transmitting pulse signals. In the array substrate 10 shown in Figures 1a and 1b, a first metal layer 12 and a gate insulating layer 13 are grown sequentially on a glass substrate 11, and a semiconductor layer 14 is grown on the insulating layer 13, on the semiconductor layer 14 and located in the first A second metal layer 16 is grown at both ends of the metal layer, an ohmic contact layer 15 is formed between the second metal layer 16 and the semiconductor layer 14, and a buffer layer 17 and tin-doped indium oxide (Indium Tin oxide) are sequentially formed on the second metal layer 16. Oxide, ITO) layer 18. Wherein, the first metal layer 12 is the grid electrode of the TFT and the common electrode of the array substrate 10, the second metal layer 16 is the source/drain of the TFT, and the ITO layer 18 forms the pixel electrode 19 of the array substrate 10, through a contact hole and source connection.

The pulse signal transmitted by the second metal layer 16 as the data line is transmitted to the pixel electrode through the contact hole connecting the source electrode and the pixel electrode when the TFT switch is turned on, so as to achieve the purpose of deflecting the liquid crystal. However, such a contact hole requires a special photomask, which increases the manufacturing cost of the photomask.

Contents of the invention

Embodiments of the present invention provide an array substrate and a manufacturing method thereof, which can reduce a mask plate process, and save process time while reducing costs.

The present invention provides a method for manufacturing an array substrate, comprising: providing a glass substrate, and depositing a first metal layer on the glass substrate; sequentially depositing a gate insulating layer and a semiconductor layer on the first metal layer; disposing ITO on the semiconductor layer layer; on the ITO layer, a protective layer and a second metal layer are arranged in sequence, wherein, the second metal layer is arranged on the protective layer using the same mask as the protective layer, and the second metal layer connects the second metal layer to the second metal layer through a contact hole. Connect with ITO layer.

Wherein, the first metal layer is the common electrode and the gate of the thin film transistor, and the ITO layer is used as the pixel electrode and the source/drain of the thin film transistor.

Wherein, the step of arranging the second metal layer on the protective layer by using the same mask as the protective layer includes: depositing the second metal layer on the protective layer; A mask plate is used to perform photolithography on the second metal layer, so that the second metal layer is left in the part where the protective layer is hollowed out.

Wherein, the step of sequentially arranging the protective layer and the second metal layer on the ITO layer includes: depositing the protective layer on the ITO layer, wherein the first photoresist is used to perform photolithography on the protective layer to form a contact hole, and the first photoresist is retained after the photolithography. A photoresist; a second metal layer is set on the first photoresist, and the second metal layer is photoetched by using the second photoresist, wherein the characteristics of the second photoresist are the same as those of the first photoresist.

Wherein, the second metal layer is arranged on the first photoresist, and the second metal layer is photoetched by using the second photoresist, wherein the step that the second photoresist has the same characteristics as the first photoresist includes: on the first photoresist Depositing a second metal layer; coating a second photoresist on the second metal layer, and removing the second photoresist except for the contact hole; etching the exposed part of the second metal layer; and etching and removing the second photoresist except for the remaining part a photoresist and a second photoresist.

Wherein, both the first photoresist and the second photoresist are positive photoresist.

Wherein, the gate insulating layer includes a first gate insulating layer and a second gate insulating layer, and the step of sequentially depositing the gate insulating layer and the semiconductor layer on the gate insulating layer includes: quickly depositing the first gate insulating layer by using a plasma chemical vapor deposition method; A plasma chemical vapor deposition method is used to slowly deposit the second gate insulating layer, wherein the thickness of the first gate insulating layer is greater than that of the second gate insulating layer; a plasma chemical vapor deposition method is used to deposit the semiconductor layer.

Wherein, the physical vapor deposition method is used to deposit the first metal layer and the second metal layer, and the sputtering method is used to deposit the ITO layer.

The present invention also provides an array substrate, comprising: a glass substrate; a first metal layer and a gate insulating layer sequentially arranged on the glass substrate; a semiconductor layer arranged on the gate insulating layer; an ITO layer arranged on the semiconductor layer; The protection layer and the second metal layer arranged on the ITO layer, wherein the protection layer and the second metal layer are made by using the same mask plate, and the second metal layer is connected with the ITO layer through a contact hole.

Wherein, the first metal layer is the common electrode and the gate of the thin film transistor, and the ITO layer is used as the pixel electrode and the source/drain of the thin film transistor.

Through the above scheme, the beneficial effects of the present invention are: the present invention deposits the first metal layer on the glass substrate; deposits the gate insulating layer and the semiconductor layer sequentially on the first metal layer; sets the ITO layer on the semiconductor layer; A protective layer and a second metal layer are sequentially provided on the protective layer; wherein, a second metal layer is provided on the protective layer using the same mask as the protective layer, and the second metal layer is connected to the second metal layer and the ITO layer through a contact hole, A mask plate process can be reduced, and the process time is saved while reducing the cost.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort. in:

Figure 1a is a schematic structural view of an array substrate in the prior art;

Figure 1b is a top view of the array substrate in Figure 1a;

FIG. 2a is a schematic structural diagram of an array substrate according to an embodiment of the present invention;

Figure 2b is a top view of the array substrate in Figure 2a;

3 is a schematic flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention;

Fig. 4a is a schematic diagram of forming a TFT in an array substrate according to an embodiment of the present invention;

Fig. 4b is a top view of the array substrate of Fig. 4a;

FIG. 5 is a schematic diagram of forming a protective layer in an array substrate according to an embodiment of the present invention;

6 is a schematic diagram of forming a second metal layer in the array substrate according to the first embodiment of the present invention;

7 is a schematic flow diagram of the formation of the second metal layer in the array substrate according to the second embodiment of the present invention;

8 is a schematic diagram of Step 1 of forming the second metal layer in the array substrate according to the second embodiment of the present invention;

9 is a schematic diagram of Step 2 of forming a second metal layer in the array substrate according to an embodiment of the present invention;

10 is a schematic diagram of Step 3 of forming the second metal layer in the array substrate according to the embodiment of the present invention;

11 is a schematic diagram of Step 4 of forming the second metal layer in the array substrate according to the embodiment of the present invention;

FIG. 12 is a schematic diagram of Step 5 of forming the second metal layer in the array substrate according to the embodiment of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In the embodiment of the present invention, the source and drain of the TFT switching element are made by using the ITO used to make the pixel electrode part in the prior art. See Figure 2a and Figure 2b for the specific structure. Fig. 2a is a schematic structural diagram of an array substrate according to an embodiment of the present invention. Fig. 2b is a top view of the array substrate in Fig. 2a.

The array substrate 20 of the embodiment of the present invention includes: a glass substrate 21, a first metal layer 22 and a gate insulating layer 23 disposed on the glass substrate 21 in sequence, a semiconductor layer 24 disposed on the gate insulating layer 23; a semiconductor layer 24 disposed on the semiconductor layer 24 The ITO layer 25 above; the protection layer 26 and the second metal layer 27 disposed on the ITO layer 25 in sequence. The protective layer 26 and the second metal layer 27 are made by using the same mask, and the second metal layer 27 is connected to the ITO layer 25 through a contact hole 28 . The first metal layer 22 is the common electrode and the gate of the thin film transistor, and the ITO layer 25 is used as the pixel electrode and the source/drain of the thin film transistor.

The array substrate 20 of the embodiment of the present invention uses the ITO layer 25 as the electrode material of the source/drain part of the TFT, so that there is no need to consider the n+ ohmic contact part of the metal and semiconductor of the TFT in common AMLCDs, that is, it does not need to be set as shown in Figure 1 The ohmic contact layer saves a process time. Moreover, since the array substrate 20 adopts a top-layer data line structure (topdate line), the electrode lines can be deposited thicker to reduce the resistance value without considering possible step coverage problems.

FIG. 3 is a schematic flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention. As shown in Figure 3, the manufacturing method of the array substrate:

Step S10 : providing a glass substrate 21 , and depositing a first metal layer 22 on the glass substrate 21 .

Wherein, the first metal layer 22 is the common electrode and the gate of the thin film transistor.

In step S10, the first metal layer 22 (Metal) is deposited using a physical vapor deposition method (PVD Sputter), and then coated with photoresist, exposed, developed, etched, and stripped of photoresist to form scanning lines (Scanning line) and common Electrode (COMline). Here, the first metal layer 22 is formed using a first photomask.

Step S11 : sequentially depositing a gate insulating layer 23 and a semiconductor layer 24 on the first metal layer 22 ; and disposing an ITO layer 25 on the semiconductor layer 24 .

The gate insulating layer includes a first gate insulating layer and a second gate insulating layer. In step S11, the first gate insulating layer (GI-SiNx) is deposited quickly by using plasma chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), and then the second gate insulating layer (GI-SiNx) is deposited slowly by PECVD, To form a better semiconductor layer/insulation layer (a-Si:H/SiNx) interface; wherein, the thickness of the first gate insulation layer is greater than the thickness of the second gate insulation layer. Then PECVD is used to deposit the semiconductor layer (a-Si:H) 24 , apply photoresist, expose, develop, etch, remove the photoresist, and pattern the semiconductor layer 24 . That is, the semiconductor layer 24 in the embodiment of the present invention is formed using a second photomask.

Afterwards, a sputtering method (Sputter) is used to deposit an ITO thin film to form an ITO layer 25 , and the ITO layer 25 can be used as a pixel electrode and a source/drain of a thin film transistor. The ITO layer 25 is fabricated using a third photomask. Step S11 completes the fabrication of the TFT, and the specific structure is shown in Figures 4a and 4b, wherein Figure 4b is a top view of Figure 4a. In step S11, the design of the storage capacitor is also considered, and a MII (Metal/Insulator/ITO) structure is adopted. The three-layer structure of the first metal layer 22 , the gate insulating layer 23 and the ITO layer 25 formed on the right part of FIG. 4 a constitutes a storage capacitor.

Step S12: On the ITO layer 25, a protective layer 26 and a second metal layer 27 are sequentially provided, wherein the second metal layer 27 is provided on the protective layer 26 using the same mask as the protective layer 26, and the second metal layer 27 passes through A contact hole 28 connects the second metal layer 27 with the ITO layer 25 .

In step S12, the PECVD deposition method is used to apply the fourth mask to quickly deposit the protective layer (GI-SiNx) 26, and then expose, develop, and etch to remove the photoresist to form a contact hole (contact hole) 28. The specific structure is shown in FIG. 5 . A jumper conduction channel is formed through the contact hole 28, so that the data line formed by the second metal layer (Metal 2) is connected to the ITO drain of the TFT. as a channel protection layer.

Further, the second metal layer 27 is deposited on the protective layer 26; the second metal layer 27 is photoetched using a photoresist with opposite characteristics to the photolithographic protective layer 26 and the same mask as the protective layer 26, so that Layer 26 forms a hollowed-out portion leaving second metal layer 27 .

Specifically, referring to FIG. 6, a second metal layer (Metal 2) 27 is deposited on the protective layer 26 by using a physical vapor deposition method (PVD Sputter), and then exposed, developed, etched, and photoresist removed to form a patterned first metal layer. Two metal layers 27 . The exposure of this process uses the same photomask as that used for the exposure of the protective layer, but the photoresist with the opposite characteristics is used, so that the photoresist of the illuminated part remains. After exposure, development, etching, and photoresist removal, the second metal layer 27 is left on the part of the protective layer 26 where the hollow pattern is formed, and the array substrate 20 is obtained. In this way, the data line formed by the second metal layer 27 can be connected to the drain formed by the ITO layer 25 of the TFT. Therefore, the production of the second metal layer 27 here is the fourth photomask, which is the same as the photomask used in the production of the protective layer 26, saving one photomask and reducing the process cost, but the patterning process of the second metal layer 27 A photoresist with the opposite characteristics to that of the protective layer 26 is selected, and the number of exposures is not reduced. For example, a positive photoresist is used when the protective layer 26 is formed by exposure, and a negative photoresist is used when the second metal layer 27 is formed by exposure.

In the embodiment of the present invention, the fabrication of the second metal layer can also be formed by exposing the same positive photoresist as that of the protective layer, and the exposure process during fabrication of the second metal layer is reduced. Specifically, a protective layer is deposited on the ITO layer, wherein the first photoresist is used to perform photolithography on the protective layer to form a contact hole; a second metal layer is arranged on the first photoresist, and the second metal layer is processed by using the second photoresist Photolithography, wherein the second photoresist has the same characteristics as the first photoresist. More specifically, depositing a second metal layer on the first photoresist; coating the second photoresist on the second metal layer, and etching and removing the second photoresist except the contact hole; etching the exposed part of the first photoresist. the second metal layer; and remove the remaining part of the first photoresist and the second photoresist.

The fabrication method of the first metal layer 22 , the gate insulating layer 23 , the semiconductor layer 24 and the ITO layer 25 of the array substrate of the second embodiment is the same as that of the array substrate of the first embodiment, and will not be repeated here. That is, the first photomask for making the first metal layer, the second photomask for making the semiconductor layer 24, and the third photomask for making the ITO layer 25 will not be described in detail here. From the protective layer 26 Production starts to explain. Referring to FIG. 7, the formation of the second metal layer includes:

Step 1: Deposit a protective layer 26 on the ITO layer 25 , wherein the first photoresist 29 is used to perform photolithography on the protective layer 26 to form a contact hole 28 .

Referring to FIG. 8 , the protective layer (GI-SiNx) 26 is rapidly deposited by PECVD deposition method, the first photoresist 29 is coated, and then the fourth photomask is used for exposure, development, and etching to form a contact hole 28 . After forming the pattern of the protective layer 26 by etching, the first photoresist 29 is not removed, that is, the first photoresist 29 except the contact hole 28 remains. The protection layer 26 is a channel protection layer, and a cross-over conduction channel is formed through the contact hole 28, so as to facilitate the connection between the data line and the drain of the TFT.

Step 2: depositing a second metal layer 27 on the first photoresist 29 .

Referring to FIG. 9 , on the basis of the unremoved first photoresist 29 , a second metal layer 27 is deposited using a physical vapor deposition method (PVDSputter).

Step 3: Coating a second photoresist 291 on the second metal layer 27 .

Referring to FIG. 10 , a second photoresist 291 is coated on the second metal layer 27 , wherein the second photoresist 291 has the same characteristics as the first photoresist 29 , and both are positive photoresists.

Step 4: Etching and removing the second photoresist except the part of the contact hole 28 .

Referring to FIG. 11 , the second photoresist 291 is removed, and only the second photoresist 291 in the contact hole 28 remains.

Step 5: Etching the exposed portion of the second metal layer 27 .

Referring to FIG. 12 , the second metal layer 27 not covered by the second photoresist 291 is etched away.

Step 6: removing the remaining part of the first photoresist 29 and the second photoresist 291 .

Finally, all the first photoresist 29 and the second photoresist 291 are removed to obtain the array substrate 20 as shown in FIG. 2a. The embodiment of the present invention uses the photomask identical with making protective layer 26 when making second metal layer 27, and the making of contact hole 28 of protective layer 26 and the making of second metal layer 27 need only one exposure, therefore not only reduces One photomask also saves one exposure process. Process time is saved while reducing mask cost.

In summary, the present invention deposits the first metal layer on the glass substrate; sequentially deposits the gate insulating layer and the semiconductor layer on the gate insulating layer; arranges the ITO layer on the semiconductor layer; Two metal layers; wherein, a second metal layer is set on the protective layer using the same mask as the protective layer, and the second metal layer is connected to the ITO layer through a contact hole, which can reduce a masking process , saving process time while reducing costs.

The above is only an embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the description of the present invention and the contents of the accompanying drawings, or directly or indirectly used in other related technologies fields, all of which are equally included in the scope of patent protection of the present invention.

Claims (4)

1. a kind of manufacturing method of array substrate, which is characterized in that the described method includes:

One glass substrate is provided, and deposits the first metal layer on the glass substrate；

Gate insulation layer and semiconductor layer are sequentially depositing on the first metal layer；ITO layer is set on the semiconductor layer；

Protective layer and second metal layer are set gradually in the ITO layer, wherein are used and formed contact hole on the protective layer The second metal layer is arranged in mask plate on the protective layer, and the second metal layer passes through the contact hole for described second Metal layer is connect with the ITO layer；

Wherein, described that second metal is arranged on the protective layer using the mask plate for forming contact hole on the protective layer Layer the step of include:

The second metal layer is deposited on the protective layer；

Using the mask plate with the contact hole on the photoresist of protective layer opposite characteristic described in photoetching and the formation protective layer Photoetching is carried out to the second metal layer, so that leaving second metal in the part that the protective layer forms the contact hole Layer.

2. the manufacturing method of array substrate according to claim 1, which is characterized in that the first metal layer is common electrical The grid of pole and thin film transistor (TFT), source/drain of the ITO layer as pixel electrode and the thin film transistor (TFT).

3. the manufacturing method of array substrate according to claim 1, which is characterized in that the gate insulation layer includes the first grid Insulating layer and the second gate insulation layer, packet the step of being sequentially depositing gate insulation layer and semiconductor layer on the first metal layer It includes:

First gate insulation layer described in using plasma chemical vapor deposition method fast deposition；

Using plasma chemical vapor deposition method deposits at a slow speed second gate insulation layer, wherein the first grid insulating layer Thickness be greater than second gate insulation layer thickness；

Semiconductor layer described in using plasma chemical vapor deposition.

4. the manufacturing method of array substrate according to claim 1, which is characterized in that heavy using physical gas-phase deposite method The product the first metal layer and the second metal layer deposit the ITO layer using sputtering method.