CN105955905B - A kind of interface circuit and communication protocol based on serial bus structure - Google Patents

Abstract

The invention discloses a bus interface circuit based on a serial bus structure and its bus communication protocol. The bus interface circuit realizes strong pull-up, Weak pull-up and strong pull-down drive output, combined with the readback function of the logic level of the bus, support the bus communication protocol in which bus nodes compete for bus control in the way of non-destructive arbitration and automatic backoff. The nodes judge the bus idleness by monitoring the bus state, and through the "presetting" of the bus level and the "assignment" based on the node address bits, the nodes participating in the competition can have the minimum address value during the competition process of the bus control right. The information sent by the node to the bus will not be destroyed, until the application data is sent, the bus control right will be re-competed by the node, so as to realize the multi-master communication of the node based on the serial bus structure, and ensure the real-time and reliability of the bus communication sex.

Description

An Interface Circuit and Communication Protocol Based on Serial Bus Structure

technical field

The invention relates to a bus interface circuit based on a serial bus structure and its non-destructive bus communication protocol, belonging to the technical field of information network communication.

Background technique

The development of electronic information, communication and computer technology has brought great changes to the whole society; at the same time, due to the expansion and development of industrial technology, the application of electronic information, communication and computer technology in factories, buildings and agricultural fields is becoming more and more extensive. and in-depth. Among them, the digital communication between intelligent instruments, controllers, executive agencies and other equipment and the communication with the upper control system are the primary problems, and the field bus is the core technology to solve this problem.

Fieldbus provides basic information transmission and networking communication support for various instruments and equipment, and is an important guarantee for the coordinated and efficient work of functional components of each node in the Internet of Things. At present, there are already some very successful fieldbus technologies abroad, such as EIB, LonWorks, etc., which are widely used in household and large-scale building electrical monitoring systems, but due to the small driving ability of nodes to the bus, if repeaters are not used, The number of nodes that can be mounted on a single bus generally does not exceed 100. If a large network needs to be formed, multiple buses are required. For 485 and CAN buses commonly used in industry, the number of single-bus nodes is generally slightly more than 100. When there are too many monitoring points, it is still necessary to use multiple buses to form a network.

Using the "push-pull" output structure as the bus drive circuit can effectively improve the drive capability of the bus nodes to the bus and increase the number of nodes that the bus can mount. The problem brought about by this method is that if there are multiple bus nodes transmitting data on one bus at the same time, there is a high possibility of a low-impedance path between high and low levels, which will lead to logic errors or even short circuits on the bus. burn. A common method to solve this problem is to use a tri-state gate with a "push-pull" output structure to access the bus at the bus node, and control the bus node to transmit data through the polling method of the microcontroller. This method can ensure Only one tri-state gate is in the working state at each moment, while the other tri-state gates are in high-impedance state, but when the number of bus nodes is large, the communication process using the polling method becomes very slow, which does not conform to the field bus Real-time requirements, and this method requires an additional control bus to control the working state and high-impedance state of the tri-state gate.

Contents of the invention

The present invention provides a bus interface circuit based on a serial bus structure and its bus communication protocol in order to avoid the shortcomings of the above-mentioned prior art, in order to realize node multi-master communication based on a serial bus structure, so that the bus The nodes obtain the control right of the bus by means of competition, which can effectively improve the load capacity of the serial bus and ensure the real-time and reliability of the bus communication.

The present invention adopts following technical scheme for solving technical problems:

The present invention is a bus interface circuit based on a serial bus structure. The serial bus structure is provided with n nodes connected in parallel on the bus, which is denoted as G={G ₁ ,G ₂ ,...,G _i ,. .., G _n }; G _i represents the i-th node; the i-th node G _i includes: the i-th microcontroller and the i-th bus interface circuit; the i-th microcontroller and the i-th The bus interface circuits are connected through the i-th group of signal lines; the i-th bus interface circuit is connected with the bus through the i-th data line Data _i ; 1≤i≤n; its characteristics are:

The i-th group of signal lines includes: the i-th transmission signal line TX _i , the i-th reception signal line RX _i , the i-th transmission control signal line HI _i and the i-th competition control signal line CI _i ;

The i-th bus interface circuit is connected with the i-th positive power supply, the i-th negative power supply and the ground wire;

The i-th bus interface circuit includes: the i-th pull-up circuit, the i-th pull-down circuit, the i-th readback circuit, the i-th data transmission control circuit and the i-th competition control circuit;

The i-th pull-down circuit is connected to the i-th positive power supply, and connected to the i-th data line Data _i through the i-th number one diode D _i,1 ;

The i-th pull-down circuit is connected to the i-th data transmission control circuit;

The i-th readback circuit is connected to the i-th data line Data _i through the i-th No. 8 resistor R _i,8 ;

The i-th readback circuit is connected to the i-th microcontroller through the i-th receiving signal line RX _i ;

The i-th data transmission control circuit is connected to the ground wire, and connected to the i-th readback circuit and the i-th number eight resistor R _i, 3 through the i-th number three diode D _i,3 between ₈ ;

The i-th data transmission control circuit is connected to the i-th microcontroller through the i-th transmission signal line TX _i and the i-th transmission control signal line HI _i respectively;

The i-th pull-up circuit is connected to the i-th negative power supply, and connected to the i-th data line Data _i through the i-th No. 2 diode D _i,2 ;

The i-th pull-up circuit is externally connected with the i-th No. 5 resistor R _i,5 ; one end of the i-th No. 5 resistor R _i,5 is connected to the i-th No. 2 diode D _{i, 2} , the other end is connected to the i-th negative power supply;

The i-th pull-up circuit is connected to the i-th competition control circuit;

The i-th competition control circuit is connected between the i-th readback circuit and the i-th No. 8 resistor R _i,8 through the i-th No. 4 diode D _i,4 ;

The i-th contention control circuit is connected to the i-th microcontroller through the i-th contention control signal line CI _i , the i-th transmission signal line TX _i and the i-th transmission control signal line HI _i .

The characteristics of the bus interface circuit based on the serial bus structure in the present invention are also that: the i-th competition control circuit includes: the i-th NAND gate U _i , the i-th No. 12 resistor R _i,12 and The i-th No. 5 PNP transistor Q _i,5 ;

The emitter of the i-th No. 5 PNP transistor Q _{i, 5} is connected to the i-th positive power supply, and the collector is respectively connected to the anode of the i-th No. 4 diode D _{i, 4} and the i-th pull-up circuit , the base is connected to one end of the i-th No. 12 resistor R _{i , 12} ; the other end of the i-th No. 12 resistor R i, 12 is connected to the output end of the i-th NAND gate U _i ; The input terminals of the i-th NAND gate U _i are respectively connected to the i-th contention control signal line CI _i , the i-th transmission signal line TX _i and the i-th transmission control signal line HI _i .

A kind of bus communication protocol based on the bus interface circuit of the present invention is characterized in that it is applied in a serial bus structure composed of n nodes connected in parallel on the bus, and the i-th node includes: the i-th microcontroller and the i-th a bus interface circuit; the i-th microcontroller and the i-th bus interface circuit are connected through the i-th group of signal lines; the i-th group of signal lines includes: the i-th sending signal line TX _i , the i-th signal line The first receiving signal line RX _i , the i-th sending control signal line HI _i and the i-th competition control signal line CI _i ; the i-th bus interface circuit is connected to the bus through the i-th data line Data _i ; 1 ≤i≤n;

Described bus communication protocol is to carry out as follows:

Step 1, define variables j and k; Assume that the i-th node is used as the sending node and send a frame of binary data data to the bus, define the number of bits of the frame of binary data as M=m+z+l ; m≥2 and is an even number, m represents the number of data bits in the one frame of binary data; z=1 represents that the number of start bits in the one frame of binary data is 1; l=1 represents the one The number of stop bits in the frame binary data is 1;

Then set the high value of the m address bits in the address ID _i of the i-th node Bit packed as Frame 1 binary data, low Bit packed as frame 2 binary data;

The data bits in the binary data of the first frame and the binary data of the second frame are formed by inserting a binary code "1" into the high bit before each address bit; that is,

Data bits of the first frame of binary data: 1, ID _m-1 , 1, ID _m-2 , 1, ..., 1, ID _m/2 ;

The data bits of the binary data of the second frame: 1, ID _m/2-1 , 1, ID _m/2-2 , 1, ..., 1, ID ₀ ;

Step 2. The microcontroller in the i-th node sets the i-th transmission control signal line HI _i to a low level, indicating that the i-th bus interface circuit is in a "weak pull-up"output;

Step 3, initialize j=1;

Step 4, the microcontroller in the i-th node collects the logic value F _j of the bus through the i-th receiving signal line RX _i under the j-th monitoring period T _j and makes a judgment,

When F _j =1, assign j+1 to j, and judge whether j>M is true, if true, it means that the bus is in the "idle" state, and execute step 5, otherwise repeat step 4;

When F _j =0, it means that the bus is in the "occupied"state; and return to step 3 for execution;

Step 5, initializing k=1;

Step 6, initializing j=0; at the start moment of the j-th sending cycle T _j , the microcontroller in the i-th node sets the i-th sending control signal line HI _i to a high level, After setting the i-th contention control signal line CI _i and the i-th transmission signal line TX _i to a low level, wait for the end moment of the j-th transmission cycle T _j ; thereby completing the k-th frame of binary data The transmission of the start bit, and let j=1;

Step 7. At the starting moment of the j-th sending cycle T _j , the microcontroller in the i-th node connects the i-th sending control signal line HI _i and the i-th competition control signal line CI _i respectively and the i-th transmission signal line TX _i is set to a high level, so that the i-th bus interface circuit is in a "strong pull-up"output; and at the middle moment of the j-th transmission cycle T _j , the i-th The competition control signal line CI _i is set to a low level, so that the i-th bus interface circuit is in the "weak pull-up" output, and the preset of the bus level state is completed;

Step 8. At the start moment of the j+1th transmission cycle T _j+1 , the microcontroller in the i-th node sends the mj-1th bit of the k-th frame of binary data to Data is sent to the bus through the i-th transmission signal line TX _i ; if the i-th transmission signal line TX _i is at a high level, it means that the i-th bus interface circuit maintains a "weak pull-up""output; if the i-th transmission signal line TX _i is low level, it means that the i-th bus interface circuit is in the "strong pull-down"output;

And at the middle moment of the j+1th sending cycle T _j+1 , the microcontroller in the i-th node reads the logic value F _j+1 of the bus through the i-th receiving signal line RX _i and judge,

When the logic value F _j+1 of the bus is the same as the data of the mj-1th bit in the data bits of the kth frame binary data, wait for the end of the j+1th sending cycle T _j+1 , and then set j+ 2 Assign a value to j, and judge whether j>m-1 is true; if true, at the beginning of the jth sending cycle T _j , the micro-controller in the i-th node sends the i-th After sending the control signal line HI _i , the i-th contention control signal line CI _i and the i-th sending signal line TX _i at high level, wait for the end moment of the j-th sending cycle T _j ; thus completing the k-th Send the stop bit in the frame binary data, and then execute step 9; otherwise, return to step 7 for execution;

When the logic value F _j+1 of the bus is not the same as the data of the mj-1th bit in the data bits of the kth frame binary data, it means that there are other nodes higher than the i-th node priority, the said The microcontroller in the i-th node sets the i-th sending control signal line HI _i to a low level, indicating that the i-th bus interface circuit is in a "weak pull-up"output; and returns to step 3 for execution;

Step 9. Assign k+1 to k, and judge whether k>2 is true, if true, it means that the microcontroller in the i-th node obtains the control right to send data to the bus and passes the i-th node The data line Data _i completes its own data transmission; and returns to step 2 for execution; otherwise, returns to step 6 for execution.

Compared with the prior art, the beneficial effects of the present invention are reflected in:

1. The present invention designs a bus interface circuit based on a serial bus structure, and realizes a strong pull-up and a weak pull-up of the bus level by using the combined setting of the sending data line, the sending control signal line and the competition control signal line and strong pull-down driver output. The effect is: the strong pull-up and pull-down drive of the bus level constitutes the "push-pull" output function of the bus, which significantly improves the output drive capability of the interface circuit to the bus, and increases the number of devices that can be mounted in parallel on the bus at the same time. the number of nodes. At the same time, combined with the weak pull-down of the bus level and the readback function of the bus logic level, the proposed bus interface circuit provides hardware support for the non-destructive bus communication protocol in which nodes compete for bus control.

2. The bus interface circuit of the present invention is mainly composed of a pull-up circuit, a pull-down circuit, a weak pull-down resistor, a transmission control circuit, a competition control circuit and a bus level readback circuit, and is connected to the serial bus through a data line and a ground line. When there is data that needs to be sent to the bus, the node monitors the bus status by reading back the logic level of the bus. If the number of consecutive high-level logic bits exceeds the number of bits in a frame of data, the bus is judged to be idle, otherwise the bus is judged to be idle. Occupied. When the bus is free, the node sends out its own address ID through the interface circuit in the order of high bits first and then low bits. But before sending each bit address, use the strong pull-up capability of the interface circuit to send a bit of logic 1 to the bus, and then control the interface circuit to enter the weak pull-up state, thereby completing the "presetting" of the bus level. In the next bit time, judge the logical value of the address bit to be sent. If it is 1, the weak pull-up output of the interface will be maintained; if it is 0, the interface circuit will be pulled down strongly, and a logic 0 will be sent to the bus. Complete the "assignment" of the bus level. The effect is: in the "preset" stage, the bus level is quickly pulled up to logic 1, and then according to the address bits of the competing nodes, the bus level is quickly "assigned" through high-level hold or strong pull-down drive. ", thereby realizing the "wire-AND" function of the strong drive "push-pull" output.

3. The present invention reads back the logic level of the bus generated by the "wire-AND" result output by the interface circuit, and the node reads back through the readback circuit of its bus interface, and judges whether the readback result is consistent with the address bits sent by the current node. If they are consistent Then continue to compete for the next bit, otherwise, the node temporarily withdraws from the bus competition and turns to monitor the bus state. The effect is: as long as the address ID of each node on the bus is unique, when all the address bits of a certain node are sent out, the node has obtained the control right of the bus and can continue to send application data to the bus. During the whole process of competition and arbitration for the nodes participating in the bus control right, the information sent by the node with the smallest address ID value to the bus will not be damaged in any way, and the bus control right will not be re-competed until its application data is sent. And arbitration, thus realizing the node multi-master communication based on the serial bus structure, effectively improving the real-time and reliability of the serial bus communication.

Description of drawings

Fig. 1 is the structural representation of serial bus among the present invention;

Fig. 2 is the schematic diagram of bus interface circuit in the present invention;

Fig. 3 is a schematic diagram of bus communication interface data channel coding pulse in the present invention;

Fig. 4 is a composition diagram of node sending data and a frame of binary data in the present invention;

Fig. 5 is a communication protocol flow chart in the present invention;

FIG. 6 is a diagram of an implementation example of non-destructive bus arbitration in the present invention.

Detailed ways

In this embodiment, the bus interface circuit utilizes the logical combination of the sending data line, the sending control line and the contention control line to realize the strong pull-up, weak pull-up and strong pull-down drive output of the bus level, combined with the control of the bus logic level The readback function supports the bus communication protocol in which the bus nodes compete for the control right of the bus in the way of non-destructive arbitration and automatic backoff. The nodes judge the bus idleness by monitoring the bus state, and through the "presetting" of the bus level and the "assignment" based on the node address bits, the nodes participating in the competition can have the minimum address value during the competition process of the bus control right. The information sent by the node to the bus will not be destroyed, until the application data is sent, the bus control right will be re-competed by the node, thus realizing the node multi-master communication based on the serial bus structure and ensuring the real-time performance of the bus communication and reliability.

Specifically, a bus interface circuit based on a serial bus structure, the structure of which is shown in FIG. 1 . The serial bus structure is that n nodes are arranged in parallel on the bus, recorded as G={G ₁ ,G ₂ ,...,G _i ,...,G _n }; G _i represents the i-th node; The i node G _i includes: the i-th microcontroller and the i-th bus interface circuit; the i-th microcontroller and the i-th bus interface circuit are connected through the i-th group of signal lines; the i-th bus interface circuit The i-th data line Data _i is connected to the bus, and the i-th microcontroller uses the i-th group of signal lines to control the i-th bus interface circuit, thereby sending data to the bus or receiving data from the bus; 1≤i≤n;

The i-th group of signal lines includes: the i-th transmission signal line TX _i , the i-th reception signal line RX _i , the i-th transmission control signal line HI _i and the i-th competition control signal line CI _i ;

The i-th bus interface circuit is connected with the i-th positive power supply +U, the i-th negative power supply-U and the ground wire;

See Figure 2; the i-th bus interface circuit includes: the i-th pull-up circuit, the i-th pull-down circuit, the i-th readback circuit, the i-th data transmission control circuit and the i-th competition control circuit;

The i-th pull-down circuit is connected to the i-th positive power supply, and connected to the i-th data line Data _i through the i-th No. 1 diode D _i,1 ;

The i-th pull-down circuit is connected to the i-th data sending control circuit;

The i-th readback circuit is connected to the i-th data line Data _i through the i-th No. 8 resistor R _i,8 ;

The i-th readback circuit is connected to the i-th microcontroller through the i-th receiving signal line RX _i ;

The i-th data transmission control circuit is connected to the ground wire, and connected between the i-th readback circuit and the i-th No. 8 resistor R _i,8 through the i-th No. 3 diode D _i,3 ;

The i-th data transmission control circuit is connected to the i-th microcontroller through the i-th transmission signal line TX _i and the i-th transmission control signal line HI _i respectively;

The i-th pull-up circuit is connected to the i-th negative power supply, and connected to the i-th data line Data _i through the i-th second diode D _i,2 ; the i-th pull-down circuit and the i-th pull-up circuit together constitute The i-th "push-pull" output circuit; when the i-th No. 1 NPN transistor Q _i,1 in the i-th pull-down circuit is turned on and the i-th No. 2 NPN transistor Q in the i-th pull-up circuit When i _{, 2} is cut off, the i-th bus interface circuit is set as a "strong pull-down"output; When the i second NPN transistor Q _i,2 is turned on, the output of the ith bus interface circuit is set as a "strong pull-up" output.

The i-th No. 1 diode D _i,1 and the i-th No. 2 diode D _i,2 work together. The first function is to avoid the reverse connection of the i-th positive power supply +U and the i-th negative power supply-U by mistake. Damage the i-th bus interface circuit and the bus; the second is to limit the i-th pull-down circuit and the i-th pull-up circuit respectively, avoiding damage due to unstable output voltage of the positive power supply +U or the i-th negative power supply-U The i-th bus interface circuit.

The i-th pull-up circuit is externally connected to the i-th No. 5 resistor R _i,5 ; one end of the i-th No. 5 resistor R _i,5 is connected to the negative pole of the i-th No. 2 diode D _i,2 , and the other end Connect to the i-th negative power supply; the resistance value of the i-th No. 5 resistor R _i,5 is very large; when the i-th No. 2 NPN transistor Q _i,2 in the i-th pull-up circuit and the i-th pull-down circuit The i-th No. 1 NPN transistor Q _{i, 1} is all cut off, and the i-th negative power supply -U can set the output of the i-th bus interface circuit to "weak pull-up" through the i-th No. 5 resistor R _{i, 5} Output; at this time, if the xth fifth NPN transistor Qx _{, 5} in the xth pull-down circuit in the xth (1≤x≤n and _x ≠i) node Gx on the bus is in the conduction state, the The i fifth resistor R _i,5 can limit the current in the path between the xth positive power supply +U and the ith negative power supply -U to the microampere level, avoiding the xth positive power supply +U and the ith A low-impedance path is formed between a negative power supply -U.

Definition: The "strong pull-up" state and the "weak pull-up" state are collectively referred to as the "pull-up" state;

When the bus level state is set to "strong pull-down" state, the sixth NPN transistor Q _{i, 6} in the i-th readback circuit is turned on, and the i-th receiving signal line RX _i is set to low level; When the level state of the bus is set to "pull-up" state, the sixth NPN transistor Q _{i, 6} in the i-th readback circuit is turned off, and the i-th receiving signal line RX _i is set to high level; If the i-th microcontroller detects that the i-th receiving signal line RX _i is low, it reads that the bus is in a "strong pull-down"state; if the i-th microcontroller detects that the i-th receiving signal line RX If _i is high level, it is read that the bus is in the "pull-up" state.

The i-th pull-up circuit is connected to the i-th competition control circuit;

The i-th competition control circuit is connected between the i-th readback circuit and the i-th No. 8 resistor R _{i, 8} through the i-th No. 4 diode D _{i, 4} ; the i-th No. 3 diode D _{i, 3} and The i-th No. 4 diode D _i,4 works together, and its function is the same as that of the i-th No. 1 diode D _i,1 and the i-th No. 2 diode D _i,2 .

The i-th contention control circuit is connected to the i-th microcontroller through the i-th contention control signal line CI _i , the i-th transmission signal line TX _i and the i-th transmission control signal line HI _i .

Specifically, the i-th competition control circuit includes: the i-th NAND gate U _i , the i-th No. 12 resistor R _i,12 and the i-th No. 5 PNP transistor Q _i,5 ;

The emitter of the i-th No. 5 PNP transistor Q _i,5 is connected to the i-th positive power supply, the collector is respectively connected to the anode of the i-th No. 4 diode D _i,4 and the i-th pull-up circuit, and the base is connected to the i-th pull-up circuit. One end of the i-th No. 12 resistor R _{i, 12} is connected; the other end of the i-th No. 12 resistor R _{i, 12} is connected with the output end of the i-th NAND gate U _i ; the i-th NAND gate U The input end of _i is connected to the i-th contention control signal line CI _i , the i-th transmission signal line TX _i and the i-th transmission control signal line HI _i respectively.

The i-th microcontroller uses the i-th group of signal lines to control the i-th bus interface circuit. Based on the principle of the i-th bus interface circuit, the control method of the i-th microcontroller on the i-th bus interface circuit can be obtained, as shown in Table 1 shows.

Table 1 Control mode of the i-th microcontroller to the i-th bus interface circuit

It can be seen from Table 1 that the i-th transmission control signal line HI _i is the signal line that controls the transmission of data; when the i-th transmission control signal line HI _i is at low level, the i-th bus interface circuit always maintains a "weak pull-up" The state does not change with the change of the signals in the i-th transmission signal line TX _i and the i-th contention control signal line CI _i . When the i-th transmission control signal line HI _i is at high level, the signals in the i-th transmission signal line TX _i and the i-th contention control signal line CI _i jointly determine the output state of the i-th bus interface circuit.

When the i-th transmission control signal line HI _i is at a high level, the signal in the i-th transmission signal line TX _i determines that the i-th bus interface circuit is in a "pull-up" output or a "strong pull-down" output.

When the i-th transmission control signal line HI _i is high level and the i-th transmission signal line TX _i is high level, the signal in the i-th contention control signal line CI _i determines that the i-th bus interface circuit is in the "weak" state. pull-up" output or "strong pull-up" output.

From the principle of the i-th bus interface circuit, it can be known that when the a (a=1,2,...,n) bus interface circuit on the bus is in the "weak pull-up" state, the bus is also in the "weak pull-up" state. "state; when b bus interface circuits are "weak pull-up" output on the bus, and c bus interface circuits are "strong pull-down" output, b+c=n, then the bus is in a "strong pull-down" state.

In this embodiment, a bus communication protocol based on a bus interface circuit is applied to a serial bus structure composed of n nodes connected in parallel on the bus, and the i-th node includes: the i-th microcontroller and The i-th bus interface circuit; the i-th microcontroller and the i-th bus interface circuit are connected through the i-th group of signal lines; the i-th group of signal lines includes: the i-th sending signal line TX _i , the i-th receiving signal line The signal line RX _i , the i-th transmission control signal line HI _i and the i-th competition control signal line CI _i ; the i-th bus interface circuit is connected to the bus through the i-th data line Data _i ; 1≤i≤n;

As shown in Figure 3, the bus communication protocol stipulates that the channel coding method of the bus adopts bipolar pulse non-return-to-zero negative logic coding, and the bus has two logic values, namely logic "1", corresponding to the bus "pull-up" state and high power Level; logic "0", corresponding to the bus "strong pull-down" state and low level;

Define the node that wants to obtain the control right to send data to the bus as the node that participates in the competition; the node that does not want to obtain the control right to send data to the bus is the node that does not participate in the competition.

As shown in Figure 5, the bus communication protocol is carried out in the following steps:

Step 1, define variables j and k; assume that the i-th node is used as the sending node and send a frame of binary data to the bus, and define the number of bits of a frame of binary data as M=m+z+l; m≥2 and an even number , m represents the number of data bits in a frame of binary data; z=1 represents that the number of start bits in a frame of binary data is 1, and the start bit is "0"; l=1 represents a stop in a frame of binary data The number of bits is 1, and the stop bit is "1"; as shown in Figure 4, the data sent by the i-th node to the bus is composed of several frames of binary data, and the number of frames of binary data is variable, but at least two frames; There is a frame interval time between each frame of binary data, and the frame interval time is less than the sending period of each binary data bit. The binary data of the first frame of data is the binary data of the first frame, and the binary data of the second frame is the binary data of the second frame. ;

Define the address ID _i of the i-th node in the bus as binary data, ID _i has a total of m address bits; and the address ID _z of the z-th node, 1≤z≤n, z≠i, must satisfy ID _i ≠ ID _z ; at this time, if ID _i < ID _z , the i-th node has a higher priority than the z-th node; in a competition, there is only one node that obtains the control right to send data to the bus, and the node’s The priority must be higher than all other nodes participating in the competition.

Then set the high value of the m address bits in the address IDi of the i-th node Bit packed as Frame 1 binary data, low Bit packed as frame 2 binary data;

The data bits in the binary data of the first frame and the binary data of the second frame are formed by inserting a binary code "1" into the high bit before each address bit; that is,

Data bits of the first frame of binary data: 1, ID _m-1 , 1, ID _m-2 , 1,..., 1, ID _m/2 ;

Data bits of the second frame binary data: 1, ID _m/2-1 , 1, ID _m/2-2 , 1,..., 1, ID ₀ ;

The i-th node sends data bits through the i-th transmission signal line TX _i , and when the transmission data bit is defined as "1", the i-th transmission signal line TX _i is at high level; when the transmission data bit is "0", the i-th transmission signal line i transmission signal line TX _i is low level;

If only the i-th node and the z-th node are nodes participating in the competition, when competing for control of sending data to the bus, the i-th node sends the first frame of binary data and the second frame of the i-th node to the bus in turn For binary data, the zth node sends the first frame of binary data and the second frame of binary data of the zth node to the bus in turn; if ID _i < ID _z , the i-th node has a higher priority than the z-th node, Therefore, by comparing the address ID _i of the i-th node with the corresponding address bits in the address ID _z of the z-th node bit by bit, the i-th node with the highest priority wins, that is, the i-th node gets the right to send data to the bus. Control.

Step 2. The microcontroller in the i-th node sets the i-th transmission control signal line HI _i to low level, indicating that the i-th bus interface circuit is in the "weak pull-up" output, that is, No. 1 in Table 1 Way;

Step 3, initialize j=1;

Step 4. The microcontroller in the i-th node collects the logical value F _j of the bus through the i-th receiving signal line RX _i in the j-th monitoring period T _j and makes a judgment. Since the node that does not send data to the bus The output is in the "weak pull-up" state, if all nodes on the bus do not send data to the bus, the logic value of the bus is "1" at this time; see Figure 4, and because the start bit of a frame of binary data is Logic "0", and the frame interval time is less than the sending cycle of a binary data bit, if in a binary data sending cycle of a frame, the logic value F _j of the i-th node acquisition bus is always "1", it means that in a frame In the sending cycle of binary data, no node is sending data to the bus, and it is defined that the bus is in the "idle" state at this time; otherwise, the bus is in the "occupied" state.

When F _j = 1, assign j+1 to j, and judge whether j>M is true, if true, that is, in a frame of binary data transmission cycle, the logical value F _j of the i-th node acquisition bus is always "1", it means that the bus is in the "idle" state, and execute step 5; otherwise, repeat step 4;

When F _j =0, it means that the bus is in the "occupied"state; and return to step 3 for execution;

Step 5, initializing k=1;

Step 6. Initialize j=0; at the start moment of the jth sending cycle T _j , the microcontroller in the i-th node sets the i-th sending control signal line HI _i to a high level, and sets the i-th After the competition control signal line CI _i and the i-th transmission signal line TX _i are set to low level, the i-th bus interface circuit is in the "strong pull-down" output at this time, and the i-th node is in the No. 3 mode in Table 1 , waiting for the end moment of the jth sending cycle T _j ; thereby completing the sending of the start bit "0" in the kth frame binary data, and making j=1;

Step 7. At the starting moment of the j-th sending cycle T _j , the microcontroller in the i-th node connects the i-th sending control signal line HI _i , the i-th competition control signal line CI _i and the i-th The transmission signal line TX _i is set to a high level, that is, the microcontroller in the i-th node sends the data of the mj-1th bit in the data bits of the k-th frame of binary data through the i-th transmission signal line TX _i to On the bus, so that the bus is in a "strong pull-up" state, at this time the i-th node is in the No. 4 mode in Table 1; and at the end of the j-th sending cycle T _j , the i-th competition control signal line CI _i is set to low level, so that the i-th bus interface circuit is in the "weak pull-up" state, and the bus level state "presetting" is completed. At this time, the i-th node is in the No. 2 mode in Table 1;

Step 7 is equivalent to first turning off the i-th No. 1 NPN transistor Q _i,1 and turning on the i-th No. 2 NPN transistor Q _i,2 in the i-th pull-up circuit, and turning on the i-th data line Data _i The level state is pulled from +U to -U by the i-th No. 2 NPN transistor Q _i,2 in the i-th pull-up circuit, and the triode is turned off, and the i-th is maintained by the i-th No. 5 resistor R _i,5 The level state of the data line Data _i . In step 7, the i-th bus interface circuit can also be directly changed from the "strong pull-down" state to the "weak pull-up" state, that is, the "strong pull-up" state is skipped, which is equivalent to turning the i-th data line Data The level state of _i is pulled from +U to -U through the i-th No. 5 resistor R _i,5 .

Step 8. At the start moment of the j+1th sending cycle T _j+1 , the microcontroller in the i-th node transmits the data of the mj-1th bit in the data bits of the k-th frame of binary data, that is, the address bit It is sent to the bus through the i-th transmission signal line TX _i ; if the i-th transmission signal line TX _i is high level, it means that the i-th bus interface circuit maintains the "weak pull-up" output, at this time the i-th node In the No. 2 node mode in Table 1; if the i-th transmission signal line TX _i is low level, it means that the i-th bus interface circuit is in the "strong pull-down" output, and at this time the i-th node is in the No. 3 node mode, and the i-th bus interface circuit also sets the bus to the "strong pull-down"state; at this time, if the z-th node on the bus is also a node participating in the competition, and the z-th transmission signal line of the z-th node TX _z is high level, that is, the zth bus interface circuit is in the "weak pull-up" state, the zth node is in the mode of No. 2 node in Table 1, and the ith positive power supply and the zth negative power supply form a access, but the current is limited to the microampere level, and no bus logic value error will occur;

And at the middle moment of the j+1th transmission cycle T _j+1 , the microcontroller in the i-th node reads the logic value F _j+1 of the bus through the i-th receiving signal line RX _i and makes a judgment,

When the logic value F _j+1 of the bus is the same as the data of the mj-1th bit in the data bits of the kth frame binary data, wait for the end of the j+1th sending cycle T _j+1 , and then set j+ 2 Assign a value to j, and judge whether j>m-1 is true; if it is true, it indicates that the data bits of the k-th frame binary data of the i-th node have all been sent, and at the beginning of the j-th sending cycle T _j , the microcontroller in the i-th node respectively sets the i-th transmission control signal line HI _i , the i-th contention control signal line CI _i and the i-th transmission signal line TX _i to high level, and waits for the j-th The end moment of the first transmission cycle T _j ; thus complete the transmission of the stop bit in the kth frame binary data, and then perform step 9; otherwise, it means that the i-th node cannot pass through the address ID _i address bit of the i-th node To judge whether you have a high priority, return to step 7 for execution;

When the logic value F _j+1 of the bus is not the same as the data of the mj-1th bit in the data bits of the k-th frame binary data, it means that there are other nodes with higher priority than the i-th node, and the i-th node The microcontroller in the i-th transmission control signal line HI _i is set to low level, indicating that the i-th bus interface circuit is in the "weak pull-up" output. At this time, the i-th node has withdrawn from this competition, and its It is hoped that the data sent to the bus will complete a non-destructive bus arbitration; and return to step 3 to execute, monitor the bus again, and prepare to participate in the next competition;

Step 9. Assign k+1 to k, and judge whether k>2 is true. If it is true, it means that the i-th node has the highest priority among all the nodes participating in the competition, and it means that the microcontroller in the i-th node Obtain the control right to send data to the bus and complete its own data sending through the i-th data line Data _i ; and return to step 2 for execution; otherwise, return to step 6 for execution.

To illustrate: in the bus contention embodiment shown in FIG. 6 , the number of data bits in one frame of binary data is m=8, and the number of bits in one frame of binary data is M=10. The first node whose address ID ₁ is 01001001 (49H) and the second node whose address ID ₂ is 01000011 (43H) detect that the bus is in the "idle" state at the same time, and send their respective first frame binary to the bus in turn. The data and the binary data of the second frame start a competition. During the process of sending the binary data of the first frame and the binary data of the second frame, the first node and the second node read back and compare each address bit sent. When sending the sixth bit of the data bit in the binary data of the second frame, that is, the third bit of the address ID, what node 1 sends is "1", that is, sending logic "1", and the first bus interface circuit is in the "weak upper Pull"state; while the second node sends "0", that is, sends logic "0", the first bus interface circuit is in the "strong pull-down"state; the bus is in the "strong pull-down" state, at this time the first node The logic value read from the bus by the second node and the second node is "0", so a bus access conflict occurs. Because the logic value "0" read by the first node from the bus is different from the logic value "1" sent by itself, it will terminate the data transmission to the bus, and the first bus interface circuit maintains the "weak pull-up" state, and turns to Monitor or receive data on the bus; and the second node will obtain the control right to send data to the bus, complete its own data transmission through the second data line Data _i , after the data transmission is completed, the second bus interface circuit is activated Put it in the "weak pull-up" state, and turn to monitor or receive data on the bus.

Claims (3)

1. A bus interface circuit based on a serial bus structure, said serial bus structure is provided with n nodes in parallel on the bus, denoted as G={G ₁ , G ₂ ,...,G _i ,. .., G _n }; G _i represents the i-th node; the i-th node G _i includes: the i-th microcontroller and the i-th bus interface circuit; the i-th microcontroller and the i-th The bus interface circuits are connected through the i-th group of signal lines; the i-th bus interface circuit is connected to the bus through the i-th data line Data _i ; 1≤i≤n; it is characterized in that: The i-th group of signal lines includes: the i-th transmission signal line TX _i , the i-th reception signal line RX _i , the i-th transmission control signal line HI _i and the i-th competition control signal line CI _i ; The i-th bus interface circuit is connected with the i-th positive power supply, the i-th negative power supply and the ground wire; The i-th bus interface circuit includes: the i-th pull-up circuit, the i-th pull-down circuit, the i-th readback circuit, the i-th data transmission control circuit and the i-th competition control circuit; The i-th pull-down circuit is connected to the i-th positive power supply, and connected to the i-th data line Data _i through the i-th number one diode D _i,1 ; The i-th pull-down circuit is connected to the i-th data transmission control circuit; The i-th readback circuit is connected to the i-th data line Data _i through the i-th No. 8 resistor R _i,8 ; The i-th readback circuit is connected to the i-th microcontroller through the i-th receiving signal line RX _i ; The i-th data transmission control circuit is connected to the ground wire, and connected to the i-th readback circuit and the i-th number eight resistor R _i, 3 through the i-th number three diode D _i,3 between ₈ ; The i-th data transmission control circuit is connected to the i-th microcontroller through the i-th transmission signal line TX _i and the i-th transmission control signal line HI _i respectively; The i-th pull-up circuit is connected to the i-th negative power supply, and connected to the i-th data line Data _i through the i-th No. 2 diode D _i,2 ; The i-th pull-up circuit is externally connected with the i-th No. 5 resistor R _i,5 ; one end of the i-th No. 5 resistor R _i,5 is connected to the i-th No. 2 diode D _{i, 2} , the other end is connected to the i-th negative power supply; The i-th pull-up circuit is connected to the i-th competition control circuit; The i-th competition control circuit is connected between the i-th readback circuit and the i-th No. 8 resistor R _i,8 through the i-th No. 4 diode D _i,4 ; The i-th contention control circuit is connected to the i-th microcontroller through the i-th contention control signal line CI _i , the i-th transmission signal line TX _i and the i-th transmission control signal line HI _i . 2. The bus interface circuit based on the serial bus structure according to claim 1, characterized in that: the i competition control circuit comprises: the i NAND gate U _i , the i twelfth resistor R _i,12 and the i-th fifth PNP transistor Q _i,5 ; The emitter of the i-th No. 5 PNP transistor Q _{i, 5} is connected to the i-th positive power supply, and the collector is respectively connected to the anode of the i-th No. 4 diode D _{i, 4} and the i-th pull-up circuit , the base is connected to one end of the i-th No. 12 resistor R _{i , 12} ; the other end of the i-th No. 12 resistor R i, 12 is connected to the output end of the i-th NAND gate U _i ; The input terminals of the i-th NAND gate U _i are respectively connected to the i-th contention control signal line CI _i , the i-th transmission signal line TX _i and the i-th transmission control signal line HI _i . 3. A bus communication method based on a bus interface circuit, characterized in that it is applied to a serial bus structure formed by n nodes connected in parallel on the bus, the i node comprising: the i microcontroller and the i i bus interface circuit; the i th microcontroller and the i th bus interface circuit are connected through the i th group of signal lines; the i th group of signal lines includes: the i th sending signal line TX _i , the i th signal line The i receiving signal line RX _i , the i th sending control signal line HI _i and the i th competition control signal line CI _i ; the i th bus interface circuit is connected to the bus through the i th data line Data _i ; 1≤i≤n; Described bus communication method is to carry out as follows: Step 1, define variables j and k; Assume that the i-th node is used as the sending node and send a frame of binary data data to the bus, define the number of bits of the frame of binary data as M=m+z+l ; m≥2 and is an even number, m represents the number of data bits in the one frame of binary data; z=1 represents that the number of start bits in the one frame of binary data is 1; l=1 represents the one The number of stop bits in the frame binary data is 1; Then set the high value of the m address bits in the address ID _i of the i-th node Bit packed as Frame 1 binary data, low Bit packed as frame 2 binary data; The data bits in the binary data of the first frame and the binary data of the second frame are formed by inserting a binary code "1" into the high bit before each address bit; that is, The data bits of the first frame of binary data: 1, ID _m-1 , 1, ID _m-2 , 1, ..., 1, ID _m/2 ; The data bits of the binary data of the second frame: 1, ID _m/2-1 , 1, ID _m/2-2 , 1, ..., 1, ID ₀ ; Step 2. The microcontroller in the i-th node sets the i-th transmission control signal line HI _i to a low level, indicating that the i-th bus interface circuit is in a "weak pull-up"output; Step 3, initialize j=1; Step 4, the microcontroller in the i-th node collects the logic value F _j of the bus through the i-th receiving signal line RX _i under the j-th monitoring period T _j and makes a judgment, When F _j =1, assign j+1 to j, and judge whether j>M is true, if true, it means that the bus is in the "idle" state, and execute step 5, otherwise repeat step 4; When F _j =0, it means that the bus is in the "occupied"state; and return to step 3 for execution; Step 5, initializing k=1; Step 6, initializing j=0; at the start moment of the j-th sending cycle T _j , the microcontroller in the i-th node sets the i-th sending control signal line HI _i to a high level, After setting the i-th competition control signal line CI _i and the i-th transmission signal line TX _i to low level, wait for the end moment of the j-th transmission cycle T _j ; thereby completing the start of the k-th frame of binary data bit transmission, and let j=1; Step 7. At the starting moment of the j-th sending cycle T _j , the microcontroller in the i-th node connects the i-th sending control signal line HI _i and the i-th competition control signal line CI _i respectively and the i-th transmission signal line TX _i is set to a high level, so that the i-th bus interface circuit is in a "strong pull-up"output; and at the middle moment of the j-th transmission cycle T _j , the i-th The competition control signal line CI _i is set to a low level, so that the i-th bus interface circuit is in the "weak pull-up" output, and the preset of the bus level state is completed; Step 8. At the start moment of the j+1th transmission cycle T _j+1 , the microcontroller in the i-th node sends the mj-1th bit of the k-th frame of binary data to Data is sent to the bus through the i-th transmission signal line TX _i ; if the i-th transmission signal line TX _i is at a high level, it means that the i-th bus interface circuit maintains a "weak pull-up""output; if the i-th transmission signal line TX _i is low level, it means that the i-th bus interface circuit is in the "strong pull-down"output; And at the middle moment of the j+1th sending cycle T _j+1 , the microcontroller in the i-th node reads the logic value F _j+1 of the bus through the i-th receiving signal line RX _i and judge, When the logic value F _j+1 of the bus is the same as the data of the mj-1th bit in the data bits of the kth frame binary data, wait for the end of the j+1th sending cycle T _j+1 , and then set j+ 2 Assign a value to j, and judge whether j>m-1 is true; if true, at the beginning of the jth sending cycle T _j , the micro-controller in the i-th node sends the i-th After sending the control signal line HI _i , the i-th contention control signal line CI _i and the i-th sending signal line TX _i at high level, wait for the end moment of the j-th sending cycle T _j ; thus completing the k-th Send the stop bit in the frame binary data, and then execute step 9; otherwise, return to step 7 for execution; When the logic value F _j+1 of the bus is not the same as the data of the mj-1th bit in the data bits of the kth frame binary data, it means that there are other nodes higher than the i-th node priority, the said The microcontroller in the i-th node sets the i-th sending control signal line HI _i to a low level, indicating that the i-th bus interface circuit is in a "weak pull-up"output; and returns to step 3 for execution; Step 9. Assign k+1 to k, and judge whether k>2 is true, if true, it means that the microcontroller in the i-th node obtains the control right to send data to the bus and passes the i-th node The data line Data _i completes its own data transmission; and returns to step 2 for execution; otherwise, returns to step 6 for execution.