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CN105955899B - Radar digital signal processing device based on all solid state semicondctor storage array - Google Patents

Radar digital signal processing device based on all solid state semicondctor storage array Download PDF

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Publication number
CN105955899B
CN105955899B CN201610256793.2A CN201610256793A CN105955899B CN 105955899 B CN105955899 B CN 105955899B CN 201610256793 A CN201610256793 A CN 201610256793A CN 105955899 B CN105955899 B CN 105955899B
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layer
controller
memory array
solid
command
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CN105955899A (en
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苏涛
徐杰
仲鸣
张辉
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Xidian University
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Xidian University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0024—Peripheral component interconnect [PCI]

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Storage Device Security (AREA)

Abstract

本发明公开了一种基于全固态半导体存储器阵列的雷达数字信号处理装置，包括：SoC芯片、AXI总线、PCIe控制器、全固态半导体存储器阵列控制器、SRIO控制器和主控计算机(PC)；PC获取控制指令和雷达回波；PCIe控制器接收控制指令并进行解析；SoC芯片接收并执行解析后的控制指令，然后给PC反馈工作状态；全固态半导体存储器阵列控制器获得编码后的雷达回波，并对编码后的雷达回波进行解码，得到雷达回波；全固态半导体存储器阵列控制器获取自身和所述阵列控制器各自工作状态，并使SoC芯片给PC反馈所述存储器和所述存储器阵列控制器各自工作状态；SRIO控制器获取控制指令和编码后的雷达回波，并使SoC芯片进行解析与执行，然后给PCIe控制器反馈当前SRIO控制器工作状态。

The invention discloses a radar digital signal processing device based on an all-solid-state semiconductor memory array, comprising: a SoC chip, an AXI bus, a PCIe controller, an all-solid-state semiconductor memory array controller, an SRIO controller and a main control computer (PC); The PC obtains control commands and radar echoes; the PCIe controller receives and parses the control commands; the SoC chip receives and executes the parsed control commands, and then feeds back the working status to the PC; the all-solid-state semiconductor memory array controller obtains the encoded radar echoes The all-solid-state semiconductor memory array controller obtains the respective working states of itself and the array controller, and makes the SoC chip feed back the memory and the said memory to the PC. The respective working states of the memory array controllers; the SRIO controller obtains the control instructions and the encoded radar echoes, makes the SoC chip parse and execute, and then feeds back the current working state of the SRIO controller to the PCIe controller.

Description

Radar digital signal processing device based on all solid state semicondctor storage array
Technical field
The invention belongs to all solid state memory technology fields, in particular to a kind of to be based on all solid state semicondctor storage array Radar digital signal processing device, the broadcasting, importing or export of digital signal suitable for all solid state memory.
Background technique
High-speed data recording and controllable play-back technology are one of the key technologies in lot of domestic and foreign field, for detecting, Investigation, monitoring, equipment Test, outfield debugging etc..In engineering, it usually needs record high speed raw digital signal data flow So that the later period carries out the work such as fault diagnosis, scene check and archives data；And practical engineering application environment often has big temperature Poor, more dust, macroseism such as swing at the mal-conditions.Therefore, hard real time, large capacity, high density, highly reliable digital collection broadcasting are set It is standby to become research and development focus.
Current commercial high-speed processing apparatus mainly has automatic magnetic-tape filing cabinet and hard disk array (Redundant Arrays of Independent Disks, RAID), such as current state-of-the-art European Nuclear Research Center computer center is large-scale hadron pair (LHC) is collided using the magnetic-tape filing cabinet storage for being fully automated processing, when magnetic-tape filing cabinet is stored in vault, robot Mechanical arm can be such that tape moves between memory layer and tape drive；Magnetic-tape filing cabinet storage has high capacity price ratio, And there are numerous advantages such as ultrahigh speed, large capacity and low price, it is the ideal chose of Fixed Base high-speed high capacity storage；Certainly it lacks Point also clearly, the framework of magnetic-tape filing cabinet storage is complicated, loosely organized, temperature applicable range is narrow, shock resistance is poor, intolerant to dust and It takes up a large area.
Compared to this, solid-state memory has the advantages that compact-sized, strong environmental adaptability, and market is commercial at present consolidates State hard disk (SSD) belongs to solid-state memory product；But current commercial solid state hard disk (SSD) product capacity is small, speed is low, collection Become second nature difference, is not able to satisfy the storage of High speed real-time signal processing device and plays demand, and what exploitation was stored based on semiconductor solid-state There are five technological difficulties for private memory tool: the semicondctor storage array controller of (one) design high density large capacity；(2) In order to extend the failure free time of memory, to all storing semiconductors on the private memory stored based on semiconductor solid-state Load balancing control is most important and difficult；(3) in the private memory stored based on semiconductor solid-state, to data Storage and reading speed and data accuracy requirement it is particularly important, it is therefore desirable to pass through multinomial technology guarantee zero defect Ground high speed operation；(4) the PCIe control between the private memory host based on semiconductor solid-state storage and high-speed data are logical Letter；(5) (such as AD analog input card, Signal transacting board analysis, these equipment plate cards are total by VPX with the other equipment board in cabinet Line backboard formed electrical connection) between high speed interface as Data entries and data outlet.
Summary of the invention
For above the shortcomings of the prior art, it is an object of the invention to propose that one kind is deposited based on all solid state semiconductor The radar digital signal processing device of memory array, at radar digital signal of this kind based on all solid state semicondctor storage array Reason device can overcome high bandwidth existing for existing memory technology record with play, high density storage, insertion VPX ruggedized equipment and Carried out in particular surroundings using problem, while be also it is a kind of based on all solid state semiconductor storage, highly reliable, high density, height The specific store of speed plays integrated apparatus.
To reach above-mentioned technical purpose, the present invention is realised by adopting the following technical scheme.
A kind of radar digital signal processing device based on all solid state semicondctor storage array, comprising: high density is entirely solid State semicondctor storage array memory plane and main control computer；The all solid state semicondctor storage array memory plane packet of high density Include FPGA and all solid state semicondctor storage array；The FPGA includes: embedded software core processor, AXI bus, PCIe control Device, all solid state semicondctor storage array controller and SRIO controller；The main control computer includes a bidirectional port, institute Stating embedded software core processor includes a bidirectional port, and the AXI bus includes four bidirectional ports, the PCIe controller Comprising two bidirectional ports, all solid state semicondctor storage array controller includes four bidirectional ports, the SRIO control Device processed includes two bidirectional ports, and all solid state semicondctor storage array includes a bidirectional port；
Main control computer is by a bidirectional port of the two-way electrical connection PCIe controller of PCIe bus, and the four of AXI bus A bidirectional port is electrically connected another bidirectional port, complete of the bidirectional port of embedded software core processor, PCIe controller One bidirectional port of one bidirectional port of solid state semiconductor memory array control unit, SRIO controller；It is all solid state partly to lead The other three bidirectional port of body memory array control unit is electrically connected one bidirectional port of residue, complete of PCIe controller Another bidirectional port of the bidirectional port of solid state semiconductor memory array, SRIO controller；
The main control computer passes through PCIe bus for the control instruction for obtaining control instruction and radar return PCIe controller is sent to radar return；The control instruction includes store instruction, reads instruction, erasing instruction, initialization Instruction and functional configuration operational order；
The PCIe controller solves the control instruction received for receiving control instruction and radar return Analysis, is then sent to embedded software core processor for the control instruction after parsing by AXI bus；Embedded software core processor is used Control instruction after receiving and executing parsing, then gives main control computer feedback operation state by PCIe controller；It will solution Control instruction after analysis is sent to all solid state semicondctor storage array controller；The PCIe controller is by radar return simultaneously It is packaged, and is communicated according to PCIe protocol with main control computer；The working condition is that the control instruction after parsing is opened Begin to execute, be carrying out or be finished；
The all solid state semicondctor storage array controller is used to obtain control instruction and radar return after parsing, and Radar return is encoded, the radar return after being encoded, and is sent out the radar return after coding by Nand I/O interface It send to all solid state semicondctor storage array and is stored；All solid state semicondctor storage array is by the radar after the coding of storage Echo is sent to all solid state semicondctor storage array controller and is decoded, and obtains radar return, and radar return is sent To main control computer；All solid state semicondctor storage array controller obtains all solid state semiconductor according to the control instruction after parsing The respective working condition of memory array and all solid state semicondctor storage array controller, and by all solid state semiconductor memory battle array Respectively working condition is sent to embedded software core processor, Embedded Soft Core to column with all solid state semicondctor storage array controller Processor is for receiving and being packaged all solid state semicondctor storage array and all solid state semicondctor storage array controller respectively Then working condition is fed back all solid state semicondctor storage array to main control computer by PCIe controller and all solid state is partly led The respective working condition of body memory array control unit；The radar return after coding is sent to SRIO controller simultaneously；
The SRIO controller is used to obtain the radar return after control instruction and coding, and the control instruction of acquisition is sent out It send to embedded software core processor and is parsed and executed, current SRIO is then fed back to PCIe controller by AXI bus and is controlled The working condition of device processed；The radar return after coding is sent to external equipment by SRIO link simultaneously and carries out HWIL simulation Or Radar Signal Processing.
Beneficial effects of the present invention: the present invention uses field programmable gate array (Field Programmable Gate Array, FPGA) as main realization platform of the invention, it is communicated, is used with main control computer using PCIe bus control unit SRIO high speed data link and peripheral communications are realized under system administration control, are deposited to the highdensity solid-state of large capacity Memory array carries out high-speed record, controllable broadcasting, data management and maintenance management function.
Detailed description of the invention
Invention is further described in detail with reference to the accompanying drawings and detailed description.
Fig. 1 is the structural schematic diagram of apparatus of the present invention；
Fig. 2 is the function structure chart of all solid state semicondctor storage array controller；
Fig. 3 is the structural schematic diagram of PCIe bus control unit；
Fig. 4 is the structural schematic diagram of SRIO controller module；
Fig. 5 is memory plane host computer interface figure；
Fig. 6 is that memory plane records sub-interface figure；
Fig. 7 is that memory plane plays back sub-interface figure；
Fig. 8 is that memory plane exports sub-interface figure；
Fig. 9 is that memory plane imports sub-interface figure.
Specific embodiment
It referring to Fig.1, is the structural schematic diagram of apparatus of the present invention；One kind of the invention is based on all solid state semiconductor memory battle array The repertoire for including in the radar digital signal processing device of column is realized in main control computer and FPGA respectively, described to be based on The digital signal dedicated unit of all solid state semicondctor storage array, comprising: all solid state semicondctor storage array of high density is deposited Store up plate and main control computer；The all solid state semicondctor storage array memory plane of high density includes FPGA and all solid state semiconductor Memory array；The FPGA includes: embedded software core processor, AXI bus, PCIe controller, all solid state semiconductor storage Device array control unit and SRIO controller；The main control computer includes a bidirectional port, the embedded software core processor Comprising a bidirectional port, the AXI bus includes four bidirectional ports, and the PCIe controller includes two bidirectional ports, The all solid state semicondctor storage array controller includes four bidirectional ports, and the SRIO controller includes two bidirectional ends Mouthful, all solid state semicondctor storage array includes a bidirectional port.
Main control computer passes through a bidirectional port of the two-way electrical connection PCIe controller of main control computer PCIe bus, Four bidirectional ports of AXI bus be electrically connected the bidirectional port of embedded software core processor, PCIe controller another Bidirectional port, a bidirectional port of all solid state semicondctor storage array controller, SRIO controller a bidirectional port； The other three bidirectional port of all solid state semicondctor storage array controller is electrically connected residue one of PCIe controller Bidirectional port, the bidirectional port of all solid state semicondctor storage array, SRIO controller another bidirectional port.
The main control computer passes through PCIe bus for the control instruction for obtaining control instruction and radar return PCIe controller is sent to radar return；The control instruction includes store instruction, reads instruction, erasing instruction, initialization Instruction and functional configuration operational order.
The PCIe controller solves the control instruction received for receiving control instruction and radar return Analysis, is then sent to embedded software core processor for the control instruction after parsing by AXI bus；Embedded software core processor is used Control instruction after receiving and executing parsing, then gives main control computer feedback operation state by PCIe controller；It will solution Control instruction after analysis is sent to all solid state semicondctor storage array controller；The PCIe controller is by radar return simultaneously It is packaged, and is communicated according to PCIe protocol with main control computer；The working condition is that the control instruction after parsing is opened Begin to execute, be carrying out or be finished.
The all solid state semicondctor storage array controller is used to obtain control instruction and radar return after parsing, and Radar return is encoded, the radar return after being encoded, and (Nand IO connects by semiconductor memory access interface Mouthful) radar return after coding is sent to all solid state semicondctor storage array stores；All solid state semiconductor memory Radar return after the coding of storage is sent to all solid state semicondctor storage array controller and is decoded by array, obtains thunder Main control computer is sent to up to echo, and by radar return；After all solid state semicondctor storage array controller is according to parsing Control instruction obtains all solid state semicondctor storage array and all solid state semicondctor storage array controller respectively working condition, And by all solid state semicondctor storage array and all solid state semicondctor storage array controller respectively working condition be sent to it is embedding Enter formula soft-core processor, embedded software core processor is for receiving and being packaged all solid state semicondctor storage array and all solid state half Then the respective working condition of conductor memory array control unit is fed back to main control computer by PCIe controller and all solid state is partly led The respective working condition of body memory array and all solid state semicondctor storage array controller；Simultaneously by the radar return after coding It is sent to SRIO controller；Wherein, all solid state semicondctor storage array includes 96 Flash chips.
The SRIO controller is used to obtain the radar return after control instruction and coding, and the control instruction of acquisition is sent out It send to embedded software core processor and is parsed and executed, current SRIO is then fed back to PCIe controller by AXI bus and is controlled The working condition of device processed；The radar return after coding is sent to external equipment by SRIO link simultaneously and carries out HWIL simulation Or Radar Signal Processing.
Specifically, apparatus of the present invention emphasis is to realize that all solid state semicondctor storage array of high density stores plate array control System, embedded software core processor intarconnected cotrol and embedded software core processor are integrated, and wherein embedded software core processor is this hair Bright control core is responsible for state-maintenance and the operation distribution of whole device, the FPGA internal frame diagram of institutional framework as shown in figure 1 It is shown, the purposes of each sub-function module is illustrated in detail below:
It (one) is the function structure chart of all solid state semicondctor storage array controller referring to Fig. 2；All solid state semiconductor is deposited The modular structure of memory array controller include all solid state semicondctor storage array memory, user logic, infrastructure and State acquisition unit: all solid state semicondctor storage array memory includes: storage control, user logic layer, basis Facility, state acquisition unit；The storage control includes: physical layer, Media Interface Connector layer, memory command layer, storage link Layer, memory maintenance and configuration unit；The physical layer is connect with the Media Interface Connector layer, and the Media Interface Connector layer is deposited with described The connection of reservoir layer order, the memory command layer are connect with the storage link layer, the storage link layer and the user It is connected using logical layer；The user logic includes four ports, is separately connected the user using logical layer, the memory Maintenance and configuration unit, the infrastructure and the state acquisition unit.
The physical layer be used for receives parse after control instruction and radar return, the control instruction after the parsing include Store instruction reads instruction, erasing instruction, initialization directive and functional configuration operational order, and obtains and meet Nand Flash Double Data Rate synchronous sequence interface model physical layer data stream that technical manual defines, single times of rate synchronous timing interface model object Recombination data stream after managing layer data stream or parsing, and, delay adjustment synchronous by data edge to radar return, timing adjust Or be fanned out to, it obtains meeting the operation timing that Nand Flash technology handbook defines, is then forwarded to all solid state semiconductor memory In array；Physical layer is also used to meet what Nand Flash technology handbook defined from Nand flash storage array received simultaneously Sequential data stream, then in turn through cache synchronization, timing adjustment, delay adjustment, timing reconstruction, data resampling or data pair Neat operation, obtain meeting Double Data Rate synchronous sequence interface model physical layer data stream that Nand Flash technology handbook defines or Single times of rate synchronous timing interface model physical layer data stream, and it is sent to Media Interface Connector layer.
It is described to meet Nand Flash technology hand for what is sended over by local timing interface (NIF) reception physical layer The Double Data Rate synchronous sequence interface model physical layer data stream or single times of rate synchronous timing interface model physical layer of volume definition Nand Flash manipulation of data stream after the decomposition that data flow and store command layer send over, and according to Nand Flash The Double Data Rate synchronous sequence interface model physical layer data stream or single times of rate synchronous timing interface model that technical manual defines Successively carry out parsing operation and recombination data stream, the recombination data stream after being parsed, then by the recombination number after the parsing Physical layer is sent to by physical link interface (PIF) according to stream；Media Interface Connector layer is used to pass through PIF interface physical layer simultaneously The Double Data Rate synchronous sequence interface model physical layer data stream, the list that meet Nand Flash technology handbook and define sended over Recombination data stream after times rate synchronous timing interface model physical layer data stream or parsing, and successively parsed and reconstructed, Nand Flash manipulation of data stream is obtained, then passes through local timing interface (NIF) interface for the Nand Flash operand Memory command layer is sent to according to stream.
The memory command layer is connect for receiving the Nand Flash manipulation of data stream, and respectively by ordering to control Mouth (CIF) obtains the respective operations instruction of Nand Flash manipulation of data stream from storage link layer, and is connect by ordering to control Mouth (CIF) obtains the data frame for meeting command interface timing from storage link layer, is then successively parsed and is decomposed, is divided Nand Flash manipulation of data stream after solution, then grasped the Nand Flash after the decomposition by local timing interface (NIF) Media Interface Connector layer is sent to as data flow；Simultaneous memory layer order is sended over by NIF interface Media Interface Connector layer Nand Flash manipulation of data stream after decomposition obtains command interface timing after being packaged, and passes through order control interface (CIF) it is sent to storage link layer.
The storage link layer is obtained for receiving the command interface timing, and by memory control interface (MIF) The operational order and respective operations data that user applies logical layer to send over, and successively by tissue frame format, addition mistake After control coding, data traffic control, the data frame for meeting command interface timing is obtained, then according to depositing order control interface (CIF) data frame for meeting command interface timing is sent to memory command layer by timing requirements；Link layer is stored simultaneously To the command interface timing successively by parsing frame format, decoding extract after, obtain decoded command interface timing, and lead to It crosses memory control interface (MIF) and the decoded command interface timing is sent to user using logical layer.
The user logic is respectively used to obtain required system clock and use when register configuration order, user logic work The operational order of data format needed for family logic global reset signal, operational order data flow, user logic and current time Physical layer, Media Interface Connector layer, memory command layer, storage link layer, memory maintenance and configuration unit, infrastructure and use Apply logical layer respectively working condition in family；The operational order data stream packets containing store instruction, read instruction, erasing instruction, first Beginningization instruction and the respective corresponding data stream of functional configuration operational order.
The memory maintenance and configuration unit belong to independent functional unit in Memory Controller, for by auxiliary Adjuvant grafting mouth obtains the register configuration order that user logic sends over, and then parses the register configuration order, is solved Register configuration order after analysis, and the register configuration order after parsing is respectively sent to physical layer, Media Interface Connector layer, is deposited Reservoir layer order and storage link layer；Simultaneous memory maintenance and configuration unit for respectively read physical layer, Media Interface Connector layer, Memory command layer and the storage corresponding register configuration order of link layer, and user is sent to by satellite interface and is patrolled Volume.
The infrastructure obtains required system clock and the user logic overall situation when user logic works by system interface Reset signal, required system clock and user logic global reset signal are successively locked when then working the user logic Xiang Huan, clock are fanned out to and reset simultaneously operating, obtain multiple work clocks and with the synchronous work respectively of multiple work clocks Reset signal, and synchronous power on reset signal is respectively sent to physics respectively by multiple work clocks and with multiple work clocks Layer, Media Interface Connector layer, memory command layer, storage link layer, memory maintenance and configuration unit；Meanwhile when by multiple work Clock and synchronous power on reset signal is exported to user logic respectively with multiple work clocks.
The state acquisition unit is for obtaining current time physical layer, Media Interface Connector layer, memory command layer, storage chains Road floor, memory maintenance and configuration unit, infrastructure and user apply logical layer respectively working condition, and are connect by state Mouthful by current time physical layer, Media Interface Connector layer, memory command layer, storage link layer, memory maintenance and configuration unit, base Respectively working condition is sent to user logic using logical layer by Infrastructure and user.
It is the layering of user logic custom feature that the user, which applies logical layer, for obtaining user by user interface The operational order of data format needed for operational order data flow and user logic that logic sends over, and it is organized into memory control Then data format and operational format needed for interface (MIF) processed are sent to storage link by memory control interface (MIF) Layer；The storage link layer obtains the operational order that Nand flash storage array can identify, institute from user logic simultaneously The operational order that Nand flash storage array can identify is stated to visit including storage, reading, functional configuration operation, direct store Ask (Direct Menory Access, DMA) write-in, DMA read, programmable input and output (Program Input Output, PIO) write-in, PIO reading, bulk erasure, simple erasing or initialization operation order, and to the Nand flash storage battle array The operational order that arranging can identify successively is parsed and is reconstructed, and the operational order of data format needed for user logic is obtained, then The operational order of data format needed for the user logic is sent to user logic by state interface.
It (two) is the structural schematic diagram of PCIe bus control unit referring to Fig. 3；PCIe controller includes physical layer, link layer And transport layer, the transport layer include register file, direct memory access (Direct Memory Access, DMA) control Device, power management；Physical layer and link layer complete respective function by the IP that Xilinx is provided respectively；Transport layer provides two pairs To port, respectively user register port (User Register Port) and direct memory access (Direct Memory Access, DMA) port, when wherein program input/output is transmitted, user accesses register file by user register port When, respectively correspond the up arrow and down arrow of this port), register file passes through PCIe protocol transparent mapped to master control Storage region in computer is read out, and the access includes reading and writing；The port DMA high-volume is completed by dma controller Data transmit-receive work；User data enters PCIe bus control unit by the port DMA, successively passes through dma controller, link layer and object Reason layer is packaged according to PCIe protocol, obtains communication data, and be sent to main control computer by PCIe bus；Master control simultaneously Computer issues communication data by PCIe bus, is successively decapsulated, is used by physical layer, link layer and transport layer User data, and user data is sent out by the port DMA；The power management is power management module, for being PCIe bus Controller power supply.
(3) SRIO controller uses full mesh interconnection architecture, can be realized the high speed interconnection of arbitrary node, i.e. realization plate Between pass through at a high speed, as shown in figure 4, SRIO controller include user logic, direct memory access (Direct Memory Access, DMA) controller, transport layer, link layer, physical layer, infrastructure；User logic transmits data to DMA control Device successively passes through transport layer, link layer and physical layer by SRIO agreement again after dma controller encapsulation and is packaged, obtains The data completed to final encapsulation, and the data that final encapsulation is completed are sent according to SRIO agreement by SRIO link；Simultaneously The data of SRIO chain road are received, and are successively exported after the decapsulation of physical layer, link layer and transport layer to user logic.
(4) embedded software core processor is control core of the invention, is responsible for state-maintenance and the operation point of whole system Match, major function is to receive and parse through the operational order from main control computer and detection lug internal controller state and pass through PCIe Bus is reported to host computer, instruction explanation function be responsible for for the operational order of host computer being construed to memory array controller, The register instruction of SRIO controller is responsible for configuration feature register and fill state register.
Above-mentioned four big functional module is connected, at Embedded Soft Core using embedded software core processor as core by AXI bus It manages device and PCIe controller, SRIO controller and all solid state semicondctor storage array controller is completed respectively by AXI bus Function setting and state are read, as shown in the FPGA internal frame diagram of Fig. 1；Secondly, PCIe controller, SRIO controller and all solid state half There is dedicated high speed interface between conductor memory array control unit respectively, meet AXI_Stream standard, can pass through The control of embedded software core processor carries out the data transmission of high speed.
Wherein, above-mentioned embedded software core processor, PCIe bus control unit, all solid state semicondctor storage array controller It realizes inside onboard FPGA with SRIO controller, all solid state is partly led by the way that the I/O interface bus marco of Nand Flash is onboard Body memory array realizes the storage of high-speed high capacity data；In apparatus of the present invention, all solid state semiconductor memory battle array of high density Column memory plane is attached by PCIe bus with main control computer, and completing order control and data transmission, (envelope is imported and led Out), the data connection between other equipment is respectively completed by SRIO controller, and completes record and the playback of data； The other equipment such as AD analog input card, Signal transacting board analysis, and connected by VPX bus backplane.
In the global structure of the present invention that Fig. 1 is shown, main control computer as host computer play center control, data storage and Restore function.Fig. 5 is memory plane control interface figure；In Fig. 5, the signified part of label 1 is the file information list, for showing simultaneously The class file information of record storage equipment, including filename, file type, record time, file size, initial address, end Address and data source, the class file information are stored in main control computer by XML file, and main control computer is by being defined in Host interface protocol in PCIe bus completes the communication between memory plane, realizes state self-test, record, playback, imports, leads Out, it deletes, format and forces to stop function, illustrate the effect of each single item function in detail below.
The signified part of label 2 is self-test in Fig. 5, i.e., sends the self-test order in Host Interface Commands to memory plane, successively The detection of memory plane working condition and feedback testing result are completed, wherein the detection includes all solid state semicondctor storage array Controller working condition, the operating mode of all solid state semicondctor storage array and current state, PCIe controller working condition, The link connection state and embedded software core processor operating status of SRIO controller.
The signified part of label 3 is record in Fig. 5, i.e., sends the record order in Host Interface Commands to memory plane, described Record order includes record start address and record length, and Fig. 6 display record work sub-interface, in the interface, user can match Recording parameters are set, the recording parameters are record filename, record time, record start address, record length；Memory plane receives After order, embedded software core processor carries out resolve command, record length and record start address is obtained, to all solid state semiconductor Memory array controller sends batch write operation, and transmits and receives and operate to SRIO controller, and control SRIO controller Record length and record start address are sent into all solid state semicondctor storage array controller, complete record length and recorded Beginning address is received and recorded in all solid state semicondctor storage array.
The signified part of label 4 is playback in Fig. 5, i.e., sends the playback command in Host Interface Commands to memory plane, described Playback command includes playback initial address, playback length and flow control option, Fig. 7 display playback work sub-interface, on the boundary In face, user can configure playback parameter, and the playback parameter is playback file name, playback duration, playback initial address, playback length Degree, enabled, the playback flow control word of playback flow control etc.；After memory plane receives order, Embedded Soft Core processor scheduling SRIO controller and all solid state semicondctor storage array controller read data simultaneously from all solid state semicondctor storage array It is sent by SRIO interface toward other equipment, the other equipment are AD analog input card, Signal transacting board analysis, and total by VPX The connection of line backboard；Wherein, the flow control option belongs to source flow control, sends data speed for controlling.
The signified part of label 5 is export in Fig. 5, i.e., sends the export (swf) command in Host Interface Commands to memory plane, described Export (swf) command includes export initial address and derived length, and Fig. 8 display export work sub-interface, in the interface, user can match Derived parameter is set, the derived parameter is export name, export time, export initial address, derived length etc.；Memory plane is received To after order, embedded software core processor resolve command obtains export initial address and derived length, passes through AXI bus marco All solid state semicondctor storage array controller is read, while being sent directly by AXI bus to PCIe controller Internal storage access order, PCIe controller receive direct memory access order and are sent to main control computer, and main control computer receives Dma controller after direct memory access order in PCI allocation e controller；Wherein, the configuration includes the packet of dma controller Length, the packet number of dma controller and the address of dma controller；Finally, all solid state semicondctor storage array controller is read Export initial address and derived length will be sent with dma mode to main control computer by the dma controller of PCIe controller.
In Fig. 5 the signified part of label 6 sends the importing order in Host Interface Commands to memory plane to import, described Importing order includes importing initial address and importing length, and Fig. 9 display imports work sub-interface, and in the interface, user can match Importing parameter is set, the importing parameter is to import filename, import the time, import initial address, import length etc..Board receives It imports after order and embedded software core processor is sent to by AXI bus, embedded software core processor is received to import to order and be gone forward side by side Row parsing obtains and imports initial address and import length, then the dma controller in PCI allocation e controller and notifies master control meter Calculation machine, main control computer receives the dma controller imported after command response in PCI allocation e controller, then from main control computer It receives and imports initial address and import length and be written in all solid state semicondctor storage array；Wherein, the configuration includes DMA Packet length, the packet number of dma controller and the address of dma controller of controller.
In Fig. 5 the signified part of label 7 sends the delete command in Host Interface Commands to memory plane to delete, described Delete command includes deleting initial address and deleting length, while main control computer removes the respective file in the file information list Record, after memory plane receives delete command, all solid state semicondctor storage array controller of Embedded Soft Core processor scheduling is simultaneously Start erasing operation, the respective file is recorded and carries out physics erasing operation.
In Fig. 5 the signified part of label 8 sends the formatting command in Host Interface Commands to memory plane to format, Main control computer empties the record of the All Files in the file information list, after board receives formatting command, embedded software simultaneously Core processor dispatches all solid state semicondctor storage array controller and starts full array erasing operation, and then partly leads to all solid state Body memory array carries out physics erasing operation.
In Fig. 5 the signified part of label 9 is stopped to force to stop for sending the pressure in Host Interface Commands to memory plane It only orders, while main control computer waits the state feedback between memory plane；Board receives after pressure ceases and desist order, embedded software Core processor is controlled according to current working status to SRIO controller, PCIe controller and all solid state semicondctor storage array Device sends corresponding emergent stopping control respectively, and then memory plane enters Auto-Sensing Mode, detects memory plane current state and feeds back To main control computer.
In addition, dedicated unit of the present invention has following function:
(1) all solid state semiconductor array reinforces storage equipment: under conditions of outfield experiments and real system are run, receiving The original data stream of collection high speed facilitates the analysis of phenomenon, technology adjustment and system mode monitoring, under most conditions, needs to add Solid special equipment could cope with the mal-condition including high temperature difference, high humility, strong motion, more dust etc. of real system operation Weather and climate condition.The present invention uses all solid state semiconductor storage, belongs to reinforcement embedded device, has technical grade environment item Part index, intrinsic mechanical stability ensure that the reliable and stable operation of this equipment under severe conditions from design.
(2) record of high sDeed real-time digital signal and broadcasting: former in the embedded system for real-time signal processing of high speed The high bandwidth of beginning data is proposed high requirement to acquisition, storage and broadcasting；And initial data acquisition and playback for System Performance Analysis, system running state monitoring will be it is indispensable, the present invention is realized by multinomial technological means embedding The acquisition and playback of high speed raw digital signal are realized in embedded system.
(3) be used for the random waveform signal digital signal broadcast source of HWIL simulation: the joint debugging work of large scale system is often It is related to the more common joint debuggings of unit, the extension set in the subsystem debugging of research and development early period, use process is examined, the performance of algorithm is commented Estimate and requires digital signal playback equipment and provide stable, controllable, the true front end of simulation number to signal processing subsystem Signal, the present invention provide complete solution for such HWIL simulation demand.The certain wave of initial data, emulation construction Graphic data or other any data for meeting particular demands can first pass through main control computer in advance and import this equipment, and embedding The data are played in embedded system, realize the function of HWIL simulation validation test.
The present invention realizes the dedicated high density high speed storing of integration and broadcasting by following technological means:
(1) memory control problem is solved using the high density large-capacity semiconductor memory array controller of customization: this Invention is using separate semiconductor storage particle as basic storage medium；For large-scale storage array still without dedicated control Device IP processed provides use, and therefore, the present invention uses the memory array controller of customized development, completes the height to high density arrays The read and write access of fast zero defect controls.
(2) control and data exchange with main control computer are realized using PCIe bus: the present invention as computer outside Peripheral equipment accesses computer system by PCIe bus, and carry passes through main control computer in the PCIe bus of computer-internal It realizes to order control of the invention and data access operation, there is biggish control flexibility and data interface bandwidth.
(3) acquisition and broadcasting of high speed original data stream are realized using SRIO data/address bus: in embedded device, The present invention and other embedded boards are realized using SRIO controller to be interconnected, and is carried out the acquisition of high speed original data stream and broadcast It puts, belongs to isomery full mesh interconnection architecture, provide the controllable system interconnection of high speed.
(4) realize controlled speed broadcasting using source flow control technique and storage dedicated frame design: the present invention uses The dedicated dedicated frame structure of storage is packaged the initial data of storage, improves memory reliability, and cooperate the present invention Source flow control technique, can be realized the output effective data rate of controllable variable, meet rear end receive system to difference The requirement of data transfer rate improves system adaptation performance.
(5) system remote upgrade and demand change: this hair are realized as master controller using embedded software core processor It is bright to use the connection of AXI bus as onboard master controller, between embedded software core processor and onboard peripheral hardware using system on chip, It ensure that the high bandwidth of connection, the flexibility of control and convenient and fast expansion, embedded software core processor external interface abundant Characteristic with software programmable is that the present invention provides the characteristics of remote system upgrade.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art Mind and range；In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies Within, then the present invention is also intended to include these modifications and variations.

Claims (8)

1.一种基于全固态半导体存储器阵列的雷达数字信号处理装置，其特征在于，包括：高密度全固态半导体存储器阵列存储板和主控计算机；所述高密度全固态半导体存储器阵列存储板包括FPGA和全固态半导体存储器阵列；所述FPGA包括：嵌入式软核处理器、AXI总线、PCIe控制器、全固态半导体存储器阵列控制器和SRIO控制器；所述主控计算机包含一个双向端口，所述嵌入式软核处理器包含一个双向端口，所述AXI总线包含四个双向端口，所述PCIe控制器包含两个双向端口，所述全固态半导体存储器阵列控制器包含四个双向端口，所述SRIO控制器包含两个双向端口，所述全固态半导体存储器阵列包含一个双向端口；1. A radar digital signal processing device based on an all-solid-state semiconductor memory array, characterized in that, comprising: a high-density all-solid-state semiconductor memory array storage board and a main control computer; the high-density all-solid-state semiconductor memory array storage board includes an FPGA and an all-solid-state semiconductor memory array; the FPGA includes: an embedded soft-core processor, an AXI bus, a PCIe controller, an all-solid-state semiconductor memory array controller, and an SRIO controller; the host computer includes a bidirectional port, and the The embedded soft core processor contains one bidirectional port, the AXI bus contains four bidirectional ports, the PCIe controller contains two bidirectional ports, the all solid state semiconductor memory array controller contains four bidirectional ports, the SRIO the controller includes two bidirectional ports and the all-solid-state semiconductor memory array includes one bidirectional port; 主控计算机通过PCIe总线双向电连接PCIe控制器的一个双向端口，AXI总线的四个双向端口分别电连接嵌入式软核处理器的双向端口、PCIe控制器的另一个双向端口、全固态半导体存储器阵列控制器的一个双向端口、SRIO控制器的一个双向端口；全固态半导体存储器阵列控制器的另外三个双向端口分别电连接PCIe控制器的剩余一个双向端口、全固态半导体存储器阵列的双向端口、SRIO控制器的另一个双向端口；The main control computer is bidirectionally connected to a bidirectional port of the PCIe controller through the PCIe bus, and the four bidirectional ports of the AXI bus are electrically connected to the bidirectional port of the embedded soft-core processor, the other bidirectional port of the PCIe controller, and the all-solid-state semiconductor memory. One bidirectional port of the array controller, one bidirectional port of the SRIO controller; the other three bidirectional ports of the all-solid-state semiconductor memory array controller are respectively electrically connected to the remaining one bidirectional port of the PCIe controller, the bidirectional port of the all-solid-state semiconductor memory array, Another bidirectional port of the SRIO controller; 所述主控计算机用于获取控制指令和雷达回波，并通过PCIe总线将所述控制指令和雷达回波发送至PCIe控制器；所述控制指令包括存储指令、读取指令、擦除指令、初始化指令和功能配置操作指令；The main control computer is used to obtain control instructions and radar echoes, and send the control instructions and radar echoes to the PCIe controller through the PCIe bus; the control instructions include storage instructions, reading instructions, erasing instructions, Initialization instructions and functional configuration operation instructions; 所述PCIe控制器用于接收控制指令和雷达回波，并对接收到的控制指令进行解析，然后通过AXI总线将解析后的控制指令发送至嵌入式软核处理器；嵌入式软核处理器用于接收并执行解析后的控制指令，然后通过PCIe控制器给主控计算机反馈工作状态；将解析后的控制指令发送至全固态半导体存储器阵列控制器；同时所述PCIe控制器将雷达回波进行打包，并按照PCIe协议与主控计算机进行通信；所述工作状态为解析后的控制指令开始执行、正在执行或执行完毕；The PCIe controller is used to receive control commands and radar echoes, parse the received control commands, and then send the parsed control commands to the embedded soft-core processor through the AXI bus; the embedded soft-core processor is used for Receive and execute the parsed control instructions, and then feed back the working status to the main control computer through the PCIe controller; send the parsed control instructions to the all-solid-state semiconductor memory array controller; at the same time, the PCIe controller packages the radar echoes , and communicate with the main control computer according to the PCIe protocol; the working state is that the parsed control instruction starts to be executed, is being executed, or is executed; 所述全固态半导体存储器阵列控制器用于获取解析后的控制指令和雷达回波，并对雷达回波进行编码，获得编码后的雷达回波，并将编码后的雷达回波发送至全固态半导体存储器阵列进行存储；全固态半导体存储器阵列将存储的编码后的雷达回波发送至全固态半导体存储器阵列控制器进行解码，得到雷达回波，并将雷达回波发送至主控计算机；全固态半导体存储器阵列控制器根据解析后的控制指令获取全固态半导体存储器阵列和全固态半导体存储器阵列控制器各自工作状态，并将全固态半导体存储器阵列和全固态半导体存储器阵列控制器各自工作状态发送至嵌入式软核处理器，嵌入式软核处理器用于接收并打包全固态半导体存储器阵列和全固态半导体存储器阵列控制器各自工作状态，然后通过PCIe控制器给主控计算机反馈全固态半导体存储器阵列和全固态半导体存储器阵列控制器各自工作状态；同时将编码后的雷达回波发送至SRIO控制器；The all-solid-state semiconductor memory array controller is used to acquire the parsed control commands and radar echoes, encode the radar echoes, obtain the encoded radar echoes, and send the encoded radar echoes to the all-solid-state semiconductors The memory array is used for storage; the all-solid-state semiconductor memory array sends the stored encoded radar echoes to the all-solid-state semiconductor memory array controller for decoding to obtain the radar echoes, and sends the radar echoes to the main control computer; all-solid-state semiconductors The memory array controller obtains the respective working states of the all-solid-state semiconductor memory array and the all-solid-state semiconductor memory array controller according to the parsed control instructions, and sends the respective working states of the all-solid-state semiconductor memory array and the all-solid-state semiconductor memory array controller to the embedded Soft-core processor, the embedded soft-core processor is used to receive and package the respective working states of the all-solid-state semiconductor memory array and the all-solid-state semiconductor memory array controller, and then feed back the all-solid-state semiconductor memory array and all-solid-state semiconductor memory array to the host computer through the PCIe controller. The respective working states of the semiconductor memory array controllers; at the same time, the encoded radar echoes are sent to the SRIO controller; 所述SRIO控制器用于获取控制指令和编码后的雷达回波，并将获得的控制指令发送至嵌入式软核处理器进行解析与执行，然后通过AXI总线给PCIe控制器反馈当前SRIO控制器的工作状态；同时将编码后的雷达回波通过SRIO链路发送至外接设备进行半实物仿真或雷达信号处理。The SRIO controller is used to obtain the control command and the encoded radar echo, send the obtained control command to the embedded soft-core processor for analysis and execution, and then feed back the current SRIO controller through the AXI bus to the PCIe controller. Working state; at the same time, the encoded radar echo is sent to the external device through the SRIO link for hardware-in-the-loop simulation or radar signal processing. 2.如权利要求1所述的一种基于全固态半导体存储器阵列的雷达数字信号处理装置，其特征在于，所述全固态半导体存储器阵列控制器的模块结构包括全固态半导体存储器阵列存储器、用户逻辑、基础设施和状态采集单元：所述全固态半导体存储器阵列存储器包括：存储控制器、用户逻辑层、基础设施、状态采集单元；所述存储控制器包括：物理层、介质接口层、存储器命令层、存储链路层、存储器维护和配置单元；所述物理层与所述介质接口层连接，所述介质接口层与所述存储器命令层连接，所述存储器命令层与所述存储链路层连接，所述存储链路层与所述用户逻辑层连接；用户逻辑包含四个端口，分别连接所述用户逻辑层、所述存储器维护和配置单元、所述基础设施和所述状态采集单元。2. A radar digital signal processing device based on an all-solid-state semiconductor memory array according to claim 1, wherein the module structure of the all-solid-state semiconductor memory array controller comprises an all-solid-state semiconductor memory array memory, a user logic , infrastructure and state acquisition unit: the all-solid-state semiconductor memory array memory includes: a storage controller, a user logic layer, infrastructure, and a state acquisition unit; the storage controller includes: a physical layer, a media interface layer, and a memory command layer , storage link layer, storage maintenance and configuration unit; the physical layer is connected with the medium interface layer, the medium interface layer is connected with the memory command layer, and the memory command layer is connected with the storage link layer , the storage link layer is connected with the user logic layer; the user logic includes four ports, which are respectively connected to the user logic layer, the memory maintenance and configuration unit, the infrastructure and the state acquisition unit. 3.如权利要求2所述的一种基于全固态半导体存储器阵列的雷达数字信号处理装置，其特征在于，所述物理层用于接收解析后的控制指令和雷达回波，所述解析后的控制指令包括存储指令、读取指令、擦除指令、初始化指令和功能配置操作指令，并获取双倍速率同步时序接口模型物理层数据流、单倍速率异步时序接口模型物理层数据流或解析后的重组数据流，并对雷达回波进行数据边沿同步、延迟调整、时序调整或扇出，得到操作时序，然后发送至Nand Flash存储器阵列中；同时物理层还用于从Nand Flash存储器阵列接收时序数据流，然后依次经过缓存同步、时序调整、延迟调整、时钟重建、数据重采样或数据对齐操作，得到双倍速率同步时序接口模型物理层数据流或单倍速率异步时序接口模型物理层数据流，并发送至介质接口层；3. A radar digital signal processing device based on an all-solid-state semiconductor memory array according to claim 2, wherein the physical layer is used to receive parsed control commands and radar echoes, and the parsed Control commands include storage commands, read commands, erase commands, initialization commands, and function configuration operation commands, and obtain the physical layer data stream of the double-rate synchronous timing interface model, the physical layer data stream of the single-rate asynchronous timing interface model, or the parsed data stream. The data stream is reorganized, and the data edge synchronization, delay adjustment, timing adjustment or fan-out is performed on the radar echo, and the operation timing is obtained, and then sent to the Nand Flash memory array; at the same time, the physical layer is also used to receive timing from the Nand Flash memory array. Data flow, and then through cache synchronization, timing adjustment, delay adjustment, clock reconstruction, data resampling or data alignment operations in sequence, to obtain double-rate synchronous timing interface model physical layer data flow or single-rate asynchronous timing interface model physical layer data flow , and sent to the media interface layer; 所述介质接口层用于接收物理层发送过来的双倍速率同步时序接口模型物理层数据流或单倍速率异步时序接口模型物理层数据流，以及获取存储命令层发送过来的分解后的Nand Flash操作数据流，并按照双倍速率同步时序接口模型物理层数据流或单倍速率异步时序接口模型依次进行解析操作和重组数据流，得到解析后的重组数据流，然后将所述解析后的重组数据流发送至物理层；同时介质接口层用于接收物理层发送过来的双倍速率同步时序接口模型物理层数据流、单倍速率异步时序接口模型物理层数据流或解析后的重组数据流，并依次进行解析和重构，得到Nand Flash操作数据流，然后将所述Nand Flash操作数据流发送至存储器命令层。The medium interface layer is used to receive the physical layer data stream of the double-rate synchronous timing interface model sent from the physical layer or the physical layer data stream of the single-rate asynchronous timing interface model, and to obtain the decomposed Nand Flash sent from the storage command layer. Operate the data stream, and perform the parsing operation and reorganize the data stream in turn according to the double-rate synchronous timing interface model physical layer data stream or the single-rate asynchronous timing interface model to obtain the parsed and reconstructed data stream, and then reorganize the parsed and reconstructed data stream. The data stream is sent to the physical layer; at the same time, the medium interface layer is used to receive the double-rate synchronous timing interface model physical layer data stream, the single-rate asynchronous timing interface model physical layer data stream or the parsed reorganized data stream sent from the physical layer. The analysis and reconstruction are performed in sequence to obtain the Nand Flash operation data stream, and then the Nand Flash operation data stream is sent to the memory command layer. 4.如权利要求2所述的一种基于全固态半导体存储器阵列的雷达数字信号处理装置，其特征在于，所述存储器命令层用于接收所述Nand Flash操作数据流，并分别从存储链路层获取Nand Flash操作数据流的对应指令，以及从存储链路层获取符合命令接口时序的数据帧，然后依次进行解析和分解，得到分解后的Nand Flash操作数据流，再将所述分解后的Nand Flash操作数据流发送至介质接口层；同时存储器命令层用于接收介质接口层发送过来的分解后的Nand Flash操作数据流，经过打包后得到命令接口时序，并将所述命令接口时序发送至存储链路层；4. A radar digital signal processing device based on an all-solid-state semiconductor memory array according to claim 2, wherein the memory command layer is used to receive the Nand Flash operation data stream, and respectively from the memory link The layer obtains the corresponding instructions of the Nand Flash operation data stream, and obtains the data frame conforming to the command interface timing from the storage link layer, and then parses and decomposes in turn to obtain the decomposed Nand Flash operation data stream, and then decomposes the decomposed data stream. The Nand Flash operation data stream is sent to the media interface layer; at the same time, the memory command layer is used to receive the decomposed Nand Flash operation data stream sent by the media interface layer, and after packaging, the command interface timing sequence is obtained, and the command interface timing sequence is sent to storage link layer; 所述存储链路层用于接收所述命令接口时序，并获取用户逻辑层发送过来的操作命令和对应操作数据，并依次经过组织帧格式、添加差错控制编码、数据流量控制后，得到符合命令接口时序的数据帧，然后按照存命令接口时序要求将所述符合命令接口时序的数据帧发送至存储器命令层；同时存储链路层对所述命令接口时序依次经过解析帧格式、解码提取后，得到解码后的命令接口时序，并将所述解码后的命令接口时序发送至用户逻辑层。The storage link layer is used to receive the command interface timing sequence, and obtain the operation command and corresponding operation data sent by the user logic layer, and sequentially organize the frame format, add error control codes, and control the data flow to obtain the corresponding command. The data frame of the interface timing, and then according to the storage command interface timing requirements, the data frame that meets the command interface timing is sent to the memory command layer; at the same time, the storage link layer sequentially analyzes the command interface timing after parsing the frame format, decoding and extracting, The decoded command interface timing sequence is obtained, and the decoded command interface timing sequence is sent to the user logic layer. 5.如权利要求2所述的一种基于全固态半导体存储器阵列的雷达数字信号处理装置，其特征在于，所述用户逻辑分别用于获取寄存器配置命令、用户逻辑工作时所需系统时钟和用户逻辑全局复位信号、操作指令和数据流、用户逻辑所需数据格式的操作命令，以及当前时刻物理层、介质接口层、存储器命令层、存储链路层、存储器维护和配置单元、基础设施以及用户逻辑层各自工作状态；所述操作指令包含存储指令、读取指令、擦除指令、初始化指令和功能配置操作指令；5. A radar digital signal processing device based on an all-solid-state semiconductor memory array as claimed in claim 2, wherein the user logic is used to obtain a register configuration command, a system clock required when the user logic works, and a user logic. Logic global reset signal, operation command and data flow, operation command in data format required by user logic, and physical layer, media interface layer, memory command layer, storage link layer, memory maintenance and configuration unit, infrastructure and user at the current moment The respective working states of the logic layers; the operation instructions include storage instructions, read instructions, erase instructions, initialization instructions and function configuration operation instructions; 所述存储器维护和配置单元用于获取用户逻辑发送过来的寄存器配置命令，然后解析所述寄存器配置命令，得到解析后的寄存器配置命令，并将解析后的寄存器配置命令分别发送至物理层、介质接口层、存储器命令层和存储链路层；同时存储器维护和配置单元用于分别读取物理层、介质接口层、存储器命令层和存储链路层各自对应的寄存器配置命令，并发送至用户逻辑；The memory maintenance and configuration unit is used to obtain the register configuration command sent by the user logic, then parse the register configuration command to obtain the parsed register configuration command, and send the parsed register configuration command to the physical layer and the medium respectively. Interface layer, memory command layer, and storage link layer; at the same time, the memory maintenance and configuration unit is used to read the corresponding register configuration commands of the physical layer, media interface layer, memory command layer, and storage link layer, and send them to the user logic. ; 所述基础设施获取用户逻辑工作时所需系统时钟和用户逻辑全局复位信号，然后对所述用户逻辑工作时所需系统时钟和用户逻辑全局复位信号依次进行锁相环、时钟扇出以及复位同步操作，获得多个工作时钟和与多个工作时钟分别同步的工作复位信号，并将多个工作时钟和与多个工作时钟分别同步的工作复位信号分别发送至物理层、介质接口层、存储器命令层、存储链路层、存储器维护和配置单元；同时，将多个工作时钟和与多个工作时钟分别同步的工作复位信号输出至用户逻辑。The infrastructure obtains the system clock and the user logic global reset signal required when the user logic works, and then performs phase-locked loop, clock fan-out and reset synchronization on the system clock and the user logic global reset signal required when the user logic works. operation, obtain multiple working clocks and working reset signals that are synchronized with multiple working clocks, and send multiple working clocks and working reset signals synchronized with multiple working clocks to the physical layer, media interface layer, and memory commands respectively. layer, storage link layer, memory maintenance and configuration unit; at the same time, multiple working clocks and working reset signals synchronized with multiple working clocks are output to user logic. 6.如权利要求2所述的一种基于全固态半导体存储器阵列的雷达数字信号处理装置，其特征在于，所述状态采集单元用于获取当前时刻物理层、介质接口层、存储器命令层、存储链路层、存储器维护和配置单元、基础设施以及用户应用逻辑层各自工作状态，并通过状态接口将当前时刻物理层、介质接口层、存储器命令层、存储链路层、存储器维护和配置单元、基础设施以及用户逻辑层各自工作状态发送至用户逻辑；6. A radar digital signal processing device based on an all-solid-state semiconductor memory array according to claim 2, wherein the state acquisition unit is used to obtain the physical layer, media interface layer, memory command layer, storage The link layer, memory maintenance and configuration unit, infrastructure and user application logic layer have their respective working states, and through the state interface, the physical layer, media interface layer, memory command layer, memory link layer, memory maintenance and configuration unit, The respective working states of the infrastructure and user logic layers are sent to the user logic; 所述用户逻辑层用于获取用户逻辑发送过来的操作指令和数据流，并组织成存储器控制接口所需数据格式和操作格式，然后发送至存储链路层；同时所述存储链路层从用户逻辑获取Nand Flash存储器阵列所能识别的操作命令，所述Nand Flash存储器阵列所能识别的操作命令包括存储、读取、功能配置操作、直接存储访问写入、直接存储访问读取、可编程输入输出写入、可编程输入输出读取、批量擦除、简单擦除或初始化操作命令，并对所述Nand Flash存储器阵列所能识别的操作命令依次进行解析和重构，得到用户逻辑所需数据格式的操作命令，再将所述用户逻辑所需数据格式的操作命令发送至用户逻辑。The user logic layer is used to obtain the operation instructions and data streams sent by the user logic, organize them into data formats and operation formats required by the memory control interface, and then send them to the storage link layer; The logic obtains the operation commands that can be recognized by the Nand Flash memory array, and the operation commands that can be recognized by the Nand Flash memory array include storage, read, function configuration operation, direct storage access write, direct storage access read, programmable input Output write, programmable input and output read, batch erase, simple erase or initialization operation commands, and sequentially analyze and reconstruct the operation commands that can be recognized by the Nand Flash memory array to obtain the data required by the user logic The operation command in the format, and then the operation command in the data format required by the user logic is sent to the user logic. 7.如权利要求1所述的一种基于全固态半导体存储器阵列的雷达数字信号处理装置，其特征在于，所述PCIe控制器包含物理层、链路层和传输层，所述传输层包含寄存器文件、直接内存访问控制器、电源管理；物理层和链路层分别通过Xilinx提供的IP完成各自功能；传输层提供两个双向端口，分别为用户寄存器端口和直接内存访问端口，其中程序输出/输入传输时，用户通过用户寄存器端口访问寄存器文件时，寄存器文件通过PCIe协议透明映射到主控计算机中的存储区域进行读取；直接内存访问端口通过DMA控制器完成大批量数据收发工作；用户数据由直接内存访问端口进入PCIe总线控制器，依次经过DMA控制器、链路层和物理层按照PCIe协议进行封装，得到通信数据，并经过PCIe总线发送至主控计算机；同时主控计算机经过PCIe总线下发通信数据，经过物理层、链路层和传输层依次进行解封装，得到用户数据，并将用户数据通过直接内存访问端口送出；所述电源管理为电源管理模块，用于为PCIe总线控制器供电。7. A radar digital signal processing device based on an all-solid-state semiconductor memory array according to claim 1, wherein the PCIe controller comprises a physical layer, a link layer and a transport layer, and the transport layer comprises a register File, direct memory access controller, power management; the physical layer and link layer complete their respective functions through the IP provided by Xilinx; the transport layer provides two bidirectional ports, namely the user register port and the direct memory access port, where the program output / During input transmission, when the user accesses the register file through the user register port, the register file is transparently mapped to the storage area in the host computer through the PCIe protocol for reading; the direct memory access port completes the bulk data sending and receiving work through the DMA controller; user data Enter the PCIe bus controller from the direct memory access port, and encapsulate it according to the PCIe protocol through the DMA controller, the link layer and the physical layer in turn to obtain the communication data, and send it to the main control computer through the PCIe bus; at the same time, the main control computer passes through the PCIe bus. The communication data is delivered, decapsulated in sequence through the physical layer, the link layer and the transmission layer to obtain user data, and the user data is sent through the direct memory access port; the power management is a power management module, which is used for PCIe bus control power supply. 8.如权利要求1所述的一种基于全固态半导体存储器阵列的雷达数字信号处理装置，其特征在于，所述SRIO控制器包含用户逻辑、直接内存访问控制器、传输层、链路层、物理层、基础设施；用户逻辑将数据发送到DMA控制器，经过直接内存访问控制器封装之后再按SRIO协议依次经过传输层、链路层和物理层进行封装，得到最终封装完成的数据，并将最终封装完成的数据按照SRIO协议通过SRIO链路发送；同时接收SRIO链路上的数据，并依次经过物理层、链路层和传输层解封装后输出给用户逻辑。8. A radar digital signal processing device based on an all-solid-state semiconductor memory array according to claim 1, wherein the SRIO controller comprises user logic, direct memory access controller, transport layer, link layer, Physical layer, infrastructure; the user logic sends data to the DMA controller, and then encapsulates it through the direct memory access controller, and then encapsulates it through the transport layer, link layer, and physical layer according to the SRIO protocol to obtain the final encapsulated data. The final encapsulated data is sent through the SRIO link according to the SRIO protocol; at the same time, the data on the SRIO link is received, and then decapsulated through the physical layer, the link layer and the transport layer in turn, and then output to the user logic.
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