CN105955385A - High pressure resistant linear voltage regulator based on standard CMOS technology - Google Patents
High pressure resistant linear voltage regulator based on standard CMOS technology Download PDFInfo
- Publication number
- CN105955385A CN105955385A CN201610293842.XA CN201610293842A CN105955385A CN 105955385 A CN105955385 A CN 105955385A CN 201610293842 A CN201610293842 A CN 201610293842A CN 105955385 A CN105955385 A CN 105955385A
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- pmos transistor
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- high pressure
- voltage regulator
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- 238000000034 method Methods 0.000 claims description 19
- 239000013078 crystal Substances 0.000 claims description 3
- 239000003381 stabilizer Substances 0.000 abstract 2
- 239000000758 substrate Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
The invention discloses a high pressure resistant linear voltage regulator which is based on standard CMOS technology and is applied in power supply systems. The linear voltage regulator comprises a pre-voltage stabilizer, a band gap amplifier, a driver and a feedback unit wherein the pre-voltage stabilizer generates stable voltage for powering the band gap amplifier according to input voltage; the band gap amplifier outputs drive signals according to feedback signals; the driver generates output voltage according to the input voltage when the drive signals are received; the feedback unit outputs feedback signals according to the output voltage; the driver comprises N PMOS transistors of the standard CMOS technology, and the N PMOS transistors are in series connection successively; the band gap amplifier performs drive control on grid voltage of each PMOS transistor, and the input voltage is uniformly distributed to the source end and drain end of the N PMOS transistors, wherein the voltage on each PMOS transistor will not damage the PMOS transistor, and N is a positive integer more than 1. According to the invention, functions of special linear voltage regulator chips such as 7805 are realized on the standard CMOS and the cost of the complete machine is reduced.
Description
Technical field
The present invention relates to relate to a kind of linear voltage regulator, particularly relate to a kind of based on standard CMOS process
High pressure resistant linear voltage regulator.
Background technology
Linear voltage regulator is the most often used, for an input D/C voltage being converted to
Another relatively low output dc voltage, is such as converted to 1.8V by 5V, powers to multi-power system,
Such as Fig. 1.The conventional linear manostat realized on standard CMOS process, is limited by device is pressure,
The input of 5V voltage can only be born.
In a lot of application, power-supply system is 9V or 12V, it is impossible to the MCU manufactured directly to CMOS technology
Power Deng main control chip, need an extra voltage stabilizing chip (such as 7805) to reduce the voltage to 5V, such as figure
2, thus increase the cost of complete machine.
Summary of the invention
For the problems referred to above, now provide a kind of be intended to cost-effective based on standard CMOS process resistance to
High-voltage linear manostat.
A kind of high pressure resistant linear voltage regulator based on standard CMOS process, including:
Pre-regulator, according to input voltage, produces burning voltage, powers for band gap amplifier；
Band gap amplifier, according to feedback signal, output drive signal；
Driver, when receiving described driving signal, according to input voltage, produces output voltage；
Feedback unit, according to described output voltage, exports described feedback signal；
Described driver includes the PMOS transistor in N number of standard CMOS process；
N number of PMOS transistor is sequentially connected in series, the band gap amplifier grid to each PMOS transistor
Pole tension is driven controlling, and input voltage is uniformly distributed in the source and drain two of N number of PMOS transistor
End, the voltage undertaken needed for each PMOS transistor is unlikely to allow it damage, and N is the most whole more than 1
Number.
Preferably, described linear voltage regulator also includes gate bias circuit；
Described gate bias circuit, according to the driving signal of band gap amplifier, for N number of PMOS transistor
Grid provide bias voltage.
Preferably, described gate bias circuit includes PMOS transistor MP0, N-1 stabilivolt, electricity
Stream source I1 and N number of nmos pass transistor；
First PMOS transistor in the N number of PMOS transistor being connected in series and PMOS crystal
Pipe MP0 constitutes current mirror biasing；Two PMOS transistor being connected in N number of PMOS transistor
Grid between connect respectively a stabilivolt；Current source I1 provides bias current for N-1 stabilivolt；
N number of nmos pass transistor is sequentially connected in series, wherein the drain electrode of first nmos pass transistor with
The drain electrode of described first PMOS transistor and its grid are simultaneously connected with；
The n-th driving signal input extremely N number of nmos pass transistor of series connection of band gap amplifier
The grid of nmos pass transistor.
Preferably, described nmos pass transistor increases by one layer of DNW, compatibility standard CMOS technology.
Preferably, described pre-regulator includes N number of resistance and N stabilivolt；
N number of resistance is sequentially connected in series, and first resistance is additionally operable to access input voltage, n-th resistance
It is additionally operable to be connected with the negative electrode of N stabilivolt, the plus earth of N stabilivolt.
Preferably, before in N number of nmos pass transistor of series connection, the grid of N-1 nmos pass transistor is inclined
Put voltage to obtain in N-1 tap from N number of resistance of pre-regulator respectively.
Preferably, described input voltage is 15V, and the output voltage that described driver produces is 5V, 3.3V
Or 2.5V.
Preferably, the MOS transistor that described stabilivolt all connects with diode realizes.
The beneficial effect of technique scheme:
The function of the special linear voltage stabilization chips such as 7805 is realized on standard CMOS by the present invention, thus
It is desirably integrated in the chip of the low pressure process designs such as MCU.So this type of chip just can directly receive
The high input voltages such as 12V/9V/15V, then reduce complete machine cost.
Accompanying drawing explanation
Fig. 1 is the electrical connection schematic diagram of traditional linear voltage regulator.
Fig. 2 is the principle schematic of traditional power-supply system.
Fig. 3 is the former of based on standard CMOS process the high pressure resistant linear voltage regulator in detailed description of the invention
Reason schematic diagram.
Fig. 4 is the principle schematic of gate bias circuit in detailed description of the invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out
Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the present invention, and
It is not all, of embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art are not making
The every other embodiment obtained on the premise of going out creative work, broadly falls into the scope of protection of the invention.
It should be noted that in the case of not conflicting, the embodiment in the present invention and the spy in embodiment
Levy and can be mutually combined.
The invention will be further described with specific embodiment below in conjunction with the accompanying drawings, but not as the present invention's
Limit.
As it is shown on figure 3, high pressure resistant linear voltage regulator based on standard CMOS process, including:
Pre-regulator, according to input voltage VIN, produce a low precision, the stable electricity of weak driving force
Pressure preg, powers for band gap amplifier；V in present embodimentIN=15V；
Band gap amplifier, according to feedback signal VFB, output drive signal；
Driver, when receiving driving signal, according to input voltage, produces output voltage VOUT；
Feedback unit, according to output voltage VOUT, output feedback signal VFB；
Further, driver includes three PMOS transistor: PMOS transistor MP1, PMOS
Transistor MP2 and PMOS transistor MP3；
PMOS transistor in present embodiment is the PMOS crystal in standard 5V CMOS technology
Pipe, and be four-terminal device, the voltage between any two ends, no more than 5.5V, utilizes this characteristic, PMOS
Transistor MP1, PMOS transistor MP2 and PMOS transistor MP3 are sequentially connected in series, band gap
The grid voltage of each PMOS transistor is driven controlling by amplifier, is divided equably by input voltage
Cloth is unlikely to the voltage undertaken needed for the source and drain two ends of three PMOS transistor, each PMOS transistor
Yu Rangqi damages.
In theory, the series connection of more PMOS transistor just can bear higher input voltage, is finally subject to
Limit is the substrate of PMOS transistor, i.e. NWELL is pressure to silicon substrate back biased diode.
In order to allow PMOS transistor MP1, PMOS transistor MP2 and PMOS transistor MP3
Uniformly sharing high input voltage, the biasing of their grid is crucial.
Further, in present embodiment, linear voltage regulator also includes gate bias circuit；
Such as Fig. 4, gate bias circuit include PMOS transistor MP0, stabilivolt D1, stabilivolt D2,
Current source I1, nmos pass transistor MN1, nmos pass transistor MN2 and nmos pass transistor MN3；
PMOS transistor MP1 and PMOS transistor MP0 constitute current mirror biasing, it is ensured that PMOS
The gate source voltage of transistor MP1 can't see high pressure；The drain electrode of PMOS transistor MP0 is brilliant with NMOS
The drain electrode of body pipe MN1, the negative electrode of stabilivolt D1, the grid of PMOS transistor MP1 and PMOS
The grid of transistor MP0 is simultaneously connected with；
The grid of the anode of stabilivolt D1 and the negative electrode of stabilivolt D2 and PMOS transistor MP2 is simultaneously
Connect；Stabilivolt D1 then provides biasing for PMOS transistor MP2, it is ensured that PMOS transistor MP1
Source and drain and the grid source of PMOS transistor MP2 can't see high pressure；
The current input terminal of the anode of stabilivolt D2 and current source I1 and the grid of PMOS transistor MP3
Pole is simultaneously connected with, and stabilivolt D2 then provides biasing for PMOS transistor MP3, it is ensured that PMOS is brilliant
High pressure is can't see in the source and drain of body pipe MP2 and the grid source of PMOS transistor MP3；The electric current of current source I1
Output head grounding；Current source I1 is bias current, for setting the steady of stabilivolt D1 and stabilivolt D2
Piezoelectricity is pressed near 5V.
Nmos pass transistor MN1, nmos pass transistor MN2 and nmos pass transistor MN3 go here and there successively
Connection connects, and the electric current flowing through PMOS transistor MP0 is controlled nmos pass transistor by band gap amplifier
MN3 adjusts, to complete closed loop control.
Equally, in order to avoid nmos pass transistor MN3 sees high pressure, nmos pass transistor MN1 and
Nmos pass transistor is series at above nmos pass transistor MN3 uniformly shares high pressure.In like manner, NMOS
Transistor is also four-terminal device, and the voltage at any two ends is no more than 5.5V.NMOS must be allowed for this
From silicon substrate independent, these need additionally increase by one layer of DNW (Deep N Well), compatibility standard
CMOS technology.
Further, as shown in Figure 4, pre-regulator includes resistance R1, resistance R2, resistance R3 and steady
Pressure pipe D3；
One end of resistance R1 is used for connecting one end of input voltage, the other end of resistance R1 and resistance R2
Connecting, the other end of resistance R2 is connected with one end of resistance R3, the other end of resistance R3 and stabilivolt
The negative electrode of D3 connects, the plus earth of stabilivolt D3.
Stabilivolt D1, stabilivolt D2 and stabilivolt D3 in present embodiment can also be used with diode and connect
MOS transistor realize.
The grid voltage of nmos pass transistor MN1 and nmos pass transistor MN2 biases from pre-regulator
Resistor tap on obtain, it is not necessary to extra circuits, rationally select the position of tap to realize
Nmos pass transistor MN1, nmos pass transistor MN2 and nmos pass transistor MN3 uniformly share height
The purpose of pressure.
Present embodiment utilizes the 5V device design in standard CMOS chip design technology to achieve 15V
High input voltage, it is adjustable that high input voltage can be converted to stable low pressure 5V/3.3V/2.5V by this linear voltage regulator
Output.
The foregoing is only preferred embodiment of the present invention, not thereby limit embodiments of the present invention and
Protection domain, to those skilled in the art, it should can appreciate that all utilization description of the invention
And the equivalent done by diagramatic content and the scheme obtained by obvious change, all should comprise
Within the scope of the present invention.
Claims (8)
1. a high pressure resistant linear voltage regulator based on standard CMOS process, including:
Pre-regulator, according to input voltage, produces burning voltage, powers for band gap amplifier；
Band gap amplifier, according to feedback signal, output drive signal；
Driver, when receiving described driving signal, according to input voltage, produces output voltage；
Feedback unit, according to described output voltage, exports described feedback signal；
It is characterized in that,
Described driver includes the PMOS transistor in N number of standard CMOS process；
N number of PMOS transistor is sequentially connected in series, the band gap amplifier grid to each PMOS transistor
Pole tension is driven controlling, and input voltage is uniformly distributed in the source and drain two of N number of PMOS transistor
End, the voltage undertaken needed for each PMOS transistor is unlikely to allow it damage, and N is the most whole more than 1
Number.
2. high pressure resistant linear voltage regulator based on standard CMOS process as claimed in claim 1, its
Being characterised by, described linear voltage regulator also includes gate bias circuit；
Described gate bias circuit, according to the driving signal of band gap amplifier, for N number of PMOS transistor
Grid provide bias voltage.
3. high pressure resistant linear voltage regulator based on standard CMOS process as claimed in claim 2, its
Being characterised by, described gate bias circuit includes PMOS transistor MP0, N-1 stabilivolt, electric current
Source I1 and N number of nmos pass transistor；
First PMOS transistor in the N number of PMOS transistor being connected in series and PMOS crystal
Pipe MP0 constitutes current mirror biasing；Two PMOS transistor being connected in N number of PMOS transistor
Grid between connect respectively a stabilivolt；Current source I1 provides bias current for N-1 stabilivolt；
N number of nmos pass transistor is sequentially connected in series, wherein the drain electrode of first nmos pass transistor with
The drain electrode of described first PMOS transistor and its grid are simultaneously connected with；
The n-th driving signal input extremely N number of nmos pass transistor of series connection of band gap amplifier
The grid of nmos pass transistor.
4. high pressure resistant linear voltage regulator based on standard CMOS process as claimed in claim 3, its
Being characterised by, described nmos pass transistor increases by one layer of DNW, compatibility standard CMOS technology.
5. based on standard CMOS process the high pressure resistant linear voltage regulator as described in claim 3 or 4,
It is characterized in that, described pre-regulator includes N number of resistance and N stabilivolt；
N number of resistance is sequentially connected in series, and first resistance is additionally operable to access input voltage, n-th resistance
It is additionally operable to be connected with the negative electrode of N stabilivolt, the plus earth of N stabilivolt.
6. high pressure resistant linear voltage regulator based on standard CMOS process as claimed in claim 5, its
It is characterised by, the gate bias of front N-1 nmos pass transistor in N number of nmos pass transistor of series connection
Voltage obtains in N-1 tap respectively from N number of resistance of pre-regulator.
7. high pressure resistant linear voltage regulator based on standard CMOS process as claimed in claim 6, its
Being characterised by, described input voltage is 15V, and the output voltage that described driver produces is 5V, 3.3V
Or 2.5V.
8. high pressure resistant linear voltage regulator based on standard CMOS process as claimed in claim 5, its
Being characterised by, the MOS transistor that described stabilivolt all connects with diode realizes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610293842.XA CN105955385B (en) | 2016-05-05 | 2016-05-05 | High pressure resistant linear voltage regulator based on standard CMOS process |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610293842.XA CN105955385B (en) | 2016-05-05 | 2016-05-05 | High pressure resistant linear voltage regulator based on standard CMOS process |
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| CN105955385A true CN105955385A (en) | 2016-09-21 |
| CN105955385B CN105955385B (en) | 2017-07-28 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104821816A (en) * | 2015-05-21 | 2015-08-05 | 苏州锴威特半导体有限公司 | Level shift circuit for half-bridge drive |
| CN109814648A (en) * | 2018-12-27 | 2019-05-28 | 西安紫光国芯半导体有限公司 | A kind of linear voltage regulator and linear voltage stabilization method suitable for hyperbaric environment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060119335A1 (en) * | 2004-12-03 | 2006-06-08 | Dialog Semiconductor Gmbh | Voltage regulator output stage with low voltage MOS devices |
| US20110050318A1 (en) * | 2009-08-26 | 2011-03-03 | Alfred E. Mann Foundation For Scientific Research | High voltage differential pair and op amp in low voltage process |
| CN103516350A (en) * | 2012-06-27 | 2014-01-15 | 三星电子株式会社 | Output driver and data output driving circuit using the same |
| CN104881070A (en) * | 2014-02-27 | 2015-09-02 | 无锡华润上华半导体有限公司 | Ultra-low power consumption LDO circuit applied to MEMS |
| CN205608579U (en) * | 2016-05-05 | 2016-09-28 | 上海铄梵电子科技有限公司 | High pressure resistant linear voltage regulator based on standard CMOS technology |
-
2016
- 2016-05-05 CN CN201610293842.XA patent/CN105955385B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060119335A1 (en) * | 2004-12-03 | 2006-06-08 | Dialog Semiconductor Gmbh | Voltage regulator output stage with low voltage MOS devices |
| US20110050318A1 (en) * | 2009-08-26 | 2011-03-03 | Alfred E. Mann Foundation For Scientific Research | High voltage differential pair and op amp in low voltage process |
| CN103516350A (en) * | 2012-06-27 | 2014-01-15 | 三星电子株式会社 | Output driver and data output driving circuit using the same |
| CN104881070A (en) * | 2014-02-27 | 2015-09-02 | 无锡华润上华半导体有限公司 | Ultra-low power consumption LDO circuit applied to MEMS |
| CN205608579U (en) * | 2016-05-05 | 2016-09-28 | 上海铄梵电子科技有限公司 | High pressure resistant linear voltage regulator based on standard CMOS technology |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104821816A (en) * | 2015-05-21 | 2015-08-05 | 苏州锴威特半导体有限公司 | Level shift circuit for half-bridge drive |
| CN109814648A (en) * | 2018-12-27 | 2019-05-28 | 西安紫光国芯半导体有限公司 | A kind of linear voltage regulator and linear voltage stabilization method suitable for hyperbaric environment |
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| Publication number | Publication date |
|---|---|
| CN105955385B (en) | 2017-07-28 |
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Effective date of registration: 20210402 Address after: 201600 room 404, room 1, No.10 Shanxi Road, Xiaokunshan Town, Songjiang District, Shanghai Patentee after: SHANGHAI HOLYCHIP ELECTRONIC Co.,Ltd. Address before: 201611 room 2404, room 1, No.10 Shanxi Road, Xiaokunshan Town, Songjiang District, Shanghai Patentee before: SHANGHAI SOVAN ELECTRONIC TECHNOLOGY Co.,Ltd. |
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