CN105939107A - A Hybrid Quasi-Switching Boost DC-DC Converter - Google Patents

Abstract

The present invention provides a hybrid quasi-switch boost DC-DC converter circuit, comprising a voltage source, a two-terminal quasi-Z source unit consisting of a first inductor, a first diode, a first capacitor, a second inductor and a second capacitor, a quasi-switch boost unit consisting of a second capacitor, a second diode, a first MOS transistor, a first diode and a second inductor, a switch capacitor unit consisting of a third capacitor and a third diode, a second MOS transistor, an output diode, an output filter capacitor and a load. The present invention has a simple circuit structure, combines the single-stage buck-boost characteristics of the quasi-Z source unit and the quasi-switch boost unit and the characteristics of parallel charging and series discharging of the switch capacitor, and realizes the improvement of the output voltage gain.

Description

A Hybrid Quasi-Switching Boost DC-DC Converter

technical field

The invention relates to the technical field of power electronic circuits, in particular to a hybrid high-gain quasi-switch boost DC-DC converter circuit combined with a switched capacitor and a quasi-Z source unit.

Background technique

In fuel cell power generation and photovoltaic power generation, due to the low DC voltage provided by a single solar cell or a single fuel cell, it cannot meet the electricity demand of existing electrical equipment, nor can it meet the needs of grid connection. It is often necessary to combine multiple batteries connected in series to achieve the desired voltage. On the one hand, this method greatly reduces the reliability of the entire system, and on the other hand, it needs to solve the problem of series voltage equalization. For this reason, a high-gain DC-DC converter capable of converting low voltage to high voltage is required. The Z-source converter and switching boost converter SBI proposed in recent years are both high-gain DC-DC converters, but in some occasions where a low-voltage input is expected to have a higher voltage output, the traditional Z-source converter and SBI The converter becomes no longer adequate. In order to expand the application range of traditional Z-source converters and SBI converters, it is necessary to expand their output voltage gain through topology improvement.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the above-mentioned prior art, and provides a hybrid high-gain quasi-switch boost DC-DC converter circuit combined with a switched capacitor and a quasi-Z source unit. The specific technical scheme is as follows.

A hybrid quasi-switch boost DC-DC converter circuit includes a voltage source, a quasi-Z source unit, a quasi-switch boost unit, a second MOS transistor, a switched capacitor unit, an output diode, an output filter capacitor and a load. The quasi-Z source unit is composed of a first inductance, a first capacitor, a first diode, a second inductance and a second capacitor; the quasi-switch boost unit is composed of a second inductance, a first diode, a second The capacitor, the first MOS transistor and the second diode; the switched capacitor unit is composed of the third capacitor and the third diode.

In the aforementioned hybrid quasi-switching step-up DC-DC converter circuit, the positive pole of the voltage source is respectively connected to the negative pole of the second capacitor and one end of the first inductance; the other end of the first inductance is respectively connected to the first The anode of a diode is connected to the cathode of the first capacitor; the anode of the second capacitor is respectively connected to the cathode of the second diode, the anode of the output diode and the drain of the first MOS transistor; the first two The cathode of the pole tube is respectively connected to one end of the second inductor and the source of the first MOS tube; the anode of the first capacitor is respectively connected to the anode of the second diode, the other end of the second inductor, and the source of the second MOS tube. The drain is connected to the positive pole of the third capacitor; the cathode of the output diode is respectively connected to the positive pole of the output filter capacitor and the other end of the load; the negative pole of the third capacitor is respectively connected to the anode of the third diode and the output filter capacitor The cathode of the voltage source is connected to the other end of the load; the cathode of the voltage source is respectively connected to the source of the second MOS transistor and the cathode of the third diode.

When the first MOS transistor and the second MOS transistor are turned on at the same time, the first diode, the second diode, and the third diode are all turned off, and the voltage source and the first capacitor charge the first inductor; The voltage source and the second capacitor charge the second inductor; meanwhile, the voltage source together with the third capacitor and the second capacitor supplies power to the output filter capacitor and the load. When the first MOS transistor and the second MOS transistor are turned off simultaneously, the first diode, the second diode and the third diode are all turned on, and the output diode is turned off. The second inductance is connected in parallel with the first capacitor to form a loop; the first inductance and the second inductance charge the second capacitor together; the voltage source, the first inductance and the second inductance charge the third capacitor; meanwhile, The output filter capacitor supplies power to the load.

Compared with the prior art, the circuit of the present invention has the following advantages and technical effects: the whole circuit of the present invention has simple structure, convenient control, and higher output voltage gain; the circuit of the present invention utilizes a single The step-up and step-down characteristics and the parallel charging and series discharging characteristics of the switched capacitors further increase the output voltage and realize the expansion of the output voltage gain of the quasi-switching boost converter.

Description of drawings

FIG. 1 is a hybrid quasi-switching step-up DC-DC converter circuit in a specific embodiment of the present invention.

Fig. 2a and Fig. 2b respectively show a kind of hybrid high-gain quasi-switching step-up DC-DC converter circuit combined with switched capacitor and quasi-Z source unit shown in Fig. ₁ in its first switch tube S1 and second switch tube S ₂ Equivalent circuit diagram for simultaneous on and simultaneous off periods.

Fig. 3a is a graph comparing the gain curve of the circuit of the present invention with the gain curves of Boost converter, switched capacitor Boost converter, traditional Z-source DC-DC converter and new quasi-Z source DC-DC converter.

Fig. 3 b is the gain curve of the circuit of the present invention in Fig. 3 a and the gain curve of Boost converter, switched capacitor Boost converter, traditional Z source DC-DC converter and novel quasi-Z source DC-DC converter when duty ratio D is less than Comparison plot within 0.38.

detailed description

The technical solution of the present invention has been described in detail above, and the specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

Referring to Fig. 1, a hybrid quasi-switch boost DC-DC converter circuit according to the present invention includes a voltage source, a quasi-Z source unit, a quasi-switch boost unit, a second MOS transistor, a switched capacitor unit, and an output diode , output filter capacitor and load. The quasi-Z source unit is composed of a first inductance, a first capacitor, a first diode, a second inductance and a second capacitor; the quasi-switch boost unit is composed of a second inductance, a first diode, a second The capacitor, the first MOS transistor and the second diode; the switched capacitor unit is composed of the third capacitor and the third diode.

The specific connection mode of the circuit of the present invention is as follows: the positive pole of the voltage source is respectively connected with the negative pole of the second capacitor and one end of the first inductance; the other end of the first inductance is respectively connected with the anode of the first diode and the first The negative electrode of the capacitor is connected; the positive electrode of the second capacitor is respectively connected to the cathode of the second diode, the anode of the output diode and the drain of the first MOS tube; the cathode of the first diode is respectively connected to the second inductor One end of the first MOS transistor is connected to the source; the anode of the first capacitor is respectively connected to the anode of the second diode, the other end of the second inductor, the drain of the second MOS transistor and the positive electrode of the third capacitor The cathode of the output diode is respectively connected to the positive pole of the output filter capacitor and the other end of the load; the negative pole of the third capacitor is respectively connected to the anode of the third diode, the negative pole of the output filter capacitor and the other end of the load; The cathode of the voltage source is respectively connected to the source of the second MOS transistor and the cathode of the third diode.

Fig. 2a and Fig. 2b show the working process diagram of the circuit of the present invention. FIG. 2 a and FIG. 2 b respectively correspond to equivalent circuit diagrams of the periods when the first MOS transistor S ₁ and the second MOS transistor S ₂ are turned on and turned off at the same time. The solid line in the figure indicates the part where current flows in the converter, and the dotted line indicates the part where no current flows in the converter.

Working process of the present invention is as follows:

Stage 1, as shown in Figure 2a: the first MOS transistor S ₁ and the second MOS transistor S ₂ are turned on at the same time, at this time the first diode D ₁ , the second diode D ₂ , and the third diode D ₃ are all off. The circuit forms three loops, respectively: the voltage source V _i charges the output filter capacitor C _f and the load R _L together with the first capacitor C ₁ and the third capacitor C ₃ to form a loop; the voltage source V _i and the first capacitor C ₁ charges and stores energy on the first inductor L ₁ to form a loop; the voltage source V _i and the second capacitor C ₂ charges and stores energy to the second inductor L ₂ to form a loop.

Stage 2, as shown in Figure 2b: the first MOS transistor S ₁ and the second MOS transistor S ₂ are turned off at the same time, at this time the first diode D ₁ , the second diode D ₂ , and the third diode D ₃ are all conduction, the output diode D _o is turned off. The circuit forms four loops, namely: the voltage source V _i , the first inductance L ₁ and the second inductance L ₂ charge and store energy to the third capacitor C ₃ to form a loop; the second inductance L ₂ charges the first capacitor C ₁ charging to form a loop; the first inductance L ₁ and the second inductance L ₂ charge and store energy to the second capacitor C ₂ to form a loop; the output filter capacitor C _f supplies power to the load _RL to form a loop.

In summary, since the switching trigger pulses of the _first MOS transistor S1 and the _second MOS transistor S2 are exactly the same, it is _assumed that the duty ratios of the switching transistors S1 and S2 are _both D, and the switching period is T _s . And set V _L1 and V _L2 to be the voltages across the inductors L ₁ and L ₂ respectively, V _C1 , V _C2 and V _C3 to be the voltages of the first capacitor C ₁ , the second capacitor C ₂ and the third capacitor C ₃ respectively, V _S1 and V _S2 are the voltages between the drain and the source of the _first MOS transistor S1 and the _second MOS transistor S2 respectively. In a switching period T _s , let the output voltage be V _o . When the converter enters the steady-state operation, the following voltage relationship derivation process is obtained.

Working mode 1: the first MOS transistor S ₁ and the second MOS transistor S ₂ are turned on at the same time, and the corresponding equivalent circuit is shown in Figure 2a, so the following formula is given:

V _L1 =V _i +V _C1 (1)

V _L2 =V _i +V _C2 (2)

V _O =V _i +V _C3 +V _C2 (3)

V _S1 =V _S2 =0 (4)

The conduction time of MOS transistors S ₁ and S ₂ is DT _s .

Working mode 2: both the first MOS transistor S ₁ and the second MOS transistor S ₂ are turned off, and the corresponding equivalent circuit is shown in Figure 2b, so the following formula is given:

V _L1 =V _C1 -V _C2 (5)

V _L2 = -V _C1 (6)

V _i =V _C3 -V _C2 (7)

V _S2 = V _C3 (8)

V _S1 = V _C1 (9)

The turn-off time of the MOS transistors S ₁ and S ₂ is (1-D)T _s .

According to the above analysis, the principle of conservation of inductance volt-seconds is applied to the first inductance L1 and the second inductance L2 respectively, and the simultaneous formula (1), formula (5), formula (2) and formula (6) can be obtained:

D(V _i +V _C1 )+(1-D)(V _C1 -V _C2 )＝0 (10)

D(V _i +V _C2 )-(1-D)V _C1 =0 (11)

Therefore, it can be obtained that the relationship between the voltage V _{C1 of the first capacitor C1 and} the voltage V _C2 of the _second capacitor C2 and the voltage source V _i is:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; D.</span>}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 3</span>}\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; D.</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 3</span>}\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; D.</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 13</span>}<span\; class="notranslate">\; )</span>$

From formula (7), formula (12) and formula (13), the relationship between the voltage V _C3 of the _third capacitor C3 and the voltage source V _i can be obtained as:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; D.</span>}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 3</span>}\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; D.</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 14</span>}<span\; class="notranslate">\; )</span>$

Then by formula (3), formula (13) and formula (14), the gain factor expression that can obtain the circuit of the present invention is:

$\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 3</span>}\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; D.</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 15</span>}<span\; class="notranslate">\; )</span>$

As shown in Fig. 3 a, it is the gain curve comparison figure of the gain curve of the circuit of the present invention and Boost converter, switched capacitor Boost converter, traditional Z source DC-DC converter and novel quasi-Z source DC-DC converter; Fig. 3 b is The gain curve of the circuit of the present invention in Fig. 3 a and the gain curve of Boost converter, switched capacitor Boost converter, traditional Z source DC-DC converter and novel quasi-Z source DC-DC converter are less than the difference in duty cycle D within 0.38 Comparison figure, including the gain curve of the circuit of the present invention, the gain curve of the traditional Z source DC-DC converter, the gain curve of the novel quasi-Z source DC-DC converter, the gain curve of the switched capacitor Boost converter, and the Boost converter gain curve. It can be seen from the figure that the gain G of the circuit of the present invention can be very large when the duty ratio D does not exceed 0.38, and the duty ratio D of the circuit of the present invention does not exceed 0.38. Therefore, the gain of the circuit of the present invention is very high in comparison.

In summary, the overall structure of the circuit of the present invention is simple, and the control is convenient. It combines the single-stage buck-boost characteristics of the quasi-Z source unit and the quasi-switch boost unit and the characteristics of parallel charging and series discharge of the switched capacitors, and realizes the output voltage gain. Further improvement, and there is no start-up inrush current and inrush current at the moment when the MOS tube is turned on.

The above-mentioned embodiment is a preferred embodiment of the present invention, but the embodiment of the present invention is not limited by the embodiment, and any other changes, modifications, substitutions and combinations made without departing from the spirit and principle of the present invention , simplification, all should be equivalent replacement methods, and are all included in the protection scope of the present invention.

Claims (3)

1. a mixed type quasi-boost switching DC-DC converter circuit, it is characterised in that include voltage source (V_i), quasi-Z source unit, quasi-boost switching unit, the second metal-oxide-semiconductor (S₂), switching capacity unit, output diode (D_o), output filter capacitor (C_f) and load (R_L)；Described quasi-Z source unit is by the first inductance (L₁), the first electric capacity (C₁), the first diode (D₁), the second inductance (L₂) and the second electric capacity (C₂) constitute；Described quasi-boost switching unit is by the second inductance (L₂), the first diode (D₁), the second electric capacity (C₂), the first metal-oxide-semiconductor (S₁) and the second diode (D₂) constitute；Described switching capacity unit is by the 3rd electric capacity (C₃) and the 3rd diode (D₃) constitute.

A kind of mixed type quasi-boost switching DC-DC converter circuit the most according to claim 1, it is characterised in that described voltage source (V_i) positive pole respectively with the second electric capacity (C₂) negative pole and the first inductance (L₁) one end connect；Described first inductance (L₁) the other end respectively with the first diode (D₁) anode and the first electric capacity (C₁) negative pole connect；Described second electric capacity (C₂) positive pole respectively with the second diode (D₂) negative electrode, output diode (D_o) anode and the first metal-oxide-semiconductor (S₁) drain electrode connect；Described first diode (D₁) negative electrode respectively with the second inductance (L₂) one end and the first metal-oxide-semiconductor (S₁) source electrode connect；Described first electric capacity (C₁) positive pole respectively with the second diode (D₂) anode, the second inductance (L₂) the other end, the second metal-oxide-semiconductor (S₂) drain electrode and the 3rd electric capacity (C₃) positive pole connect；Described output diode (D_o) negative electrode respectively with output filter capacitor (C_f) positive pole and load (R_L) the other end connect；Described 3rd electric capacity (C₃) negative pole respectively with the 3rd diode (D₃) anode, output filter capacitor (C_f) negative pole and load (R_L) the other end connect；Described voltage source (V_i) negative pole respectively with the second metal-oxide-semiconductor (S₂) source electrode, the 3rd diode (D₃) negative electrode connect.

A kind of mixed type quasi-boost switching DC-DC converter circuit the most according to claim 1, it is characterised in that as the first metal-oxide-semiconductor (S₁) and the second metal-oxide-semiconductor (S₂) when simultaneously turning on, described first diode (D₁), the second diode (D₂), the 3rd diode (D₃) be turned off, voltage source (V_i) and the first electric capacity (C₁) to the first inductance (L₁) charging；Voltage source (V_i) and the second electric capacity (C₂) to the second inductance (L₂) charging；Meanwhile, voltage source (V_i) and the 3rd electric capacity (C₃) and the second electric capacity (C₂) together to output filter capacitor (C_f) and load (R_L) power supply；As the first metal-oxide-semiconductor (S₁) and the second metal-oxide-semiconductor (S₂) when simultaneously turning off, described first diode (D₁), the second diode (D₂), the 3rd diode (D₃) be both turned on, output diode (D_o) turn off；Described second inductance (L₂) and the first electric capacity (C₁) in parallel, form loop；Described first inductance (L₁) and the second inductance (L₂) together to the second electric capacity (C₂) charging；Described voltage source (V_i), the first inductance (L₁) and the second inductance (L₂) give the 3rd electric capacity (C₃) charging；Meanwhile, output filter capacitor (C_f) give load (R_L) power supply.