CN105931998A - Insulating substrate structure and power module employing insulating substrate - Google Patents
Insulating substrate structure and power module employing insulating substrate Download PDFInfo
- Publication number
- CN105931998A CN105931998A CN201610435605.2A CN201610435605A CN105931998A CN 105931998 A CN105931998 A CN 105931998A CN 201610435605 A CN201610435605 A CN 201610435605A CN 105931998 A CN105931998 A CN 105931998A
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- Prior art keywords
- brachium pontis
- insulated substrate
- lower brachium
- chip unit
- metal level
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Power Conversion In General (AREA)
- Inverter Devices (AREA)
Abstract
The invention discloses an insulating substrate structure and a power module employing an insulating substrate. The insulating substrate comprises a ceramic insulating layer and a metal layer, wherein the metal layer is formed on the ceramic insulating layer and comprises an upper bridge arm metal layer and a lower bridge arm metal layer; an upper bridge arm chip unit is arranged on the upper bridge arm metal layer; a lower bridge arm chip unit is arranged on the lower bridge arm metal layer; the lower bridge arm metal layer comprises a wiring area; the upper bridge arm chip unit is connected with the wiring area through a bonding wire; and the lower bridge arm metal layer is provided with an insulated balance tank between the wiring area and the lower bridge arm chip unit. By the insulating substrate structure, a power device close to a DC input terminal can be protected; the risk of burn-out of the device caused by an overload is reduced; and parasitic parameters, especially parasitic inductance and loop resistance, of parallel devices are balanced, so that the current-sharing effect is reached; burn-out of certain devices caused by an over-current is avoided; and the reliability of the power module is improved.
Description
Technical field
The present invention relates to power semiconductor modular, particularly relate to a kind of insulated substrate structure and use the power mould of this substrate
Block.
Background technology
It is energy-conservation that global energy crisis and the threat of climate warming allow people increasingly pay attention to while pursuing economic development
Reduction of discharging, low carbon development.Along with environmental protection establishment in the world and propelling, the development of power semiconductor, application prospect are more
Wide.
The power grade of current power module improves constantly, although the electric current of power device, electric pressure constantly carry now
Rise, but single power device still cannot meet the demand of high-power converter, then power model internal components and be unified into
For a kind of inevitable choice, and the equal flow problem of multiple devices of parallel connection highlights the most therewith.The all half-bridges of existing power model are tied
Structure connects two DC input terminal jointly, and owing to power device is different, often at the location layout within power model
The parasitic parameter causing multiple devices in parallel is inconsistent.Operationally, parasitic parameter difference can cause devices in parallel to power model
The electric current passed through is inconsistent, and the chip bigger by electric current burns inefficacy it is possible that cross stream, even if not causing stream to burn
Ruin, the loss of this chip also can bigger, heating ratio is more serious, for a long time the reliability of the most such power model also can be affected.
Summary of the invention
Goal of the invention: the defect existed for above-mentioned prior art, it is desirable to provide one to improve parallel chip equal
The insulated substrate structure of fluidity and use the power model of this substrate, the parasitic parameter of equilibrium parallel chip, improves power model
Reliability.
Technical scheme: a kind of insulated substrate structure, including ceramic insulating layer and be formed at the gold on this ceramic insulating layer
Belonging to layer, described metal level includes brachium pontis metal level and lower brachium pontis metal level, and upper brachium pontis metal level is provided with brachium pontis chip list
Unit, lower brachium pontis metal level is provided with lower brachium pontis chip unit, and lower brachium pontis metal level includes Wiring area, upper brachium pontis chip unit with connect
Line district is connected by bonding line, and lower brachium pontis metal level is provided with the equalizing tank of insulation between Wiring area and lower brachium pontis chip unit.
Further, described equalizing tank originates in the edge of lower brachium pontis metal level near DC input terminal, to away from
The direction of DC input terminal extends.
Further, the bearing of trend of described equalizing tank is vertical with the bonding direction of bonding line.
Further, described lower brachium pontis chip unit includes the power device of multiple parallel connection, the shortest extension of described equalizing tank
To the most concordant with the top of first power device, the longest extend to concordant with the top of last power device.
Further, described equalizing tank is single hop insulation tank or multistage insulation tank.
Further, the material of described upper brachium pontis chip unit is one or more in Si, SiC and GaN, lower brachium pontis core
The material of blade unit is one or more in Si, SiC and GaN.
Further, the chip type of described upper brachium pontis chip unit is the one in IGBT, MOSFET and FRD or many
Kind, the chip type of lower brachium pontis chip unit is one or more in IGBT, MOSFET and FRD.
A kind of power model, uses any of the above-described kind of insulated substrate structure.
Further, including DC input terminal, lead-out terminal and the half-bridge structure of multiple parallel connection, half-bridge structure includes absolutely
Chip set on edge substrate and insulated substrate, each half-bridge structure connects two DC input terminal and an output respectively
Son, the lower brachium pontis metal level of at least one insulated substrate is provided with the equilibrium of insulation between Wiring area with lower brachium pontis chip unit
Groove.
Further, including tactic three half-bridge structures, each half-bridge structure includes an insulated substrate, is positioned at
Its lower brachium pontis metal level of a middle insulated substrate is provided with the equalizing tank of insulation between Wiring area and lower brachium pontis chip unit.
Further, including three transversely arranged half-bridge structures, each half-bridge structure includes two of longitudinal arrangement absolutely
Edge substrate, its lower brachium pontis metal level of three insulated substrates of a line of close DC input terminal is at Wiring area and lower brachium pontis chip list
The equalizing tank of insulation it is equipped with between unit.
Further, including two half-bridge structures, each half-bridge structure includes an insulated substrate, each insulated substrate its
Lower brachium pontis metal level is equipped with the equalizing tank of insulation between Wiring area and lower brachium pontis chip unit.
Beneficial effect: the present invention is provided with equalizing tank on insulated substrate, it is possible to protection is near the power of DC input terminal
Device, reduces the risk that device burns because of overload；Additionally, the power model of the present invention makes half-bridge structure direct-flow input end each other
Independent, decrease input resistance, it is simple to the installation of wave filter.It is defeated that the present invention uses each half-bridge structure to connect two direct currents respectively
Enter terminal and the structure of a lead-out terminal, it is to avoid it is defeated that all half-bridge structures of existing power model connect two direct currents jointly
Enter terminal, protect the power device near DC input terminal, solve distance DC input terminal half-bridge structure farther out
Input resistance bigger than normal and cannot the problem of separately installed filter capacitor.The present invention has equalized the parasitic parameter of devices in parallel,
Especially stray inductance and loop resistance, thus reach the effect of current-sharing, reduce the risk that device burns because of overload, improve
The reliability of power model.
Accompanying drawing explanation
Fig. 1 is the structural representation of insulated substrate of the present invention；
Fig. 2 (a), Fig. 2 (b), Fig. 2 (c) are three kinds of different insulated substrate structural representations；
The stray inductance comparison diagram that the insulated substrate that Fig. 3 is different extracts；
Fig. 4 is MOSFET three-phase bridge power model schematic diagram；
Fig. 5 is three-phase bridge MOSFET power model electrical structure topological diagram；
Fig. 6 is MOSFET power model schematic diagram；
Fig. 7 is the electrical structure topological diagram of embodiment 3；
Fig. 8 is IGBT three-phase bridge power model schematic diagram.
Detailed description of the invention
Below in conjunction with the accompanying drawings the technical program is described in detail.
Embodiment 1:
A kind of insulated substrate structure, and use the power model of this structure, insulated substrate structure is as it is shown in figure 1, include pottery
Porcelain insulating layer and be formed at the metal level on this ceramic insulating layer, the material of metal level uses copper or aluminium, and surface is coated with nickel
With golden or nickel and silver, metal level is realized by thick film printing technique or soldering tech, and thickness is 0.1mm-1mm.
Metal level includes brachium pontis metal level 1 and lower brachium pontis metal level 2, and upper brachium pontis metal level 1 sinters or is welded with
Brachium pontis chip unit 3, lower brachium pontis metal level 2 sinters or is welded with lower brachium pontis chip unit 4, and lower brachium pontis metal level 2 includes connecing
Line district 5, upper brachium pontis chip unit 3 is connected by bonding line 6 with Wiring area 5, and alleged bonding line 6 is all English bonding below
Translation, Wiring area 5 is as it can be seen, nation's line of i.e. going up brachium pontis chip unit 3 is connected to lower brachium pontis chip unit 4 place insulation base
Region on plate, generally nation's line of this area is the horizontally-parallel arrangement shown in figure, Wiring area 5 i.e. these nation's lines with
The region that the set of the contact point of lower brachium pontis chip is formed, lower brachium pontis metal level 2 is at Wiring area 5 and lower brachium pontis chip unit 4
Between be provided with the equalizing tank 7 realizing electrically equilibrium purpose insulation, equalizing tank 7 is that metal level passes through the technique of etching and formed.
The voltage of power model, current class improve constantly, but one single chip often cannot meet requirement, the most each bridge
Arm is typically to be carried out parallel connection by multiple chips.In the present embodiment, a brachium pontis is composed in parallel by 7 power devices, such as institute in Fig. 1
Show, 7 power device groups of upper and lower bridge arm total order from top to bottom arrangement, that is 7 power device groups of 7 dotted line frames in figure.
The generally power device close to direct-flow input end position is easiest to lose efficacy, reason be the stray inductance in this power device loop
Little, in order to equalize the stray inductance in parallel chip loop, now devise two kinds of insulated substrate structures to improve the equal of parallel chip
Stream, equalizing tank 7, as a measure of regulation parasitic parameter, can balance the stray inductance between chipset, but unsuitable long,
Reason is that equalizing tank 7 increases loop resistance, can increase the quiescent dissipation of power model accordingly.
The width of equalizing tank 7 is the most consistent with the insulation tank width of insulating metal substrate upper surface layers of copper, for 0.6-
1.2mm, lower brachium pontis chip unit 4 includes that the power device of multiple parallel connection, equalizing tank 7 originate near DC input terminal 8
The edge of lower brachium pontis metal level 2, extends to the direction away from DC input terminal 8, the shortest extends to and first power device
Top concordant, the longest extend to concordant with the top of last power device, described herein power device top be with
Insulated substrate putting position shown in figure be reference, i.e. insulated substrate be top near one end of DC input terminal 8, if
The placing direction of insulated substrate becomes, and aforesaid " top " still keeps, with one end of close DC input terminal 8 for top, not regarded
Angle and the restriction of placing direction；Further, 7 power device longitudinally order arrangements in the present embodiment, if in other embodiments,
Multiple power devices do not form a line, but in matrix or other modes are arranged, the most aforementioned " the longest extends to and last merit
The top of rate device is concordant " in " last power device " refer near Wiring area 5 one row in distance direct current defeated
Enter the power device that terminal 8 is farthest.
The optimization length of equalizing tank 7 is relevant with chip position and quantity, and equalizing tank 7 be single hop insulation tank or multistage exhausted
Edge groove.Combining concrete power model in the present embodiment to test, Fig. 2 (a) is the insulated substrate of prior art, without the most all
The equalizing tank 7 of weighing apparatus purpose, the insulated substrate of Fig. 2 (b) has the equalizing tank 7 of an electric equilibrium purpose；Its equalizing tank 7 extend to by
Near concordant with the base of second power device of lower brachium pontis；The insulated substrate of Fig. 2 (c) has that one is long and the other is short two electric equilibrium mesh
Equalizing tank 7, long equalizing tank 7 extends to nearly concordant with the base of the power device of second lower brachium pontis from top, short all
The length of weighing apparatus groove 7 is less than the length of first equalizing tank 7, and short equalizing tank 7 prolongs from the top of the 3rd of lower brachium pontis the power device
Extend the medium position of the 3rd power device of lower brachium pontis.
In order to verify the effect of the electrically equalizing tank 7 of equilibrium purpose, now above-mentioned three kinds of insulated substrates are carried out numerical value respectively
Emulation, extracts the stray inductance obtaining different capacity device group, as it is shown on figure 3, do not do equalizing tank 7 on insulating metal substrate
Time, in 7 power devices, from direct-flow input end more close to its stray inductance of power device group the least, this power device group is
Easily lost efficacy；When metal level is etched with long equalizing tank 7, the stray inductance of the 3rd power device group is minimum, but first three merit
The stray inductance of rate device group is more or less the same；As improving further, the length direction at long equalizing tank 7 be further added by one short all
Weighing apparatus groove 7, now the stray inductance of first three power device group is more nearly, and current-sharing effect is more preferable, the power mould in the present embodiment
Block uses single hop equalizing tank 7 structure shown in Fig. 2 (b).
The bearing of trend of equalizing tank 7 is vertical with the bonding direction of bonding line 6, and as shown in Fig. 2 (b), equalizing tank 7 is vertical
To, the bonding direction of bonding line 6 is that laterally the bonding direction of the bonding line 6 of indication is the approximation of bonding line 6 in theory herein
Direction, if bonding line 6 bends, the line side by bonding line 6 two ends approximated because of himself physical characteristic in practical operation
To being interpreted as the bonding direction described in the claims in the present invention, its trickle deformation, bend or tilt not as to this
The restriction of bright protection domain.
A kind of power model using above-mentioned insulated substrate structure, as shown in Figure 4, including DC input terminal 8, output
Son 9 and three half-bridge structures in parallel, three half-bridge structure order arrangements, each half-bridge structure includes insulated substrate and insulation base
Chip set on plate, in the present embodiment, every piece of insulated substrate is a half-bridge topology electrical structure, as it is shown in figure 5, each
Half-bridge structure connects two DC input terminal 8 and a lead-out terminal 9, six direct currents that three half-bridge structures are connected respectively
Input terminal 8 one word is arranged, three half-bridge structure composition three-phase bridge electric topology structures.Three pieces of insulated substrates, chip set, outer
Shell, base plate composition three-phase bridge power model.As shown in Figure 4, every piece of insulated substrate comprises two brachium pontis, and power model includes six altogether
Individual brachium pontis, each brachium pontis is composed in parallel by 7 power chips.Emitter stage or the drain electrode of upper brachium pontis chip unit 3 are drawn by bonding
Line is connected with colelctor electrode or the source electrode of lower brachium pontis chip unit 4.
The lower brachium pontis metal level 2 of at least one insulated substrate is provided with insulation between Wiring area 5 and lower brachium pontis chip unit 4
Equalizing tank 7, in the present embodiment, three insulated substrates are designed with equalizing tank 7.
Wherein, the material of the upper brachium pontis chip unit 3 of insulated substrate is one or more in Si, SiC and GaN, lower bridge
The material of arm chip unit 4 is one or more in Si, SiC and GaN；Equalizing tank 7 structure of the present invention is suitable for
The power model of high-speed switch, is particularly suitable for SiC power model.The chip type of upper brachium pontis chip unit 3 be IGBT,
One or more in MOSFET and FRD, the chip type of lower brachium pontis chip unit 4 is the one in IGBT, MOSFET and FRD
Or it is multiple.In the present embodiment, upper brachium pontis chip unit 3 and lower brachium pontis chip unit 4 chip type be MOSFET.
Embodiment 2:
The present embodiment also provides a kind of insulated substrate structure and uses the power model of this substrate, its structure and embodiment
1 structure provided is roughly the same, and the difference of the two is: the power model in the present embodiment uses the length shown in Fig. 2 (c)
Equalizing tank 7 structure.
Embodiment 3:
The present embodiment also provides a kind of insulated substrate structure and uses the power model of this substrate, as shown in Figure 6, and its knot
The structure that structure provides with embodiment 1 is roughly the same, and the difference of the two is: in the present embodiment, all half-bridge structures connect two jointly
Individual DC input terminal 8, its electrical structure topological diagram is as shown in Figure 7.
Embodiment 4:
The present embodiment also provides a kind of insulated substrate structure and uses the power model of this substrate, as shown in Figure 8, and its knot
The structure that structure provides with embodiment 1 is roughly the same, and the difference of the two is: upper brachium pontis chip unit 3 and Xia Qiao in the present embodiment
Arm chip unit 4 chip type include IGBT and FRD, and, all half-bridge structures connect two direct-flow input ends jointly
Son 8.
Embodiment 5:
The present embodiment also provides a kind of insulated substrate structure and uses the power model of this substrate, its structure and embodiment
1 structure provided is roughly the same, and the difference of the two is: the power model in the present embodiment includes three insulated substrates, but only
Have and between Wiring area 5 and lower brachium pontis chip unit 4, be provided with insulation at its lower brachium pontis metal level 2 of a middle insulated substrate
Equalizing tank 7.
Embodiment 6:
The present embodiment also provides a kind of insulated substrate structure and uses the power model of this substrate, its structure and embodiment
1 structure provided is roughly the same, and the difference of the two is: the power model in the present embodiment includes transversely arranged three half-bridge
Structure, each half-bridge structure includes two insulated substrates of longitudinal arrangement, near three insulation bases of a line of DC input terminal 8
Its lower brachium pontis metal level 2 of plate is equipped with the equalizing tank 7 of insulation between Wiring area 5 and lower brachium pontis chip unit 4.
Embodiment 7:
The present embodiment also provides a kind of insulated substrate structure and uses the power model of this substrate, its structure and embodiment
1 structure provided is roughly the same, and the difference of the two is: the power model in the present embodiment only includes two half-bridge structures, often
Individual half-bridge structure includes an insulated substrate, and its lower brachium pontis metal level 2 of each insulated substrate is at Wiring area 5 and lower brachium pontis chip list
The equalizing tank 7 of insulation it is equipped with between unit 4.
In describing the invention, it is to be understood that term " level ", " vertically ", " on ", D score, " top ", " end
Portion " etc. instruction orientation or position relationship be based on orientation shown in the drawings or position relationship, be for only for ease of describe this
Bright and simplification describes rather than indicates or imply that the equipment of indication or element must have specific orientation, with specific orientation
Structure and operation, be therefore not considered as limiting the invention.
Below it is only the preferred embodiment of the present invention, it should be pointed out that: those skilled in the art are come
Saying, under the premise without departing from the principles of the invention, it is also possible to make some improvements and modifications, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (12)
1. an insulated substrate structure, it is characterised in that include ceramic insulating layer and be formed at the gold on this ceramic insulating layer
Belonging to layer, described metal level includes that brachium pontis metal level (1) and lower brachium pontis metal level (2), upper brachium pontis metal level (1) are provided with bridge
Arm chip unit (3), lower brachium pontis metal level (2) is provided with lower brachium pontis chip unit (4), and lower brachium pontis metal level (2) includes wiring
District (5), upper brachium pontis chip unit (3) is connected by bonding line (6) with Wiring area (5), and lower brachium pontis metal level (2) is in Wiring area
(5) equalizing tank (7) of insulation and it is provided with between lower brachium pontis chip unit (4).
A kind of insulated substrate structure the most according to claim 1, it is characterised in that described equalizing tank (7) originates in close
The edge of the lower brachium pontis metal level (2) of DC input terminal (8), extends to the direction away from DC input terminal (8).
A kind of insulated substrate structure the most according to claim 2, it is characterised in that the bearing of trend of described equalizing tank (7)
Vertical with the bonding direction of bonding line (6).
A kind of insulated substrate structure the most according to claim 2, it is characterised in that described lower brachium pontis chip unit (4) is wrapped
Including the power device of multiple parallel connection, described equalizing tank (7) is the shortest to be extended to concordant with the top of first power device, the longest prolongs
Extend concordant with the top of last power device.
A kind of insulated substrate structure the most according to claim 1, it is characterised in that described equalizing tank (7) is single hop insulation
Groove or multistage insulation tank.
A kind of insulated substrate structure the most according to claim 1, it is characterised in that described upper brachium pontis chip unit (3)
Material is one or more in Si, SiC and GaN, and the material of lower brachium pontis chip unit (4) is the one in Si, SiC and GaN
Or it is multiple.
A kind of insulated substrate structure the most according to claim 1, it is characterised in that described upper brachium pontis chip unit (3)
Chip type is one or more in IGBT, MOSFET and FRD, the chip type of lower brachium pontis chip unit (4) be IGBT,
One or more in MOSFET and FRD.
8. a power model, it is characterised in that: use the insulated substrate structure as according to any one of claim 1-7.
A kind of power model the most according to claim 8, it is characterised in that include DC input terminal (8), lead-out terminal
And the half-bridge structure of multiple parallel connection (9), half-bridge structure includes the chip set on insulated substrate and insulated substrate, and each half-bridge is tied
Structure connects two DC input terminal (8) and a lead-out terminal (9), the lower brachium pontis metal level of at least one insulated substrate respectively
(2) between Wiring area (5) and lower brachium pontis chip unit (4), it is provided with the equalizing tank (7) of insulation.
A kind of power model the most according to claim 9, it is characterised in that include tactic three half-bridge structures,
Each half-bridge structure includes an insulated substrate, is positioned at its lower brachium pontis metal level (2) of an insulated substrate of centre in Wiring area
(5) equalizing tank (7) of insulation and it is provided with between lower brachium pontis chip unit (4).
11. a kind of power models according to claim 9, it is characterised in that include transversely arranged three half-bridge structure,
Each half-bridge structure includes two insulated substrates of longitudinal arrangement, near three insulated substrates of a line of DC input terminal (8)
Its lower brachium pontis metal level (2) is equipped with the equalizing tank (7) of insulation between Wiring area (5) and lower brachium pontis chip unit (4).
12. a kind of power models according to claim 9, it is characterised in that including two half-bridge structures, each half-bridge is tied
Structure includes an insulated substrate, and its lower brachium pontis metal level (2) of each insulated substrate is at Wiring area (5) and lower brachium pontis chip unit
(4) equalizing tank (7) of insulation it is equipped with between.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610435605.2A CN105931998B (en) | 2016-06-17 | 2016-06-17 | A kind of insulating substrate structure and the power module using the substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610435605.2A CN105931998B (en) | 2016-06-17 | 2016-06-17 | A kind of insulating substrate structure and the power module using the substrate |
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| CN105931998A true CN105931998A (en) | 2016-09-07 |
| CN105931998B CN105931998B (en) | 2018-07-20 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107146775A (en) * | 2017-06-14 | 2017-09-08 | 扬州国扬电子有限公司 | A kind of low stray inductance two-side radiation power model |
| CN107369657A (en) * | 2017-08-30 | 2017-11-21 | 扬州国扬电子有限公司 | A kind of two-side radiation power model of multizone laid out in parallel |
| CN108447845A (en) * | 2018-05-21 | 2018-08-24 | 臻驱科技（上海）有限公司 | Power semiconductor module substrate and power semiconductor module |
| CN118899290A (en) * | 2024-08-18 | 2024-11-05 | 致瞻科技(上海)有限公司 | A power module suitable for parallel connection |
| CN118899290B (en) * | 2024-08-18 | 2025-03-28 | 致瞻科技(上海)有限公司 | A power module suitable for parallel connection |
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