CN105930300A - Three-dimensional in-chip cache based processor structure and method for manufacturing same - Google Patents
Three-dimensional in-chip cache based processor structure and method for manufacturing same Download PDFInfo
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Abstract
The invention relates to a three-dimensional in-chip cache based processor structure and a method for manufacturing the same. The processor structure includes a processor body, and a three-dimensional stacked cache which is stacked on the processor body; the three-dimensional stacked cache includes decoders, multiplexers, a sense amplifier and a three-dimensional storage module; the three-dimensional storage module is formed by stacking a plurality of cache sub-modules with the same size; corresponding address lines of each cache sub-module are mutually connected through TSV holes; word lines of the internal address lines of the three-dimensional storage module are connected to the decoders; each of bit lines of the internal address lines of each cache sub module is connected to a multiplexer; output ends of all the multiplexers are connected each other through the TSV holes and then are connected to the input end of the sense amplifier; each of the multiplexer is provided with an enable signal OE which can control work of the multiplexer; and the input ends of the decoders, the output end of the sense amplifier and the enable signal OEs are connected to the processor body.
Description
Technical field
The present invention relates to microelectronics technology, be specially based in three-dimensional plate caching processor structure and
Its preparation method.
Background technology
Conventional planar processor is based primarily upon plane interconnection structure at present, and along with integrated level improves, tradition is flat
Globally interconnected delay and power consumption that face processor architecture introduces become restriction plane processor performance and carry further
One of bottleneck risen.To this end, most research institutions and scholar take up three-dimensional processor research.Use
Three-dimensional integration technology bring such as shorten globally interconnected length, reduce chip area, increase memory capacity excellent
While Dian, three-dimensional processor structure there is also problems with:
First, most three-dimensional processor structures are by caching in plane processor and other unit modules
Separate, caching and other modules are carried out three-dimensional integrated, form double-deck or multi-layer three-dimension processor structure.
But this processor structure needs other unit modules layout again in plane processor.
Secondly, partial 3-D processor structure is only by extension conventional planar processor cache, i.e. original
Stack cache on buffer structure.Owing to plane processor architecture and extension buffer structure are independent, therefore
This three dimensional structure only extends processor memory capacity, it is impossible to form monolithic three dimensional processor structure.
Summary of the invention
For problems of the prior art, the present invention provides a kind of based on the process of caching in three-dimensional plate
Device structure and preparation method thereof, it is not necessary to change other unit module structures in primary plane processor, at alleviation
Reason device intraconnection redundancy, improves processor structure integrated level, and design principle is simple, and structure is reliable.
The present invention is to be achieved through the following technical solutions:
Based on the processor structure of caching in three-dimensional plate, form including by ALU and control unit
Processor body, and the three-dimensional stacked caching that is arranged on processor body of stacking；Three-dimensional stacked slow
Bag deposit includes decoder, MUX, sense amplifier and three-dimensional memory module；Three-dimensional memory module by
The cache sub-module stacking that several sizes are identical is formed；By TSV hole between every layer of cache sub-module
By corresponding home address line interconnection, the wordline in three-dimensional memory module home address line connects decoder,
Bit line in every layer of cache sub-module home address line connects a MUX respectively；All multichannels are selected
The outfan selecting device is connected with the input of sense amplifier after TSV hole interconnects；In MUX
It is provided with for controlling its enable signal OE whether worked；The input of decoder and sense amplifier
Outfan and enable signal OE be connected with processor body respectively.
Preferably, when the wordline in three-dimensional memory module home address line connects a decoder, every layer is delayed
The wordline depositing submodule is connected with decoder respectively.
Preferably, in three-dimensional memory module, the wordline of every layer of cache sub-module connects a decoder respectively
Time, the outfan of all decoders is connected with processor body after TSV hole interconnects.
Preferably, three-dimensional stacked caching is arranged in encapsulation, and by the clock signal clk drawn, sheet
Select signal CS, write enable signalSignal is enabled with readingIt is connected with processor body.
Based on the processor preparation method of caching in three-dimensional plate, comprise the steps,
Step 1, chooses the plane caching meeting processor cache requirement to be prepared, in this plane being cached
Memory module along the sizes such as wordline and/or bit line are carried out split, obtain some cache sub-module and
MUX that cache sub-module is corresponding and decoder；
Step 2, is stacked the cache sub-module obtained by TSV hole, every layer of cache sub-module
Between by TSV hole, corresponding home address line is interconnected, obtain three-dimensional memory module；
Step 3, the wordline in three-dimensional memory module home address line connects decoder, every layer of caching submodule
Bit line in block home address line connects the MUX of correspondence respectively；Defeated by all MUX
Go out end after TSV hole interconnects, connect the input of sense amplifier；Be provided with in MUX for
Control its enable signal OE whether worked；
Step 4, by mutual to the three-dimensional memory module obtained, decoder, MUX and sense amplifier
Even post package obtains three-dimensional stacked caching；By three-dimensional stacked caching by draw enable signal OE, time
Clock signal CLK, chip selection signal CS, data wire, write enable signal, read enable signalAnd ground
Location line is connected with processor body.
Preferably, plane caching in memory module only along the sizes such as wordline is carried out split n time time, obtain
Corresponding decoder quantity is the 1/2 of the front decoder quantity of segmentationn, n is positive integer.
Preferably, plane caching in memory module only along the sizes such as bit line is carried out split n time time, obtain
Corresponding MUX quantity is the 1/2 of the front MUX quantity of segmentationn, n is positive integer；Increase
The quantity of MUX, it is ensured that outputs data bits width is consistent with outputs data bits width before segmentation.
Preferably, plane caching in memory module along the sizes such as wordline is carried out split n time time, edge simultaneously
When the sizes such as bit line is carried out split m time, the decoder quantity obtaining correspondence is decoder quantity before segmentation
1/2n, n is positive integer, and the MUX quantity obtaining correspondence is MUX quantity before segmentation
1/2m, m is positive integer；Increase the quantity of MUX, it is ensured that outputs data bits width and segmentation
Front outputs data bits width is consistent.
Compared with prior art, the present invention has a following useful technique effect:
Caching in conventional planar processor piece is divided by method of the present invention, uses and leads to based on silicon
The caching of division is carried out three-dimensional collection by the three-dimensional integration technology in hole (Through Silicon-Via, TSV)
Becoming, form small size, Large Copacity, low latency three-dimensional cache, then by caching and processor in three-dimensional plate
The logic module of this body weight carries out three-dimensional integrated.
Structure of the present invention improves based on two dimensional surface processor structure, and basic structure maturation can
Lean on, it is not necessary to change processor structure original relative placement of other modules in addition to caching so that it is population structure is steady
Gu；It is three-dimensional integrated by buffer structure in processor piece is carried out, it is achieved that caching single-chip integration in sheet,
The increase of capacity per unit area is cached in achieving sheet；By increasing multichannel in three-dimensional caching internal structure
Selector enables signal OE, and when making normally to work, three-dimensional storage system monolayer turns on, at effective reduction
Reason device structure power consumption；Utilize the TSV hole arranged to replace processor redundancy interconnection structure, constitute the most mutually
Link structure, considerably reduce the distance of logical block access cache, reduce processor access cache and wait
Time, reduce and postpone, effectively promote processor performance；The interior caching of planar chip of breaking the normal procedure in overall structure
Layout designs structure and conventional planar processor structure natural mode, carried out structure innovation to it, made place
Reason device performance is highly improved.
Accompanying drawing explanation
Fig. 1 is a kind of plane buffer structure schematic diagram in prior art.
Fig. 2 is the cache sub-module solid integrated morphology schematic diagram described in present example.
Fig. 3 is prior art midplane buffer structure schematic diagram.
Fig. 4 is the three-dimensional buffering external structural representation described in present example.
Fig. 5 is two dimensional surface processor structure schematic diagram in prior art.
Fig. 6 is the structural representation through three-dimensional caching stacking preprocessor described in present example.
In figure: home address line 1, internal data line 2, TSV hole 3, three-dimensional memory module 4, spirit
Quick amplifier 5, MUX 6, enable signal OE 7, clock signal clk 8, chip selection signal
CS 9, data wire 10, write enable signal11, read to enable signal12, address wire 13, process
Device body 14, three-dimensional stacked buffer structure 15.
Detailed description of the invention
Below in conjunction with specific embodiment, the present invention is described in further detail, described in be to the present invention
Explanation rather than restriction.
The present invention is to carry out existing plane processor architecture based on the processor structure of caching in three-dimensional plate
Three dimensional stress.
First, caching in sheet in processor structure is carried out three-dimensional integrated by this structure, it is not necessary to change primary plane
Other unit module structures in processor, can continue to use primary plane processor structure layout, it is not necessary to other moulds
Block carries out layout again.
Secondly, this structure carries out three-dimensional division to caching in sheet in processor structure, uses TSV skill
Art, forms monolithic solid integrated cache of memory structure.
The present invention alleviates processor intraconnection redundancy, improves processor structure integrated level, and principle is simple,
Structure is reliable, is a kind of brand-new processor structure.
Processor of the present invention mainly has three below feature, and in sheet, caching is the three-dimensional of three dimensional structure
Stack cache 15；Three-dimensional stacked caching 15 and the processor being made up of ALU and control unit
Body 14 is three-dimensional integrated；Three-dimensional stacked caching 15 three-dimensional integrated time cache sub-module between three-dimensional interconnection by
TSV is constituted.The illustrating of structure is given below.
(1) in sheet, caching is the three-dimensional stacked caching 15 of three dimensional structure.
First, use 3 D stereo integrated technology, by sheet two dimension buffer structure along wordline, bit line or
Dividing along wordline and bit line direction, division direction as shown in phantom in Figure 1, tie by two dimension caching simultaneously
Structure is as it is shown in figure 1, be divided into cache sub-module of the same size by plane buffer structure.
Secondly, division gained cache sub-module is carried out three-dimensional integrated, as in figure 2 it is shown, integrated in solid
During, if cache sub-module solid to be integrated into the three-dimensional memory module 4 of dried layer, increase caching simultaneously
The outside signal OE of enable controls three-dimensional memory module 4 internal different layers MUX gating, further
Control different layers duty；Simultaneously as along bit line divide time, cause MUX number to subtract
Few, for ensureing output data consistent, in three-dimensional memory module 4, different according to splitting scheme, increase
MUX number；
As in figure 2 it is shown, inside three-dimensional memory module 4, by corresponding home address line 1, internal number
According to line 2, and MUX enables holding wire OE and carries out longitudinal interconnection；As shown in Figure 4, three
Dimension memory module 4 is outside, by the clock signal port CLK corresponding to the cache sub-module of different layers,
Chip selection signal CS, and read-writeAddress wire 13, data wire 10, MUX
Enable holding wire OE and carry out longitudinal interconnection.
(2) three-dimensional stacked caching 15 and the processor body being made up of ALU and control unit
14 is three-dimensional integrated.
For arbitrary plane processor structure, use three-dimensional memory module 4 replacement in three-dimensional buffer structure
Plane processor caches position originally, by three-dimensional buffered signal port, such as clock signal in sheet
Port CLK, chip selection signal port CS, read-write portAddress signal port, number
According to signal port and logic unit module input, output signal port in corresponding primary plane processor structure
Interconnection, gives processor structure side view as shown in Figure 6.
Simultaneously in plane processor logical layer structure, increase input MUX and enable signal OE,
Control different cache layer MUX, select normal workspace cache layer, reduce normal operating power consumption.
(3) three-dimensional stacked caching 15 three-dimensional integrated time cache sub-module between three-dimensional interconnection by TSV structure
Become.
In three-dimensional stacked caching 15 internal structure, use TSV interconnection structure, corresponding interior before and after dividing
Portion's address wire 1, internal data line 2, and MUX enable holding wire OE and are interconnected；Three
In dimension stack cache 15 external structure, as shown in Figure 4, use TSV interconnection structure, solid is integrated
In sheet, the clock signal clk of caching different layers, chip selection signal CS, read-write, input address signal
13, outputting data signals port 10, MUX enables holding wire OE and is interconnected.
Concrete structure and preparation are as described in the following Examples.
Embodiment 1, uses the three-dimensional processor structure of single dividing mode.
(1) the structure explanation of three-dimensional memory module.
Plane buffer structure schematic diagram as shown in Figure 1.The plane of 64K × 8 is cached internal structure edge
Bit line direction once divides, and segmentation obtains Bank1-0, Bank1-1, Bank2-0, Bank2-1
Four sizes are the cache module that 16K × 4 are consistent, at the multi-path choice that levels doubles respectively
Device, it is ensured that output data are the most consistent with original, formed four 16K × 8 buffer unit Bank1-a,
Bank1-b、Bank2-a、Bank2-b.According to Fig. 2, by the memory module of 16K × 8
Bank1-a, Bank2-a are stacked on memory module Bank1-b, Bank2-b respectively, form two-layer
Three-dimensional integrated cache of memory structure.
Plane buffering external structure as shown in Figure 3；The three-dimensional contrasting solid as shown in Figure 4 integrated is deposited
Storage module-external signal connected mode.Wherein MUX enable signal OE can cache work time,
Control the MUX of different layers, thus select to turn on the cache sub-module of respective layer, make to be buffered in work
Make under state, only need monolayer to work.
(2) explanation of three-dimensional processor structure.
Comparison diagram 5 provides plane processor architecture, stores in the three-dimensional processor structural representation in Fig. 6
In device, cache sub-module is 2 layers, and during three-dimensionally integrated, in three-dimensional integrated cache of memory, cache sub-module is
The logical layer of lower floor and processor body is positioned at same layer, i.e. builds three-dimensional processor structure and compares original place reason
Device structure is without changing logic unit module relativeness.Three-dimensional processor passes through TSV access cache,
Considerably reduce globally interconnected length.
(3) three-dimensional integrated interconnection structure explanation.
In three-dimensional memory module 4 internal structure, as in figure 2 it is shown, in three-dimensional integrating process, use
Corresponding address line before and after caching division and data wire are interconnected by TSV；
In three-dimensional memory module 4 outside, as shown in Figure 4, use TSV that buffer structure clock is believed
Number CLK, chip selection signal CS, read write enable signal, and MUX enable signal
OE carries out longitudinal interconnection.In Fig. 4, dotted line represents caching internal structure TSV.
Embodiment 2, uses the three-dimensional processor structure of different demarcation mode.
(1) the structure explanation of three-dimensional memory module.
Plane buffer structure schematic diagram as shown in Figure 1.The plane of 64K × 8 is cached internal structure edge
Bit line direction once divides, then carries out secondary division along word-line direction, and segmentation obtains Bank1-
The cache module of 0/1/2/3, Bank2-0/1/2/3 eight 8K × 4, doubles respectively in levels
MUX, it is ensured that output data, with the most consistent, form 8 8K × 8 cache modules.According to
Shown in Fig. 2, memory module Bank1-a/b, Bank2-a/b are stacked in memory module Bank1-respectively
On c/d, Bank2-c/d, form 4 layers of three-dimensional integrated cache of memory layer.
Plane buffering external structure as shown in Figure 3；The three-dimensional contrasting solid as shown in Figure 4 integrated is deposited
Storage module-external signal connected mode.Wherein MUX enable signal OE can cache work time,
Control different layers MUX, thus select to turn on the cache sub-module of respective layer, make to be buffered in work
Under state, monolayer is only needed to work.
(2) explanation of three-dimensional processor structure.
Comparison diagram 5 provides plane processor architecture, stores in the three-dimensional processor structural representation in Fig. 6
In device, cache sub-module is 4 layers, and during three-dimensionally integrated, in three-dimensional integrated cache of memory, cache sub-module is
The logical layer of lower floor and processor body is positioned at same layer, i.e. builds three-dimensional processor structure and compares original place reason
Device structure is without changing logic unit module relativeness.Three-dimensional processor passes through TSV access cache,
Considerably reduce globally interconnected length.
(3) three-dimensional integrated interconnection structure explanation.
In three-dimensional memory module 4 internal structure, as in figure 2 it is shown, in three-dimensional integrating process, use
Corresponding address line before and after caching division and data wire are interconnected by TSV；
In three-dimensional memory module 4 outside, as shown in Figure 4, use TSV that buffer structure clock is believed
Number CLK, chip selection signal CS, read write enable signalAnd MUX enables signal
OE carries out longitudinal interconnection.In Fig. 4, dotted line represents caching internal structure TSV.
Claims (8)
1. based on the processor structure of caching in three-dimensional plate, it is characterised in that include by ALU
With control unit composition processor body (14), and stacking be arranged on processor body (14)
Three-dimensional stacked caching (15)；
Described three-dimensional stacked caching (15) includes decoder, MUX (6), sense amplifier
And three-dimensional memory module (4) (5)；Three-dimensional memory module (4) is sub by the caching that several sizes are identical
Module stack is formed；By TSV hole by corresponding home address line (1) between every layer of cache sub-module
Interconnection, the wordline in three-dimensional memory module (4) home address line (1) connects decoder, every layer of caching
Bit line in submodule home address line (1) connects a MUX (6) respectively；All multichannels
The outfan of selector (6) is connected with the input of sense amplifier (5) after TSV hole interconnects；
It is provided with in MUX (6) for controlling its enable signal OE (7) whether worked；Decoding
The input of device and the outfan of sense amplifier (5) and enable signal OE (7) respectively with place
Reason device body (14) connects.
The most according to claim 1 based on the processor structure of caching in three-dimensional plate, its feature exists
In, when the wordline in three-dimensional memory module (4) home address line (1) connects a decoder, every layer
The wordline of cache sub-module is connected with decoder respectively.
The most according to claim 1 based on the processor structure of caching in three-dimensional plate, its feature exists
In, when in three-dimensional memory module (4), the wordline of every layer of cache sub-module connects a decoder respectively,
The outfan of all decoders is connected with processor body (14) after TSV hole interconnects.
The most according to claim 1 based on the processor structure of caching in three-dimensional plate, its feature exists
Arrange in encapsulation in, three-dimensional stacked caching (15), and by the clock signal clk (8) drawn,
Chip selection signal CS (9), write enable signal(11) and read enable signalAnd processor (12)
Body (14) connects.
5. based on the processor preparation method of caching in three-dimensional plate, it is characterised in that comprise the steps,
Step 1, chooses the plane caching meeting processor cache requirement to be prepared, in this plane being cached
Memory module along the sizes such as wordline and/or bit line are carried out split, obtain some cache sub-module and
MUX (6) that cache sub-module is corresponding and decoder；
Step 2, is stacked the cache sub-module obtained by TSV hole, every layer of cache sub-module
Between by TSV hole, corresponding home address line (1) is interconnected, obtain three-dimensional memory module (4)；
Step 3, the wordline in three-dimensional memory module (4) home address line (1) connects decoder, often
Bit line in layer cache sub-module home address line (1) connects the MUX (6) of correspondence respectively；
The outfan of all MUX (6) is connected after TSV hole interconnects sense amplifier (5)
Input；It is provided with in MUX (6) for controlling its enable signal OE whether worked
(7)；
Step 4, by the three-dimensional memory module (4) obtained, decoder, MUX (6) and spirit
Quick amplifier (5) interconnection post package obtains three-dimensional stacked caching (15)；By three-dimensional stacked caching (15)
By enable signal OE (7) drawn, clock signal clk (8), chip selection signal CS (9), number
According to line (10), write enable signal(11), read to enable signal(12) and address wire (13) with
Processor body (14) connects.
The most according to claim 5 based on the processor preparation method of caching, its feature in three-dimensional plate
Be, the memory module in plane caching only along the sizes such as wordline is carried out split n time time, obtain corresponding
Decoder quantity is the 1/2 of the front decoder quantity of segmentationn, n is positive integer.
The most according to claim 5 based on the processor preparation method of caching, its feature in three-dimensional plate
Be, the memory module in plane caching only along the sizes such as bit line is carried out split n time time, obtain corresponding
MUX (6) quantity is the 1/2 of the front MUX quantity of segmentationn, n is positive integer；Increase
The quantity of MUX (6), it is ensured that outputs data bits width is consistent with outputs data bits width before segmentation.
The most according to claim 5 based on the processor preparation method of caching, its feature in three-dimensional plate
Be, plane caching in memory module along the sizes such as wordline is carried out split n time time, while enter along bit line
When the sizes such as row split m time, the decoder quantity obtaining correspondence is decoder quantity before segmentation
1/2n, n is positive integer, and MUX (6) quantity obtaining correspondence is MUX number before segmentation
The 1/2 of amountm, m is positive integer；Increase the quantity of MUX (6), it is ensured that outputs data bits width
Consistent with outputs data bits width before segmentation.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114051131A (en) * | 2021-10-08 | 2022-02-15 | 四川九洲空管科技有限责任公司 | Radar video display method, device, equipment and storage medium |
| CN117034827A (en) * | 2023-10-08 | 2023-11-10 | 华中科技大学 | Multi-path selector, interconnection switch and peripheral interface circuit for eFPGA |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101145147A (en) * | 2007-10-10 | 2008-03-19 | 山东大学 | 3D Multiprocessor SoC |
| US20110078412A1 (en) * | 2009-09-30 | 2011-03-31 | International Business Machines Corporation | Processor Core Stacking for Efficient Collaboration |
-
2016
- 2016-04-13 CN CN201610228623.3A patent/CN105930300A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101145147A (en) * | 2007-10-10 | 2008-03-19 | 山东大学 | 3D Multiprocessor SoC |
| US20110078412A1 (en) * | 2009-09-30 | 2011-03-31 | International Business Machines Corporation | Processor Core Stacking for Efficient Collaboration |
Non-Patent Citations (1)
| Title |
|---|
| LEI YI,GUANGBAO SHAN,SONG LIU,CHENGMIN XIE: "A new processor design based on 3D cache", 《4TH NATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS AND COMPUTER ENGINEERING》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114051131A (en) * | 2021-10-08 | 2022-02-15 | 四川九洲空管科技有限责任公司 | Radar video display method, device, equipment and storage medium |
| CN114051131B (en) * | 2021-10-08 | 2023-12-26 | 四川九洲空管科技有限责任公司 | Radar video display method, device, equipment and storage medium |
| CN117034827A (en) * | 2023-10-08 | 2023-11-10 | 华中科技大学 | Multi-path selector, interconnection switch and peripheral interface circuit for eFPGA |
| CN117034827B (en) * | 2023-10-08 | 2023-12-15 | 华中科技大学 | Multi-path selector, interconnection switch and peripheral interface circuit for eFPGA |
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