CN105930294A

CN105930294A - Digital IIC (Inter-Integrated Circuit) system based on state machine

Info

Publication number: CN105930294A
Application number: CN201610470849.4A
Authority: CN
Inventors: 张宏彬
Original assignee: Individual
Current assignee: Individual
Priority date: 2016-06-25
Filing date: 2016-06-25
Publication date: 2016-09-07

Abstract

The invention relates to a digital IIC (Inter-Integrated Circuit) system based on a state machine. The digital IIC system comprises a processor, a serial bus clock, a serial data bus and a plurality of slave devices, wherein the processor is provided with two pin ends; the two pin ends are respectively connected with the serial bus clock and the serial data bus; the serial bus clock and the serial data bus are respectively and sequentially connected to a slave device I, a slave device II, a slave device III and a slave device IV. The digital IIC system disclosed by the invention has the beneficial effects that the problem that plenty of CPU (Central Processing Unit) time is wasted on IIC time sequence waiting can be avoided when an IIC is used by the digital IIC system, so that the whole system efficiency is increased; a timer is used for interrupting and pushing the state machine to simulate the operation of the IIC, the operation is realized by adopting an interruption way, and the system efficiency is greatly improved through the design; the digital IIC system is beneficial for meeting IIC interconnection at a high speed and a low speed.

Description

A kind of digital integrated electronic circuit bus system based on state machine

Technical field

The present invention relates to iic bus technology, particularly relate to a kind of digital integrated electronic circuit bus system based on state machine.

Background technology

Iic bus technology i.e. Inter-Integrated Circuit(IC bus), designed at early eighties by Philips Semiconductor Co., Ltd., it is primarily used to connect integrated circuit (ICS), IIC is a kind of multidirectional control bus, the most multiple chips may be connected under same bus structure, the most each chip can serve as the control source of real-time Data Transmission, and this mode simplifies signal transmission bus interface.Secondly, iic bus is to use holding wire minimum in various bus, and has the bus of the functions such as automatic addressing, the synchronization of many host clock and arbitration.Therefore, using the iic bus system that designs a calculating machine very convenient flexibly, volume is the least, is used widely in all kinds of actual application.

This case it is important to note that, more IIC device is also using in existing unmanned plane during flying device system design process, so the IIC design of whole system also highlights important, but, the comprehensive feature of IIC technology at present and the use of actual scene limit, need according to some reason following, carry out innovative design:

First, at present, the speed of the most of IIC device used on the market is general at present only supports 400Kbit/s, belong to relative to MCU speed and connect at a slow speed, when using IIC in a rapid system, the sequential that being easily caused a large amount of CPU time wastes in IIC waits, thus drags slow whole system efficiency.

Second, in aerocraft system designs, there is multiple IIC device, and each response device speed speed is inconsistent, some device can support 400Kbit/s, when some device can only support 100Kbit/s even 50Kbit/s, system effectiveness to be made reaches optimization, is now accomplished by making special handling for the device of different rates；The method used in aerocraft system designs is to be divided into by device quickly and slow response component other places reason, the method is used to need to use multiple IIC interfaces, aerocraft system design comparison is intensive simultaneously, the peripheral resource of used MCU is limited, so that realizing many IIC interface by the mode of GPIO simulation is the selection making system optimization.

3rd, the program of overwhelming majority GPIO simulation iic bus is all inquiry mode at present, wastes a large amount of cpu cycle for circular wait.This case use timer interruption promote state machine to simulate the operation of iic bus, employing interrupt mode realizes, call back function can be automatically called when read-write completes or makes mistakes by self-defining call back function, this design greatly improves system effectiveness, certainly, this design also can read and write iic bus by inquiry mode, it is only necessary to inquiry IIC_BUSY.

4th, when design, if the device without subaddressing is only supported in the CPAL storehouse selecting MCU, the ST company of STM32 to release under interrupt mode works, it is impossible to accomplish that interrupt mode completes to read and write major part I2C device.Simultaneously, CPAL storehouse is when multiple IIC use simultaneously, the most also there are existing problems, actual product uses instability, thus, finally abandon and use the CPAL storehouse of ST company and standard peripherals storehouse to access IIC device, use GPIO based on state machine to simulate iic bus, be the most also to support that interrupt mode completes IIC read-write.

Therefore, for the above, need prior art is effectively innovated.

Summary of the invention

For disadvantages described above, the present invention provides a kind of digital integrated electronic circuit bus system based on state machine that system effectiveness is greatly improved, to solve many deficiencies of prior art.

For achieving the above object, the present invention is by the following technical solutions:

A kind of digital integrated electronic circuit bus system based on state machine, it is made up of processor, Serial Bus Clock, serial data bus and some slaves, described processor arranges two leads ends, the two leads ends connects Serial Bus Clock, serial data bus respectively, and described Serial Bus Clock, serial data bus are sequentially ingressed into slave I, slave II, slave III, slave IV the most respectively；Described Serial Bus Clock, serial data bus promote the running of whole IIC state machine based on intervalometer, by adjusting the timing step of intervalometer, meet the IIC interconnection of high, low speed.

Described Serial Bus Clock, serial data bus are respectively provided with pull-up resistor.

When bus system realizes, including IIC write operation flow process, this flow process supports that 1 to 4 byte IIC, from address of devices, supports that multibyte data sends；

When bus system realizes, including IIC read operation flow process, this flow process supports that 1 to 4 byte IIC, from address of devices, supports that multibyte data reads.

Having the beneficial effect that of digital integrated electronic circuit bus system based on state machine of the present invention

(1), when this system uses IIC, a large amount of CPU time can be avoided to waste the problem waited in IIC sequential, improve whole system efficiency；

(2) using timer interruption to promote state machine to simulate the operation of iic bus, use interrupt mode to realize, this design greatly improves system effectiveness；

(3) be conducive to meeting the IIC interconnection of high, low speed.

Accompanying drawing explanation

Below according to accompanying drawing, the present invention is described in further detail.

Fig. 1 is digital integrated electronic circuit bus system connection diagram based on state machine described in the embodiment of the present invention；

Fig. 2 is that the intervalometer of digital integrated electronic circuit bus system based on state machine described in the embodiment of the present invention promotes state machine entrance schematic flow sheet；

Fig. 3 is the IIC write operation schematic flow sheet of digital integrated electronic circuit bus system based on state machine described in the embodiment of the present invention；

Fig. 4 is the IIC read operation schematic flow sheet of digital integrated electronic circuit bus system based on state machine described in the embodiment of the present invention.

In figure:

1, processor；2, slave I；3, slave II；4, slave III；5, slave IV；6, supply pin；7, Serial Bus Clock；8, serial data bus.

Detailed description of the invention

As shown in Figure 1, digital integrated electronic circuit bus system based on state machine described in the embodiment of the present invention, by processor 1, Serial Bus Clock 7, serial data bus 8 and some slaves composition, described processor 1 arranges two leads ends, the two leads ends connects Serial Bus Clock 7 respectively, serial data bus 8, described Serial Bus Clock 7, serial data bus 8 is each all sequentially ingressed into slave I 2, slave II 3, slave III 4, slave IV 5, simultaneously, if with pull-up resistor to meet circuit sequence requirement inside described processor 1, then it is not required to external pull-up resistor.It addition, this digital integrated electronic circuit bus system is with power module.

As in Figure 2-4, the digital integrated electronic circuit bus system based on state machine described in the embodiment of the present invention, promote the running of whole IIC state machine based on intervalometer, by adjusting the timing step of intervalometer, the IIC interconnection of high, low speed can be met；This bus system workflow mainly includes that intervalometer promotes state machine entrance flow process, IIC write operation, IIC read operation, and IIC write operation therein supports that 1 to 4 byte IIC, from address of devices, supports that multibyte data sends；IIC read operation therein supports that 1 to 4 byte IIC, from address of devices, supports that multibyte data reads.

Digital integrated electronic circuit bus system based on state machine described in the above embodiment of the present invention, this case uses timer interruption to promote state machine to simulate the operation of iic bus, employing interrupt mode realizes, call back function can be automatically called when read-write completes or makes mistakes by self-defining call back function, this design greatly improves system effectiveness, this design also can read and write iic bus by inquiry mode, it is only necessary to inquiry IIC_BUSY；If the device without subaddressing is only supported in the CPAL storehouse selecting MCU, the ST company of STM32 to release under interrupt mode works, it is impossible to accomplish that interrupt mode completes to read and write major part I2C device.Simultaneously, CPAL storehouse is when multiple IIC use simultaneously, the most also there are existing problems, actual product uses instability, thus, finally abandon and use the CPAL storehouse of ST company and standard peripherals storehouse to access IIC device, use GPIO based on state machine to simulate iic bus, be the most also to support that interrupt mode completes IIC read-write.

The above-mentioned description to embodiment be for the ease of those skilled in the art it will be appreciated that and application this case technology, these examples obviously can be made various amendment by person skilled in the art easily, and General Principle described herein is applied in other embodiments without through performing creative labour.Therefore, this case is not limited to above example, and those skilled in the art should be in the protection domain of this case according to the announcement of this case, the improvement made for this case and amendment.

Claims

1. a digital integrated electronic circuit bus system based on state machine, it is characterized in that, it is made up of processor, Serial Bus Clock, serial data bus and some slaves, described processor arranges two leads ends, the two leads ends connects Serial Bus Clock, serial data bus respectively, and described Serial Bus Clock, serial data bus are sequentially ingressed into slave I, slave II, slave III, slave IV the most respectively；Described Serial Bus Clock, serial data bus promote the running of IIC state machine based on intervalometer, by adjusting the timing step of intervalometer, meet the IIC interconnection of high, low speed.

Digital integrated electronic circuit bus system based on state machine the most according to claim 1, it is characterised in that: described Serial Bus Clock, serial data bus are respectively provided with pull-up resistor.

Digital integrated electronic circuit bus system based on state machine the most according to claim 1, it is characterised in that: when bus system realizes, including IIC write operation flow process, this flow process supports that 1 to 4 byte IIC, from address of devices, supports that multibyte data sends.

Digital integrated electronic circuit bus system based on state machine the most according to claim 1, it is characterised in that: when bus system realizes, including IIC read operation flow process, this flow process supports that 1 to 4 byte IIC, from address of devices, supports that multibyte data reads.