CN105897223B - A kind of primary particle inversion resistant d type flip flop - Google Patents

Abstract

The invention discloses an anti-single-event flip-flop D flip-flop, which is composed of master-slave two-stage latches (Latch) connected in series. Instead, it consists of six PMOS transistors P1-P6 and six NMOS transistors N1-N6. On the basis of the Latch core, the main Latch or the slave Latch of the present invention can be formed by adding transistors with clock control. Compared with the traditional three-mode redundancy technology, the invention not only saves the area overhead of an election circuit, but also eliminates the single event sensitivity problem caused by the election circuit. At the same time, when the D flip-flop in the present invention stores a value of 0, it has lower single-event sensitivity and stronger anti-single-event reversal capability. Since many flip-flops need to maintain the same value for a long time in practical applications, the present invention is of great significance for further improving the anti-single-event reversal capability of such flip-flops.

Description

A D Flip-Flop Anti-Single Event Inversion

technical field

The invention relates to a flip-flop in the field of integrated circuits, in particular to a D flip-flop resistant to single-event reversal in a radiation environment.

Background technique

There are a large number of high-energy particles (protons, heavy ions, etc.) and high-energy rays in the universe. A sequential unit in an integrated circuit, such as a flip-flop, will generate a Single Event Upset (SEU for short) after being bombarded by these high-energy particles and rays. The generation of single-event upsets will produce soft errors, which will make the operation of integrated circuits go wrong. As the process size continues to shrink, the transistor density of integrated circuits continues to increase, and the probability of multiple transistors being bombarded by single particles at the same time is greatly increased, and the reduction in the size of the transistor itself makes the critical charge that represents the state of the device continue to decrease. Device design poses great challenges. On the one hand, multi-node charge collection caused by simultaneous bombardment of multiple transistors will lead to single-event multi-bit flip (Multiple Cell Upset, referred to as MCU); on the other hand, simultaneous multi-node charge collection makes many traditional flip-flop reinforcement design techniques (such as double interlocking unit Dual Interlocked Cell ( DICE for short), etc.) the reinforcement effect is greatly weakened. Therefore, at the nanoscale, it is necessary to design a new type of highly reliable anti-single event flip-flop circuit.

The ordinary D flip-flop is shown in Figure 1. It is composed of master-slave two-level latches (Latch) in series, which are recorded as the master Latch and the slave Latch. The logic structure of the master Latch and the slave Latch is the same, as shown in Figure 2(a) As shown, it consists of two input inverters Inv1 with clock control, feedback inverter Inv2, and one inverter without clock control (referred to as the third inverter Inv3). The input terminal of the input inverter receives the data signal D, the output terminal is connected to the node MN, and two clock input terminals respectively receive the clock signal CLK and From a functional point of view, as shown in Figure 2(b), the feedback inverter Inv2 and the third inverter Inv3 are connected end to end to form the storage structure of Latch or the core of Lacth in a common D flip-flop, and the third inverter The input terminal of Inv3 is connected to the node MN, the node MN is connected to the output terminal of the input inverter Inv1, the output terminal of the third inverter Inv3 is connected to the node M and the input terminal of the feedback inverter Inv2, and the node M is actually directly connected to The output Q of the Latch; the input terminal of the feedback inverter Inv2 is connected to the node M, the output terminal is connected to the node MN, and two clock input terminals respectively receive the clock signal CLK and

The realization of the third inverter is shown in Figure 3(a ₎ , which is composed of a PMOS transistor P0 and an NMOS transistor _N0 , wherein the drains of the PMOS transistor and the NMOS transistor are connected to form the output terminal Y of the inverter, and The gates of the PMOS transistor and the NMOS transistor are connected to form the input terminal A of the inverter; the source of the PMOS transistor is connected to the power supply VDD, and the source of the NMOS transistor is connected to the ground VSS. As shown in Fig. 3(b)-(d), the input inverter or feedback inverter with clock control is composed _of two PMOS transistors P1 and P2 and _two NMOS transistors _N1 and _N2 . 3 implementations. Looking at these three implementation forms, they all add a clock-controlled PMOS transistor P2 _on the basis of the third inverter (composed of PMOS transistor P1 and NMOS transistor N1) shown in Figure ₃ ( _a ). and a clock-controlled NMOS transistor N ₂ ; and its increased transistors are either connected in series as shown in Figure 3(b)-(c), or connected in a transmission gate (TransmissionGate, TG) as shown in Figure 3(d) ) is connected to the output of the inverter. The transmission gate is composed of a PMOS transistor and an NMOS transistor, where the sources of the PMOS transistor and the NMOS transistor are connected to each other, and the drains are also connected to each other, and the respective gates are controlled by an external control signal from the source to the drain. . It should be noted that the phase difference between the clock signal in the input inverter with clock control and the clock signal in the feedback inverter with clock control is 180 degrees. That is to say, when the gate of the PMOS transistor P2 in the input inverter with clock control is connected to an external signal _CLK , the gate of the PMOS transistor P2 in the feedback inverter with clock control is connected to the CLK signal via An inverter generates the non-signal of CLK superior.

"Upset hardened memory design for submicro CMOS Technology" published by T.Calin et al. in IEEE Transaction on Nuclear Science (Journal of IEEE Atomic Energy Science) (December 1996 No. Issue 6, Volume 43, Pages 2874-2878) proposed the DICE structure for the first time. This structure adopts the form of double interlocking, which can effectively suppress single-event flipping in micron and submicron processes. So far, the DICE structure has been widely used to trigger Device reinforcement design. However, under nanotechnology, "Technology scaling com-parison of flip-flop heavy-ion single event upsetcross sections" published in IEEE Transaction on Nuclear Science (IEEE Atomic Energy Science Journal) by N.Gaspard et al. A comparison of the effects of process reduction factors on single event flip-flop cross section of flip-flops) (Volume 60, Issue 6, December 2013, pages 4368-4373) pointed out that the reinforcement effect of DICE flip-flops decreased sharply compared to D flip-flops, and DICE flip-flops and The single event turnover cross section of the D flip-flop changed from a difference of 1 to 2 orders of magnitude to a difference of only 1.2 to 5 times. Under the nano-CMOS process, the currently widely used flip-flop design scheme also has a three-mode redundant reinforced D flip-flop, such as "Comparison of heavy" published in Science China Information Sciences by Y.He et al. -ion induced SEU for D-and TMR-flip-flop designs in 65nmbulk CMOS technology" (Comparison of Heavy-Ion Single Event Flip for D-Flip-Flop and its Triple-Mode Redundancy Design under 65nm CMOS Technology) (No. 10, October 2014 Issue No. 57, Page 102405:1-7) pointed out that triple-mode redundancy technology is very effective in suppressing single event flipping, but the flipping cross-section of triple-mode redundancy is only reduced by about one order of magnitude under the 65-nanometer process, and the triple-mode redundancy The election circuit itself introduced by the redundancy technique is also single-event sensitive.

As the process size shrinks to 65nm and below, charge sharing-induced single-event multi-node charge collection in integrated circuits has become a common phenomenon. On the one hand, it is increasingly difficult for the current reinforced D flip-flop to avoid the single event upset caused by single-event multi-node charge collection, so that it cannot meet the requirements of anti-single event upset in the radiation environment; on the other hand, the traditional D flip-flop Although the three-mode redundancy reinforcement technology of the device can well suppress the single event flip, it cannot avoid the single event flip caused by the election circuit required by the triple-mode redundancy and requires more than 4 times the area (including the area of the election circuit) overhead. How to reduce the single event turnover cross-section of the reinforced D flip-flop, and then improve the anti-single event turnover capability of the D flip-flop is a technical issue that is of great concern to those skilled in the art.

Contents of the invention

The technical problem to be solved by the present invention is: the existing reinforced D flip-flop cannot meet the requirement of anti-single event flip-flop in the radiation environment, and the traditional three-mode redundant reinforcement technology of D flip-flop cannot avoid the single event flip-flop caused by the election circuit In addition to the problem of large area overhead, a D flip-flop that resists single event flips is provided, which has stronger anti-single event flip-flop capability, and effectively reduces the area overhead of the triple-mode redundancy reinforcement technology, eliminating the single-event sensitivity caused by the election circuit. sexual issues.

The technical scheme of the present invention is: among the present invention, D flip-flop is formed by master latch and slave latch two-stage latch series connection, and the structure of master latch and slave latch is exactly the same, but this Latch and The Latch in the ordinary D flip-flop is not exactly the same. The core of the Latch is no longer two inverters connected end to end, but as shown in Figure 4, it consists of 6 PMOS transistors P1~P6 and 6 NMOS transistors N1~ N6 constitutes. As shown in Figure 4, the drain of N1 is connected to the drain of P1, node MN1, and connected to the gates of P2 and N4, the gate of N1 is connected to the drain of N2; the drain of N2 is connected to the drain of P2 pole, node M1, and connected to the gate of P3 and N1, the gate of N2 is connected to the drain of N5; the drain of N3 is connected to the drain of P3, node MN2, and connected to the gate of P4 and N6 On the pole, the gate of N3 is connected to the drain of N4; the drain of N4 is connected to the drain of P4, the node M2, and connected to the gates of P5 and N3, and the gate of N4 is connected to the drain of N1; The drain of N5 is connected to the drain of P5 and the node MN3, and connected to the gates of P6 and N2, the gate of N5 is connected to the drain of N6; the drain of N6 is connected to the drain of P6 and the node M3, And connected to the gates of P1 and N5, the gate of N6 is connected to the drain of N3. The gate of P1 is connected to the drain of N6, the drain of P1 is connected to the drain of N1; the gate of P2 is connected to the drain of N1, the drain of P2 is connected to the drain of N2; the gate of P3 is connected to the drain of N2 The drain of P3 is connected to the drain of N3; the gate of P4 is connected to the drain of N3, the drain of P4 is connected to the drain of N4; the gate of P5 is connected to the drain of N4, and the drain of P5 The drain of P6 is connected with the drain of N5; the gate of P6 is connected with the drain of N5, and the drain of P6 is connected with the drain of N6. The sources of the six PMOS transistors P1-P6 are all connected to the power supply VDD; the sources of the six NMOS transistors N1-N6 are all connected to the ground VSS.

On the basis of the kernel shown in FIG. 4 , the master latch or the slave latch of the present invention can be formed by adding transistors with clock control and the like. The master latch in the D flip-flop of the present invention is still completely the same as the slave latch. As shown in Figure 5, the data input D of the master latch is respectively connected to the nodes MN1, MN2 and MN3 in the latch core through three input inverters with clock control, and the latch core nodes M1, M2 and M3 only need to add one each according to the inverter with clock control in the prior art (serial mode as shown in Figure 3(b)-(c), or transmission gate mode as shown in Figure 3(d)) The PMOS and NMOS transistors controlled by the clock are enough, and finally any node of the M1 or M2 or M3 node of the master latch is connected to the data input D of the slave latch, and the M1 or M2 or M3 of the slave latch Any one of the nodes is the data output Q of the D flip-flop of the present invention.

5-7 are three specific implementation forms of the master (or slave) latch in the D flip-flop of the present invention.

The latch shown in Figure 5 adopts the implementation shown in Figure 3(b), and the sources of PMOS transistors P2, P4, and P6 are each connected to the power supply through a PMOS transistor controlled by a clock signal (ie, P7, P8, and P9). VDD, while the sources of the NMOS transistors N2, N4 and N6 are each connected to the ground VSS through an NMOS transistor (ie, N7, N8 and N9) controlled by a clock signal. The data input D of the latch is respectively connected to the nodes MN1, MN2 and MN3 through three clocked input inverters Inv1~Inv3, and the node M3 is selected as the output signal Q. Two such latches can be connected in series in the manner of Fig. 1 to form the D flip-flop of the present invention, and any node in the M1 or M2 or M3 nodes of the master latch is connected to the data input D of the slave latch. , and in this example, node M3 of the slave latch is selected as the output signal Q.

The latch shown in Figure 6 adopts the implementation shown in Figure 3(c). A PMOS transistor P10 controlled by a clock signal and a PMOS transistor controlled by a clock signal are sequentially inserted between the drain of the PMOS transistor P2 and the drain of the NMOS transistor N2. Between the NMOS transistor N10 controlled by the signal, the drain of the PMOS transistor P4 and the drain of the NMOS transistor N4, a PMOS transistor P11 controlled by a clock signal and an NMOS transistor N11 controlled by a clock signal, the drain of the PMOS transistor P6 A PMOS transistor P12 controlled by a clock signal and an NMOS transistor N12 controlled by a clock signal are sequentially inserted between the pole and the drain of the NMOS transistor N6. Similarly, the data input D of the latch is respectively connected to the nodes MN1, MN2 and MN3 through three input inverters Inv1~Inv3 with clock control, and the node M3 is selected as the output signal Q. Two such latches can be connected in series in the manner of Fig. 1 to form the D flip-flop of the present invention, and any node in the M1 or M2 or M3 nodes of the master latch is connected to the data input D of the slave latch. , and in this example, node M3 of the slave latch is selected as the output signal Q.

The latch shown in Figure 7 adopts the transmission gate method shown in Figure 3(d), that is, the control of the clock signal to the data path is realized through the transmission gates TG1, TG2 and TG3. The PMOS transistor P13 and the NMOS transistor N13 constitute the transmission gate TG1, the PMOS transistor P14 and the NMOS transistor N14 constitute the transmission gate TG2, and the PMOS transistor P15 and the NMOS transistor N15 constitute the transmission gate TG3. One end of the transmission gate TG1 is connected to the M1 node, and the other end is connected to the gates of the NMOS transistor N1 and the PMOS transistor P3; one end of the transmission gate TG2 is connected to the M2 node, and the other end is connected to the gates of the NMOS transistor N3 and the PMOS transistor P5; One end of the transmission gate TG3 is connected to the M3 node, and the other end is connected to the gates of the NMOS transistor N5 and the PMOS transistor P1. Similarly, the data input D of the latch is respectively connected to the nodes MN1, MN2 and MN3 through three clocked input inverters Inv1~Inv3, and the node M3 is selected as the output signal Q. Two such latches can be connected in series in the manner of Fig. 1 to form the D flip-flop of the present invention, and any node in the M1 or M2 or M3 nodes of the master latch is connected to the data input D of the slave latch. , and in this example, node M3 of the slave latch is selected as the output signal Q.

The working process of anti-single event flipping of the present invention is:

When the high-energy particles or rays in the space bombard the master latch in the D flip-flop of the present invention or somewhere in the slave latch, as shown in PMOS transistors P2 and P3 in Figure 4, single event transients will be produced on P3 , the node MN2 will produce a 0→1 full-scale voltage jump, turn on the NMOS transistor N6, so that the voltage on the node M3 becomes an intermediate level value; at the same time, the PMOS transistor P2 is bombarded by particles and the node The voltage on M1 is boosted and maintained at a high level, which acts on the N1 transistor so that the node MN1 is not affected by the N6 transistor driving P1 and remains at a logic low level, so the storage structure of the latch does not occur The value is flipped. Of course, from the point of view of the circuit, the latch composed of the core shown in Figure 4 is not completely immune to single-event inversion. For example, when the transistor pair (P1, P3) is bombarded by particles at the same time, both nodes MN1 and MN2 will generate 0 → 1 full-swing voltage jump; thus causing a 1→0 full-swing voltage jump on the node M2, and a 1→1/2 half-swing voltage jump on the node M3; at this time, the MN3 node is affected by P5 The drive is stronger, and the MN3 node slowly undergoes a 0→1 full-swing transition, which drives a 1→0 full-swing transition on M3; finally, the value of Lacth flips. In the latch composed of the core shown in Figure 4, for the two data modes of storing 0 and storing 1, there are 9 pairs of transistor pairs that can be reversed by the simultaneous bombardment of particles, and these transistor pairs are only in the data mode of storing 1 However, the transistor pairs (P1, P3) and (P3, P5) have the shortest distance in the layout implementation, and both achieve 1.79 μm according to the minimum layout design rules; therefore, it is actually difficult for these transistor pairs to be bombarded by particles at the same time, that is, The latch in the present invention and the D flip-flop in the present invention have very high anti-single-event reversal capability.

Adopt the present invention can reach following technical effect:

1. Since the core of each latch in the present invention is composed of 6 PMOS transistors and 6 NMOS transistors, this not only saves the area overhead of an election circuit compared with the traditional triple-mode redundancy technology, but also eliminates The single event sensitivity problem caused by the election circuit;

2. The value stored in the D flip-flop in the present invention has a significant impact on the single event sensitivity of the unit. For the data mode of storing 0, any two transistors in the D flip-flop are bombarded by particles at the same time, and the value reversal will not occur, which makes the D flip-flop in the present invention less sensitive to single events when storing a value of 0 Particle flipping ability is stronger. Since many flip-flops need to maintain the same value for a long time in practical applications, the present invention is of great significance for further improving the anti-single-event upset capability of such flip-flops.

Description of drawings

Fig. 1 is a logic structure diagram of a D flip-flop adopting a master-slave two-stage latch structure;

Fig. 2 is the logical structural diagram of master-slave two-stage latch and latch kernel in common D flip-flop in the background technology;

Figure 3(a) is the logic structure of the third inverter in the common D flip-flop in the background technology, and Figure 3(b)-(d) are three implementations of input inverter or feedback inverter with clock control the logical structure of the form;

Fig. 4 is the logical structural diagram of latch kernel among the present invention;

Fig. 5 is the latch core logic structural diagram that utilizes the mode shown in Fig. 3 (b) to realize among the present invention;

Fig. 6 is the latch core logic structural diagram that utilizes the mode shown in Fig. 3 (c) to realize in the present invention;

FIG. 7 is a logic structure diagram of a latch core realized by using the method shown in FIG. 3( d ) in the present invention.

Detailed ways

Figure 1 is a logical structure diagram of a D flip-flop using a master-slave two-level latch structure.

Both the ordinary D flip-flop and the D flip-flop of the present invention are composed of a master latch (latch) and a slave latch connected in series. The master latch and the slave latch have exactly the same structure.

Fig. 2 is a logic structure diagram of a master-slave two-level latch and a latch core in a common D flip-flop in the background art.

The master latch or slave latch of an ordinary D flip-flop is composed of an input inverter with clock control, a feedback inverter with clock control and an inverter. The core of the latch consists of two inverters connected end to end.

Figure 3(a) is the third inverter, which is composed of a PMOS transistor and an NMOS transistor, wherein the drains of the PMOS transistor and the NMOS transistor are connected to form the output of the inverter, and the PMOS transistor and the NMOS transistor The gate is connected to form the input of the inverter; the source of the PMOS transistor is connected to the power supply, and the source of the NMOS transistor is connected to the ground. Figure 3(b)-(d) are 3 implementations of input inverter or feedback inverter with clock control. Looking at these three implementation forms, they all add a clock-controlled PMOS transistor P2 and a clock Controlled NMOS transistor N2; and its added transistors are either connected in series as shown in Figure 3(b)-(c), or connected in the form of transmission gates in the inverter as shown in Figure 3(d). output. It should be noted that the phase difference between the clock signal in the input inverter with clock control and the clock signal in the feedback inverter with clock control is 180 degrees. That is to say, when the gate of the PMOS transistor P2 in the input inverter with clock control is connected to an external signal _CLK , the gate of the PMOS transistor P2 in the feedback inverter with clock control is connected to the CLK signal via CLK. An inverter generates the non-signal of CLK superior.

Fig. 4 is the core of the latch in the present invention.

It is no longer composed of two end-to-end inverters like the core of the latch in the ordinary D flip-flop (shown in Figure 2), but consists of 6 PMOS transistors P1~P6 and 6 NMOS transistors N1~N6 constitute. The drain of N1 is connected to the drain of P1, node MN1, and connected to the gates of P2 and N4, the gate of N1 is connected to the drain of N2; the drain of N2 is connected to the drain of P2, node M1, And connected to the gate of P3 and N1, the gate of N2 is connected to the drain of N5; the drain of N3 is connected to the drain of P3, node MN2, and connected to the gate of P4 and N6, the gate of N3 The pole is connected to the drain of N4; the drain of N4 is connected to the drain of P4, node M2, and connected to the gate of P5 and N3, the gate of N4 is connected to the drain of N1; the drain of N5 is connected to P5 The drain of N6 is connected to the drain of node MN3, and connected to the gate of P6 and N2, the gate of N5 is connected to the drain of N6; the drain of N6 is connected to the drain of P6, node M3, and connected to P1 and N5 On the gate of N6, the gate of N6 is connected with the drain of N3. The gate of P1 is connected to the drain of N6, the drain of P1 is connected to the drain of N1; the gate of P2 is connected to the drain of N1, the drain of P2 is connected to the drain of N2; the gate of P3 is connected to the drain of N2 The drain of P3 is connected to the drain of N3; the gate of P4 is connected to the drain of N3, the drain of P4 is connected to the drain of N4; the gate of P5 is connected to the drain of N4, and the drain of P5 The drain of P6 is connected with the drain of N5; the gate of P6 is connected with the drain of N5, and the drain of P6 is connected with the drain of N6. The sources of the six PMOS transistors P1-P6 are all connected to the power supply VDD; the sources of the six NMOS transistors N1-N6 are all connected to the ground VSS.

5-7 are three specific implementation forms of the master (or slave) latch in the D flip-flop of the present invention.

The latch shown in Figure 5 adopts the implementation shown in Figure 3(b), and the sources of PMOS transistors P2, P4, and P6 are each connected to the power supply through a PMOS transistor controlled by a clock signal (ie, P7, P8, and P9). VDD, while the sources of the NMOS transistors N2, N4 and N6 are each connected to the ground VSS through an NMOS transistor (ie, N7, N8 and N9) controlled by a clock signal. The data input D of the latch is respectively connected to the nodes MN1, MN2 and MN3 through three clocked input inverters Inv1~Inv3, and the node M3 is selected as the output signal Q. Two such latches can be connected in series in the manner of Fig. 1 to form the D flip-flop of the present invention, and any node in the M1 or M2 or M3 nodes of the master latch is connected to the data input D of the slave latch. , and in this example, node M3 of the slave latch is selected as the output signal Q.

The latch shown in Figure 6 adopts the implementation shown in Figure 3(c). A PMOS transistor P10 controlled by a clock signal and a PMOS transistor controlled by a clock signal are sequentially inserted between the drain of the PMOS transistor P2 and the drain of the NMOS transistor N2. Between the NMOS transistor N10 controlled by the signal, the drain of the PMOS transistor P4 and the drain of the NMOS transistor N4, a PMOS transistor P11 controlled by a clock signal and an NMOS transistor N11 controlled by a clock signal, the drain of the PMOS transistor P6 A PMOS transistor P12 controlled by a clock signal and an NMOS transistor N12 controlled by a clock signal are sequentially inserted between the pole and the drain of the NMOS transistor N6. Similarly, the data input D of the latch is respectively connected to the nodes MN1, MN2 and MN3 through three input inverters Inv1~Inv3 with clock control, and the node M3 is selected as the output signal Q. Two such latches can be connected in series in the manner of Fig. 1 to form the D flip-flop of the present invention, and any node in the M1 or M2 or M3 nodes of the master latch is connected to the data input D of the slave latch. , and in this example, node M3 of the slave latch is selected as the output signal Q.

The latch shown in Figure 7 adopts the transmission gate method shown in Figure 3(d), that is, the control of the clock signal to the data path is realized through the transmission gates TG1, TG2 and TG3. The PMOS transistor P13 and the NMOS transistor N13 constitute the transmission gate TG1, the PMOS transistor P14 and the NMOS transistor N14 constitute the transmission gate TG2, and the PMOS transistor P15 and the NMOS transistor N15 constitute the transmission gate TG3. One end of the transmission gate TG1 is connected to the M1 node, and the other end is connected to the gates of the NMOS transistor N1 and the PMOS transistor P3; one end of the transmission gate TG2 is connected to the M2 node, and the other end is connected to the gates of the NMOS transistor N3 and the PMOS transistor P5; One end of the transmission gate TG3 is connected to the M3 node, and the other end is connected to the gates of the NMOS transistor N5 and the PMOS transistor P1. Similarly, the data input D of the latch is respectively connected to the nodes MN1, MN2 and MN3 through three clocked input inverters Inv1~Inv3, and the node M3 is selected as the output signal Q. Two such latches can be connected in series in the manner of Fig. 1 to form the D flip-flop of the present invention, and any node in the M1 or M2 or M3 nodes of the master latch is connected to the data input D of the slave latch. , and in this example, node M3 of the slave latch is selected as the output signal Q.

Claims (4)

1. a kind of primary particle inversion resistant d type flip flop is connected in series by main latch and from latch two stage latch, main latch Device is identical with the structure from latch, which is characterized in that main latch and latch kernel from latch are by 6 PMOS transistor P1~P6 and 6 NMOS transistor N1~N6 are constituted；The drain electrode of N1 is connected with the drain electrode of P1, node M N1, and even It is connected on the grid of P2 and N4, the grid of N1 is connected with the drain electrode of N2；The drain electrode of N2 is connected with the drain electrode of P2, node M 1, and even It is connected on the grid of P3 and N1, the grid of N2 is connected with the drain electrode of N5；The drain electrode of N3 is connected with the drain electrode of P3, node M N2, and even It is connected on the grid of P4 and N6, the grid of N3 is connected with the drain electrode of N4；The drain electrode of N4 is connected with the drain electrode of P4, node M 2, and even It is connected on the grid of P5 and N3, the grid of N4 is connected with the drain electrode of N1；The drain electrode of N5 is connected with the drain electrode of P5, node M N3, and even It is connected on the grid of P6 and N2, the grid of N5 is connected with the drain electrode of N6；The drain electrode of N6 is connected with the drain electrode of P6, node M 3, and even It is connected on the grid of P1 and N5, the grid of N6 is connected with the drain electrode of N3；The grid of P1 is connected with the drain electrode of N6, the drain electrode of P1 and N1 Drain electrode be connected；The grid of P2 is connected with the drain electrode of N1, and the drain electrode of P2 is connected with the drain electrode of N2；The drain electrode phase of the grid of P3 and N2 Even, the drain electrode of P3 is connected with the drain electrode of N3；The grid of P4 is connected with the drain electrode of N3, and the drain electrode of P4 is connected with the drain electrode of N4；P5's Grid is connected with the drain electrode of N4, and the drain electrode of P5 is connected with the drain electrode of N5；The grid of P6 is connected with the drain electrode of N5, the drain electrode of P6 and N6 Drain electrode be connected；The source electrode of 6 PMOS transistor P1~P6 meets power vd D；The source electrode of 6 NMOS transistor N1~N6 connects Ground VSS；

Main latch is connected respectively to latch from the data of latch input D by 3 input inverters with clock control Node M N1, MN2 and MN3 in device kernel, and respectively increase one by clock control at latch core nodes M1, M2 and M3 PMOS and NMOS transistor, any one node in M1 or M2 or the M3 node of final main latch are connected to from latch Data input D, and are that data export Q from any one node in M1 or M2 or the M3 node of latch.

2. primary particle inversion resistant d type flip flop as described in claim 1, which is characterized in that the latch core nodes M1, Respectively increase PMOS transistor P7, P8 and a P9 and NMOS transistor N7, N8 and N9 by clock control at M2 and M3；PMOS PMOS transistor, that is, P7, P8 and P9 that the source electrode of transistor P2, P4 and P6 are controlled each by one by clock signal, is connected to Power vd D, and the source electrode of NMOS transistor N2, N4 and N6 are each by a NMOS transistor by clock signal control N7, N8 and N9 are connected to ground VSS；Latch data input D by three input inverter Inv1 with clock control~ Inv3 is connected respectively to node M N1, MN2 and MN3.

3. primary particle inversion resistant d type flip flop as described in claim 1, which is characterized in that the latch core nodes M1, Respectively increase at M2 and M3 one by PMOS transistor P10, P11 and P12 and NMOS transistor N10, N11 of clock control and N12；One has been sequentially inserted between the drain electrode and the drain electrode of NMOS transistor N2 of PMOS transistor P2 to be controlled by clock signal PMOS transistor P10 and a NMOS transistor N10 controlled by clock signal, the drain electrode of PMOS transistor P4 and NMOS crystal It has been sequentially inserted into PMOS transistor P11 that one is controlled by clock signal between the drain electrode of pipe N4 and one is controlled by clock signal NMOS transistor N11, be sequentially inserted between the drain electrode and the drain electrode of NMOS transistor N6 of PMOS transistor P6 one by when The PMOS transistor P12 of a clock signal control and NMOS transistor N12 controlled by clock signal, the data input of latch D is connected respectively to node M N1, MN2 and MN3 by three input inverter Inv1~Inv3 with clock control.

4. primary particle inversion resistant d type flip flop as described in claim 1, which is characterized in that the latch core nodes M1, Respectively increase at M2 and M3 one by PMOS transistor P13, P14 and P15 and NMOS transistor N13, N14 of clock control and N15；PMOS transistor P13 and NMOS tube N13 constitutes transmission gate TG1, PMOS transistor P14 and NMOS tube N14 and constitutes transmission gate TG2, PMOS transistor P15 and NMOS tube N15 constitute transmission gate TG3；One end of transmission gate TG1 is connected to M1 nodes, the other end It is connected to the grid of NMOS transistor N1 and PMOS transistor P3；One end of transmission gate TG2 is connected to M2 nodes, other end connection To the grid of NMOS transistor N3 and PMOS transistor P5；One end of transmission gate TG3 is connected to M3 nodes, and the other end is connected to The grid of NMOS transistor N5 and PMOS transistor P1；Similarly, the data of latch input D by three with clock control Input inverter Inv1~Inv3 is connected respectively to node M N1, MN2 and MN3.