CN105896954A - Adaptive antistatic property-enhanced intelligent power module - Google Patents
Adaptive antistatic property-enhanced intelligent power module Download PDFInfo
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- CN105896954A CN105896954A CN201610347405.1A CN201610347405A CN105896954A CN 105896954 A CN105896954 A CN 105896954A CN 201610347405 A CN201610347405 A CN 201610347405A CN 105896954 A CN105896954 A CN 105896954A
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- 230000003044 adaptive effect Effects 0.000 title claims abstract description 170
- 230000005611 electricity Effects 0.000 claims abstract description 4
- 230000006978 adaptation Effects 0.000 claims description 4
- 230000003068 static effect Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 8
- 102100027206 CD2 antigen cytoplasmic tail-binding protein 2 Human genes 0.000 description 7
- 101000914505 Homo sapiens CD2 antigen cytoplasmic tail-binding protein 2 Proteins 0.000 description 7
- 101000739160 Homo sapiens Secretoglobin family 3A member 1 Proteins 0.000 description 7
- 102100037268 Secretoglobin family 3A member 1 Human genes 0.000 description 7
- 101100181929 Caenorhabditis elegans lin-3 gene Proteins 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 240000003550 Eusideroxylon zwageri Species 0.000 description 5
- 101000922137 Homo sapiens Peripheral plasma membrane protein CASK Proteins 0.000 description 5
- 102100031166 Peripheral plasma membrane protein CASK Human genes 0.000 description 5
- 240000003864 Ulex europaeus Species 0.000 description 5
- 235000010730 Ulex europaeus Nutrition 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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Abstract
The invention discloses an adaptive antistatic property-enhanced intelligent power module. An HO1 end, an HO2 end, an HO3 end, an LO1 end, an LO2 end, an LO3 end and a PFCO end of an HVIC tube are connected with a first input end, a second input end, a third input end, a fourth input end, a fifth input end, a sixth input end and a seventh input end of an adaptive circuit respectively; a first output end, a second output end, a third output end, a fourth output end, a fifth output end, a sixth output end and a seventh output end of the adaptive circuit are connected with gates of various IGBT tubes respectively; and diodes which are connected with a power supply end and a GND end respectively are arranged in the adaptive circuit. When the adaptive antistatic property-enhanced intelligent power module is not powered on, the gates of the IGBT tubes have electric connection, so that direct voltage impacts on the gates are reduced; the antistatic capacity of the gates of the IGBT tubes is improved; and the probability that the intelligent power module is broken down by static electricity is reduced.
Description
Technical field
The present invention relates to the design field of SPM, the protection circuit of a kind of SPM and the design of electrostatic suppression circuit.
Background technology
SPM, i.e. IPM(Intelligent Power Module), it is a kind of power drive series products that power electronics and integrated circuit technique are combined.SPM integrates device for power switching and high-voltage driving circuit, and in keep overvoltage, overcurrent and the failure detector circuit such as overheated.On the one hand SPM receives the control signal of MCU, drives subsequent conditioning circuit work, on the other hand sends the state detection signal of system back to MCU.Compared with traditional discrete scheme, SPM wins increasing market with its advantage such as high integration, high reliability, it is particularly suitable for driving the converter of motor and various inverter, it it is frequency control, metallurgical machinery, electric propulsion, servo-drive, a kind of desired power level electronic device of frequency-conversion domestic electric appliances.
The circuit structure of the existing SPM 100 for fields such as convertible frequency air-conditioners is as shown in Figure 1:
The VCC end of HVIC pipe 101 is as the low-pressure area power supply anode VDD of described SPM 100, and VDD is generally 15V;
Having boostrap circuit inside described HVIC pipe 101, boostrap circuit structure is as follows:
VCC end is connected with bootstrap diode 102, bootstrap diode 103, the anode of bootstrap diode 104;
The negative electrode of described bootstrap diode 102 is connected with the VB1 of described HVIC pipe 101;
The negative electrode of described bootstrap diode 103 is connected with the VB2 of described HVIC pipe 101;
The negative electrode of described bootstrap diode 104 is connected with the VB3 of described HVIC pipe 101;
The HIN1 end of described HVIC pipe 101 is as brachium pontis input UHIN in the press U phase of described SPM 100;
The HIN2 end of described HVIC pipe 101 is as brachium pontis input VHIN in the press V phase of described SPM 100;
The HIN3 end of described HVIC pipe 101 is as brachium pontis input WHIN in the press W phase of described SPM 100;
The LIN1 end of described HVIC pipe 101 is as the lower brachium pontis input ULIN of press U phase of described SPM 100;
The LIN2 end of described HVIC pipe 101 is as the lower brachium pontis input VLIN of press V phase of described SPM 100;
The LIN3 end of described HVIC pipe 101 is as the lower brachium pontis input WLIN of press W phase of described SPM 100;
The PFCINP end of described HVIC pipe 101 controls input PFCIN as the PFC of described SPM 100;
Here, described SPM 100 UHIN, VHIN, WHIN, ULIN, VLIN, WLIN six tunnel input and PFCIN end receive 0V or 5V input signal;
The GND end of described HVIC pipe 101 is as the low-pressure area power supply negative terminal COM of described SPM 100;
The ITRIP end of described HVIC pipe 101 is as the current detecting vb end MTRIP of described SPM 100;
The VB1 end of described HVIC pipe 101 connects one end of electric capacity 131, and as the press U phase higher-pressure region power supply anode UVB of described SPM 100;
The HO1 end of described HVIC pipe 101 is connected with the grid of brachium pontis IGBT pipe 121 in press U phase;
The VS1 end of described HVIC pipe 101 is connected with the emitter-base bandgap grading of described IGBT pipe 121, the anode of FRD pipe 111, the lower colelctor electrode of brachium pontis IGBT pipe 124 of press U phase, the negative electrode of FRD pipe 114, the other end of described electric capacity 131, and as the press U phase higher-pressure region power supply negative terminal UVS of described SPM 100;
The VB2 end of described HVIC pipe 101 connects one end of electric capacity 132, as the press U phase higher-pressure region power supply anode VVB of described SPM 100;
The HO2 end of described HVIC pipe 101 is connected with the grid of brachium pontis IGBT pipe 122 in press V phase;
The VS2 end of described HVIC pipe 101 is connected with the emitter-base bandgap grading of described IGBT pipe 122, the anode of FRD pipe 112, the lower colelctor electrode of brachium pontis IGBT pipe 125 of press V phase, the negative electrode of FRD pipe 115, the other end of described electric capacity 132, and as the press V phase higher-pressure region power supply negative terminal VVS of described SPM 100;
The VB3 end of described HVIC pipe 101 connects one end of electric capacity 133, as the press W phase higher-pressure region power supply anode WVB of described SPM 100;
The HO3 end of described HVIC pipe 101 is connected with the grid of brachium pontis IGBT pipe 123 in press W phase;
The VS3 end of described HVIC pipe 101 is connected with the emitter-base bandgap grading of described IGBT pipe 123, the anode of FRD pipe 113, the lower colelctor electrode of brachium pontis IGBT pipe 126 of press W phase, the negative electrode of FRD pipe 116, the other end of described electric capacity 133, and as the press W phase higher-pressure region power supply negative terminal WVS of described SPM 100;
The LO1 end of described HVIC pipe 101 is connected with the grid of described IGBT pipe 124;
The LO2 end of described HVIC pipe 101 is connected with the grid of described IGBT pipe 125;
The LO3 end of described HVIC pipe 101 is connected with the grid of described IGBT pipe 126;
The emitter-base bandgap grading of described IGBT pipe 124 is connected with the anode of described FRD pipe 114, and as the press U phase low reference voltage end UN of described SPM 100;
The emitter-base bandgap grading of described IGBT pipe 125 is connected with the anode of described FRD pipe 115, and as the press V phase low reference voltage end VN of described SPM 100;
The emitter-base bandgap grading of described IGBT pipe 126 is connected with the anode of described FRD pipe 116, and as the press W phase low reference voltage end WN of described SPM 100;
The PFCO end of described HVIC pipe 101 is connected with the grid of IGBT pipe 127;
The emitter-base bandgap grading of described IGBT pipe 127 is connected with the anode of FRD pipe 117, and as the PFC low reference voltage end-VP of described SPM 100;
The colelctor electrode of described IGBT pipe 127 is connected with negative electrode, the anode of FRD pipe 131 of described FRD pipe 117, and as the PFC end of described SPM 100;
The negative electrode of described FRD pipe 131, the colelctor electrode of described IGBT pipe 121, the negative electrode of described FRD pipe 111, the colelctor electrode of described IGBT pipe 122, the negative electrode of described FRD pipe 112, the colelctor electrode of described IGBT pipe 123, the negative electrode of described FRD pipe 113 are connected, and the high voltage input P, P as described SPM 100 typically meets 300V.
The effect of described HVIC pipe 101 is:
VDD is the power supply anode of described HVIC pipe 101, and GND is the power supply negative terminal of described HVIC pipe 101;VDD-GND voltage is generally 15V;
VB1 and VS1 is respectively positive pole and the negative pole of the power supply of U phase higher-pressure region, and HO1 is the outfan of U phase higher-pressure region;
VB2 and VS2 is respectively positive pole and the negative pole of the power supply of V phase higher-pressure region, and HO2 is the outfan of V phase higher-pressure region;
VB3 and VS3 is respectively positive pole and the negative pole of the power supply of U phase higher-pressure region, and HO3 is the outfan of W phase higher-pressure region;
LO1, LO2, LO3 are respectively U phase, V phase, the outfan of W phase low-pressure area;
PFCO is the outfan of PFC drive circuit;
The logic input signal of the 0 or 5V of input HIN1, HIN2, HIN3 is passed to outfan HO1, HO2, HO3 respectively, the signal of LIN1, LIN2, LIN3 passes to outfan LO1, LO2, LO3 respectively, the signal of PFCINP passes to outfan PFCO, wherein HO1 be the logic output signal of VS1 or VS1+15V, HO2 be the logic output signal of VS2 or VS2+15V, HO3 be the logic output signal of VS3 or VS3+15V, LO1, LO2, LO3, PFCO are the logic output signals of 0 or 15V.
The input signal of same phase can not be high level simultaneously, i.e. HIN1 and LIN1, HIN2 and LIN2, HIN3 and LIN3 can not be high level simultaneously.
Described UVS, VVS, WVS and PFC connect inductive load.
PFCINP is then frequently switched between low and high level by certain frequency, make that described IGBT pipe 127 is continuously on off state and described FRD pipe 131 is continuously in freewheeling state, this frequency be generally LIN1 ~ LIN3,2 ~ 4 times of HIN1 ~ HIN3 switching frequency, and the most directly contact with the switching frequency of LIN1 ~ LIN3, HIN1 ~ HIN3.
nullVisible,The described IGBT pipe 124 of existing SPM 100、Described IGBT pipe 125、Described IGBT pipe 126、The emitter-base bandgap grading of described IGBT pipe 127 is directly as the pin of described SPM 100,During described SPM 100 assembles,Owing to touching operating board、Touch the reasons such as workman's body part,Described SPM 100 is highly susceptible to electrostatic and threatens,These electrostatic are if there is at UN、VN、WN、Between-VP pin and COM pin,Be equivalent to electrostatic directly to described IGBT pipe 124、Described IGBT pipe 125、Described IGBT pipe 126、The grid of described IGBT pipe 127 constitutes impact,The oxygen of deleting of IGBT pipe is to be easiest to by the position of electrostatic breakdown,So the defect being damaged by static electricity during the upper existence of the design of existing SPM 100 is mounted.
In fact, if this damage makes IGBT pipe complete failure, detection after SPM assembles can be detected to be avoided coming into the market, if but this damage only makes IGBT pipe generation micro-damage, then the detection after SPM assembling would become hard to be found, come into the market and can cause the initial failure of goods, IGBT pipe belongs to power device, high-voltage great-current is had to flow through, easily there is overheated burning in IGBT tube failure moment, whole SPM is caused to burst, the heat localization of SPM even can cause SPM to explode, the security incidents such as breaking out of fire are understood time serious.The antistatic effect of SPM can be promoted, become the important topic affecting SPM popularization and application.
Therefore, prior art existing defects, need to improve.
Summary of the invention
The technical problem to be solved is: provide the SPM of a kind of reliability, high-adaptability, can ensure that SPM, on the premise of antistatic effect is greatly improved, improves the performance of SPM.
Technical scheme is as follows: the SPM that a kind of self adaptation antistatic strengthens, including: HVIC pipe 1101;The IGBT pipe 1121 that is connected with HVIC pipe 1101 respectively, IGBT pipe 1122, IGBT pipe 1123, IGBT pipe 1124, IGBT pipe 1125, IGBT pipe 1126 and IGBT pipe 1127;And adaptive circuit 1105;Wherein, the HO1 end of HVIC pipe 1101 is connected with the first input end of adaptive circuit 1105, and the first outfan of adaptive circuit 1105 is connected with the grid of brachium pontis IGBT pipe 1121 in press U phase;The HO2 end of HVIC pipe 1101 is connected with the second input of adaptive circuit 1105, and the second outfan of adaptive circuit 1105 is connected with the grid of brachium pontis IGBT pipe 1122 in press V phase;The HO3 end of HVIC pipe 1101 is connected with the 3rd input of adaptive circuit 1105, and the 3rd outfan of adaptive circuit 1105 is connected with the grid of brachium pontis IGBT pipe 1123 in press W phase;The LO1 end of HVIC pipe 1101 is connected with the four-input terminal of adaptive circuit 1105, and the 4th outfan of adaptive circuit 1105 is connected with the grid of IGBT pipe 1124;The LO2 end of HVIC pipe 1101 is connected with the 5th input of adaptive circuit 1105, and the 5th outfan of adaptive circuit 1105 is connected with the grid of IGBT pipe 1125;The LO3 end of HVIC pipe 1101 is connected with the 6th input of adaptive circuit 1105, and the 6th outfan of adaptive circuit 1105 is connected with the grid of IGBT pipe 1126;The PFCO end of HVIC pipe 1101 is connected with the 7th input of adaptive circuit 1105, and the 7th outfan of adaptive circuit 1105 is connected with the grid of IGBT pipe 1127;Further, adaptive circuit 1105 is internal is additionally provided with diode 2011 and diode 2013, and wherein, the anode of diode 2011 meets GND, and the negative electrode of diode 2013 meets VCC.
It is applied to technique scheme, in described SPM, when it not yet powers on, first outfan of adaptive circuit 1105, the second outfan, the 3rd outfan, the 4th outfan, the 5th outfan, the 6th outfan, the 7th outfan produce electrical connection and also present high-impedance state, and with the first input end of adaptive circuit (1105), the second input, the 3rd input, four-input terminal, the 5th input, the 6th input, the 7th input signal unrelated.
nullIt is applied to each technique scheme,In described SPM,When after its electricity,The signal of the first outfan of adaptive circuit 1105 and the signal homophase of the first input end of adaptive circuit 1105,The signal homophase of the second input of the signal of the second outfan of adaptive circuit 1105 and described adaptive circuit 1105,The signal of the 3rd outfan of adaptive circuit 1105 and the signal homophase of the 3rd input of adaptive circuit 1105,The signal of the 4th outfan of adaptive circuit 1105 and the signal homophase of the four-input terminal of adaptive circuit 1105,The signal of the 5th outfan of adaptive circuit 1105 and the signal homophase of the 5th input of adaptive circuit 1105,The signal of the 6th outfan of adaptive circuit 1105 and the signal homophase of the 6th input of adaptive circuit 1105,The signal of the 7th outfan of adaptive circuit 1105 and the signal homophase of the 7th input of adaptive circuit 1105.
It is applied to each technique scheme, in described SPM, adaptive circuit 1105 is internally provided with resistance 2016, resistance 2012, voltage comparator 2015, not gate 2010, not gate 2017, resistance 2021, resistance 2022, resistance 2023, resistance 2024, resistance 2025, resistance 2026, resistance 2027 and analog switch 2001, analog switch 2002, analog switch 2003, analog switch 2004, analog switch 2005, analog switch 2006 and analog switch 2007;Wherein;Resistance 2,016 1 terminates VCC, resistance 2016 other end connecting resistance 2012 and voltage comparator 2015;The output termination not gate 2010 of voltage comparator 2015, the input of the output termination not gate 2017 of not gate 2010;The outfan of not gate 2017 connects the control end of analog switch 2001, the control end of analog switch 2002, the control end of analog switch 2003, the control end of analog switch 2004, the control end of analog switch 2005, the control end of analog switch 2006 and the control end of analog switch 2007 respectively;The first input end of adaptive circuit 1105 is connected with one end of resistance 2021, the first input end of adaptive circuit 1105 is connected with one end of resistance 2021, the first input end of adaptive circuit 1105 is connected with one end of resistance 2021, second input of adaptive circuit 1105 is connected with one end of resistance 2022, 3rd input of adaptive circuit 1105 is connected with one end of resistance 2023, the four-input terminal of adaptive circuit 1105 is connected with one end of resistance 2024, 5th input of adaptive circuit 1105 is connected with one end of resistance 2025, 6th input of adaptive circuit 1105 is connected with one end of resistance 2026, 7th input of adaptive circuit 1105 is connected with one end of resistance 2027;And, first outfan that fixing end is adaptive circuit 1105 of analog switch 2001, the 2nd 1 outfan that fixing end is adaptive circuit 1105 of analog switch 2002, the 3rd outfan that fixing end is adaptive circuit 1105 of analog switch 2003, the 4th outfan that fixing end is adaptive circuit 1105 of analog switch 2004, the 5th outfan that fixing end is adaptive circuit 1105 of analog switch 2005, the 6th outfan that fixing end is adaptive circuit 1105 of analog switch 2006, the 7th outfan that fixing end is adaptive circuit 1105 of analog switch 2007;Further, 0 selection end of analog switch 2001,0 selection end of analog switch 2002,0 selection end of analog switch 2003,0 selection end of analog switch 2004,0 selection end of analog switch 2005,0 selection end of analog switch 2006,0 selection end of analog switch 2001 be connected and connect the negative electrode of diode 2011, diode 2013 anode connected.
It is applied to each technique scheme, in described SPM, the resistance that resistance 2016 and resistance 2012 select resistance to be 30k Ω.
It is applied to each technique scheme, in described SPM, resistance 2021, resistance 2022, resistance 2023, resistance 2024, resistance 2025, the resistance of resistance 2026 are 100 Ω, the 7th outfan making adaptive circuit 1105 is connected with the 7th input of adaptive circuit 1105 by resistance 2027, and the resistance of resistance 2027 is 50 Ω.
nullUse such scheme,The SPM of the present invention is compared with existing SPM,When SPM not yet powers on,I.e. it is most susceptible to the occasion of electrostatic accumulation and electric discharge,The grid of IGBT pipe is because having electrical connection,Be equivalent to increase grid oxygen area,And because it is forward diode state to power end,It is backward diode state to GND end,Even if making electric discharge,Also can take the lead in being discharged by diode,Reduce the direct voltage to grid to impact,Improve the antistatic effect of the grid of the internal IGBT pipe of SPM,And,Due to HVIC pipe HO1、HO2、HO3、LO1、LO2、LO3、PFCO end the most respectively with corresponding IGBT pipe and after SPM powers on,Effect due to motional electric field,Electrostatic cannot gather,So,The outfan of the HVIC pipe of SPM is the lowest by the chance of electrostatic breakdown after re-establishing with the grid of IGBT pipe and electrically connecting after the power-up.It is thus possible to reduce the SPM of the present invention by the probability of electrostatic breakdown, ensure that the quality that SPM dispatches from the factory, this is for maintaining application system stability, it is provided that the user satisfaction of product, reduce product to complain, safeguard that brand image is greatly facilitated effect.
Accompanying drawing explanation
Fig. 1 is the structural circuit figure of prior art;
Fig. 2 is the structural circuit figure of the present invention;
Fig. 3 is the internal structure circuit diagram of adaptive circuit in the present invention.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
Present embodiments providing the SPM that a kind of self adaptation antistatic strengthens, SPM 1100 structure chart is as shown in Figure 2.Wherein, the VCC end of HVIC pipe 1101 is as the low-pressure area power supply anode VDD of described SPM 1100, and VDD is generally 15V;
Described HVIC pipe 1101 is internal also has boostrap circuit structure as follows:
VCC end is connected with bootstrap diode 1102, bootstrap diode 1103, the anode of bootstrap diode 1104;
The negative electrode of described bootstrap diode 1102 is connected with the VB1 of described HVIC pipe 1101;
The negative electrode of described bootstrap diode 1103 is connected with the VB2 of described HVIC pipe 1101;
The negative electrode of described bootstrap diode 1104 is connected with the VB3 of described HVIC pipe 1101.
The HIN1 end of described HVIC pipe 1101 is brachium pontis input UHIN in the U phase of described SPM 1100;
The HIN2 end of described HVIC pipe 1101 is brachium pontis input VHIN in the V phase of described SPM 1100;
The HIN3 end of described HVIC pipe 1101 is brachium pontis input WHIN in the W phase of described SPM 1100;
The LIN1 end of described HVIC pipe 1101 is the lower brachium pontis input ULIN of U phase of described SPM 1100;
The LIN2 end of described HVIC pipe 1101 is the lower brachium pontis input VLIN of V phase of described SPM 1100;
The LIN3 end of described HVIC pipe 1101 is the lower brachium pontis input WLIN of W phase of described SPM 1100;
The PFCINP end of described HVIC pipe 1101 controls input PFCIN as the PFC of described SPM 100;
Here, described SPM 1100 UHIN, VHIN, WHIN, ULIN, VLIN, WLIN six tunnel input and PFCIN end receive 0V or 5V input signal;
The ITRIP end of described HVIC pipe 1101 is the MTRIP end of described SPM 1100;
Here, described SPM 1100 UHIN, VHIN, WHIN, ULIN, VLIN, WLIN six tunnel input receive 0V or 5V input signal;
The GND end of described HVIC pipe 1101 is as the low-pressure area power supply negative terminal COM of described SPM 1100;
The VB1 end of described HVIC pipe 1101 connects one end of electric capacity 1131, and as the press U phase higher-pressure region power supply anode UVB of described SPM 1100;
The HO1 end of described HVIC pipe 1101 is connected with the first input end of adaptive circuit 1105, and the first outfan of described adaptive circuit 1105 is connected with the grid of brachium pontis IGBT pipe 1121 in press U phase;
The VS1 end of described HVIC pipe 1101 is connected with the emitter-base bandgap grading of described IGBT pipe 1121, the anode of FRD pipe 1111, the lower colelctor electrode of brachium pontis IGBT pipe 1124 of press U phase, the negative electrode of FRD pipe 1114, the other end of described electric capacity 1131, and as the press U phase higher-pressure region power supply negative terminal UVS of described SPM 1100;
The VB2 end of described HVIC pipe 1101 connects one end of electric capacity 1132, as the press U phase higher-pressure region power supply anode VVB of described SPM 1100;
The HO2 end of described HVIC pipe 1101 is connected with the second input of described adaptive circuit 1105, and the second outfan of described adaptive circuit 1105 is connected with the grid of brachium pontis IGBT pipe 1122 in press V phase;
The VS2 end of described HVIC pipe 1101 is connected with the emitter-base bandgap grading of described IGBT pipe 1122, the anode of FRD pipe 1112, the lower colelctor electrode of brachium pontis IGBT pipe 1125 of press V phase, the negative electrode of FRD pipe 1115, the other end of described electric capacity 1132, and as the press V phase higher-pressure region power supply negative terminal VVS of described SPM 1100;
The VB3 end of described HVIC pipe 1101 connects one end of electric capacity 1133, as the press W phase higher-pressure region power supply anode WVB of described SPM 1100;
The HO3 end of described HVIC pipe 1101 is connected with the 3rd input of described adaptive circuit 1105, and the 3rd outfan of described adaptive circuit 1105 is connected with the grid of brachium pontis IGBT pipe 1123 in press W phase;
The VS3 end of described HVIC pipe 1101 is connected with the emitter-base bandgap grading of described IGBT pipe 1123, the anode of FRD pipe 1113, the lower colelctor electrode of brachium pontis IGBT pipe 1126 of press W phase, the negative electrode of FRD pipe 1116, the other end of described electric capacity 1133, and as the press W phase higher-pressure region power supply negative terminal WVS of described SPM 1100;
The LO1 end of described HVIC pipe 1101 is connected with the four-input terminal of described adaptive circuit 1105, and the 4th outfan of described adaptive circuit 1105 is connected with the grid of described IGBT pipe 1124;
The LO2 end of described HVIC pipe 1101 is connected with the 5th input of described adaptive circuit 1105, and the 5th outfan of described adaptive circuit 1105 is connected with the grid of described IGBT pipe 1125;
The LO3 end of described HVIC pipe 1101 is connected with the 6th input of described adaptive circuit 1105, and the 6th outfan of described adaptive circuit 1105 is connected with the grid of described IGBT pipe 1126;
The emitter-base bandgap grading of described IGBT pipe 1124 is connected with the anode of described FRD pipe 1114, and as the UN end of described SPM 1100;
The emitter-base bandgap grading of described IGBT pipe 1125 is connected with the anode of described FRD pipe 1115, and as the VN end of described SPM 1100;
The emitter-base bandgap grading of described IGBT pipe 1126 is connected with the anode of described FRD pipe 1116, and as the WN end of described SPM 1100;
The PFCO end of described HVIC pipe 1101 is connected with the 7th input of described adaptive circuit 1105, and the 7th outfan of described adaptive circuit 1105 is connected with the grid of IGBT pipe 1127;
The emitter-base bandgap grading of described IGBT pipe 1127 is connected with the anode of FRD pipe 1117, and as-VP the end of described SPM 1100;
The colelctor electrode of described IGBT pipe 1127 is connected with negative electrode, the anode of FRD pipe 1131 of described FRD pipe 1117, and as the PFC end of described SPM 1100;
The negative electrode of described FRD pipe 1131, the colelctor electrode of described IGBT pipe 1121, the negative electrode of described FRD pipe 1111, the colelctor electrode of described IGBT pipe 1122, the negative electrode of described FRD pipe 1112, the colelctor electrode of described IGBT pipe 1123, the negative electrode of described FRD pipe 1113 are connected, and the high voltage input P, P as described SPM 1100 typically meets 300V.
The effect of described HVIC pipe 1101 is:
VDD is described HVIC pipe 1101 power supply anode, and GND is the power supply negative terminal of described HVIC pipe 1101;VDD-GND voltage is generally 15V;
VB1 and VS1 is respectively positive pole and the negative pole of the power supply of U phase higher-pressure region, and HO1 is the outfan of U phase higher-pressure region;
VB2 and VS2 is respectively positive pole and the negative pole of the power supply of V phase higher-pressure region, and HO2 is the outfan of V phase higher-pressure region;
VB3 and VS3 is respectively positive pole and the negative pole of the power supply of U phase higher-pressure region, and HO3 is the outfan of W phase higher-pressure region;
LO1, LO2, LO3 are respectively U phase, V phase, the outfan of W phase low-pressure area;
PFCO is the outfan of PFC drive circuit;
The logic input signal of the 0 or 5V of input HIN1, HIN2, HIN3 is passed to outfan HO1, HO2, HO3 respectively, the signal of LIN1, LIN2, LIN3 passes to outfan LO1, LO2, LO3 respectively, the signal of PFCINP passes to outfan PFCO, wherein HO1 be the logic output signal of VS1 or VS1+15V, HO2 be the logic output signal of VS2 or VS2+15V, HO3 be the logic output signal of VS3 or VS3+15V, LO1, LO2, LO3, PFCO are the logic output signals of 0 or 15V.
And the effect of described adaptive circuit 1105 is:
When described SPM 1100 not yet powers on, first outfan of described adaptive circuit 1105, the second outfan, the 3rd outfan, the 4th outfan, the 5th outfan, the 6th outfan, the 7th outfan produce electrical connection and are forward diode state to power end, be backward diode state to GND end, and with the first input end of described adaptive circuit 1105, the second input, the 3rd input, four-input terminal, the 5th input, the 6th input, the 7th input signal unrelated;
nullAfter described SPM 1100 powers on,The signal homophase of the first input end of the signal of the first outfan of described adaptive circuit 1105 and described adaptive circuit 1105,The signal homophase of the second input of the signal of the second outfan of described adaptive circuit 1105 and described adaptive circuit 1105,The signal of the 3rd outfan of described adaptive circuit 1105 and the signal homophase of the 3rd input of described adaptive circuit 1105,The signal of the 4th outfan of described adaptive circuit 1105 and the signal homophase of the four-input terminal of described adaptive circuit 1105,The signal of the 5th outfan of described adaptive circuit 1105 and the signal homophase of the 5th input of described adaptive circuit 1105,The signal of the 6th outfan of described adaptive circuit 1105 and the signal homophase of the 6th input of described adaptive circuit 1105,The signal of the 7th outfan of described adaptive circuit 1105 and the signal homophase of the 7th input of described adaptive circuit 1105.
Described adaptive circuit 1105 can be the structure such as Fig. 3, as follows:
One end of VCC connecting resistance 2016;
One end of the other end connecting resistance 2012 of described resistance 2016 and the positive input terminal of voltage comparator 2015;
Another termination COM of described resistance 2012;
The anode of the negative input termination voltage source 2014 of described voltage comparator 2015;
The negative terminal of described voltage source 2014 meets COM;
The input of the output termination not gate 2010 of described voltage comparator 2015;
The input of the output termination not gate 2017 of described not gate 2010;
The output of described not gate 2017 terminates the control end, the control end of described analog switch 2007 that control end, described analog switch 2006 that control end, described analog switch 2005 that control end, described analog switch 2004 that control end, described analog switch 2003 of the control end of described analog switch 2001, described analog switch 2002.
The first input end of described adaptive circuit 1105 is connected with one end of resistance 2021;
The other end of described resistance 2021 is connected with 1 selection end of analog switch 2001;
The fixing end of described analog switch 2001 is the first outfan of described adaptive circuit 1105;
Second input of described adaptive circuit 1105 is connected with one end of resistance 2022;
The other end of described resistance 2022 is connected with 1 selection end of analog switch 2002;
The fixing end of described analog switch 2002 is the second outfan of described adaptive circuit 1105;
3rd input of described adaptive circuit 1105 is connected with one end of resistance 2023;
The other end of described resistance 2023 is connected with 1 selection end of analog switch 2003;
The fixing end of described analog switch 2003 is the 3rd outfan of described adaptive circuit 1105;
The described four-input terminal of adaptive circuit 1105 is connected with one end of resistance 2024;
The other end of described resistance 2024 is connected with 1 selection end of analog switch 2004;
The fixing end of described analog switch 2004 is the 4th outfan of described adaptive circuit 1105;
5th input of described adaptive circuit 1105 is connected with one end of resistance 2025;
The other end of described resistance 2025 is connected with 1 selection end of analog switch 2005;
The fixing end of described analog switch 2005 is the 5th outfan of described adaptive circuit 1105;
6th input of described adaptive circuit 1105 is connected with one end of resistance 2026;
The other end of described resistance 2026 is connected with 1 selection end of analog switch 2006;
The fixing end of described analog switch 2006 is the 6th outfan of described adaptive circuit 1105;
7th input of described adaptive circuit 1105 is connected with one end of resistance 2027;
The other end of described resistance 2027 is connected with 1 selection end of analog switch 2007;
The fixing end of described analog switch 2007 is the 7th outfan of described adaptive circuit 1105;
0 selection end of described analog switch 2001,0 selection end of described analog switch 2002,0 selection end of described analog switch 2003,0 selection end of described analog switch 2004,0 selection end of described analog switch 2005,0 selection end of described analog switch 2006,0 selection end of described analog switch 2007 be connected and connect the negative electrode of diode 2011, diode 2013 anode connected;
The anode of described diode 2011 meets GND;
The negative electrode of described diode 2013 meets VCC.
Described resistance 2016 and described resistance 2012 are it is contemplated that the resistance that selects resistance to be 30k Ω, and described voltage source 2014 is it is contemplated that be designed as 5.5V ± 1V;Then VCC is fully powered up reach about 15V before, described voltage comparator 2015 output low level, thus described not gate 2017 output low level, the low level of described not gate 2017 makes the first outfan of described adaptive circuit 1105, the second outfan, the 3rd outfan, the 4th outfan, the 5th outfan, the 6th outfan, the 7th outfan be connected with described diode 2011 and described diode 2013 simultaneously, and described diode 2011 and described diode 2013 may be designed as the BASE diode of square area 50 m × 50 m;nullVCC is fully powered up reach about 15V after,Described voltage comparator 2015 exports high level,Thus described not gate 2017 exports high level,So that the first outfan of described adaptive circuit 1105 is connected with the first input end of described adaptive circuit 1105 by described resistance 2021,The second outfan making described adaptive circuit 1105 is connected with the second input of described adaptive circuit 1105 by described resistance 2022,The 3rd outfan making described adaptive circuit 1105 is connected with the 3rd input of described adaptive circuit 1105 by described resistance 2023,The 4th outfan making described adaptive circuit 1105 is connected with the four-input terminal of described adaptive circuit 1105 by described resistance 2024,The 5th outfan making described adaptive circuit 1105 is connected with the 5th input of described adaptive circuit 1105 by described resistance 2025,The 6th outfan making described adaptive circuit 1105 is connected with the 6th input of described adaptive circuit 1105 by described resistance 2026,At this,Described resistance 2021、Described resistance 2022、Described resistance 2023、Described resistance 2024、Described resistance 2025、Described resistance 2026 is it is contemplated that be designed as about 100 Ω,And make the 7th outfan of described adaptive circuit 1105 be connected with the 7th input of described adaptive circuit 1105 by described resistance 2027,The resistance of described resistance 2027 is it is contemplated that be designed as the half of described resistance 2026 resistance,I.e. 50 Ω.
These are only presently preferred embodiments of the present invention, be not limited to the present invention, all any amendment, equivalent and improvement etc. made within the spirit and principles in the present invention, should be included within the scope of the present invention.
Claims (6)
1. the SPM that a self adaptation antistatic strengthens, it is characterised in that including:
HVIC manages (1101);
IGBT pipe (1121), IGBT pipe (1122), IGBT pipe (1123), IGBT pipe (1124), IGBT pipe (1125), IGBT pipe (1126) and IGBT pipe (1127) being connected with HVIC pipe (1101) respectively;
And adaptive circuit (1105);
Wherein, the HO1 end of HVIC pipe (1101) is connected with the first input end of adaptive circuit (1105), and the first outfan of adaptive circuit (1105) is connected with the grid of brachium pontis IGBT pipe (1121) in press U phase;
The HO2 end of HVIC pipe (1101) is connected with the second input of adaptive circuit (1105), and the second outfan of adaptive circuit (1105) is connected with the grid of brachium pontis IGBT pipe (1122) in press V phase;
The HO3 end of HVIC pipe (1101) is connected with the 3rd input of adaptive circuit (1105), and the 3rd outfan of adaptive circuit (1105) is connected with the grid of brachium pontis IGBT pipe (1123) in press W phase;
The LO1 end of HVIC pipe (1101) is connected with the four-input terminal of adaptive circuit 1105, and the 4th outfan of adaptive circuit (1105) is connected with the grid of IGBT pipe (1124);
The LO2 end of HVIC pipe (1101) is connected with the 5th input of adaptive circuit 1105, and the 5th outfan of adaptive circuit (1105) is connected with the grid of IGBT pipe (1125);
The LO3 end of HVIC pipe (1101) is connected with the 6th input of adaptive circuit (1105), and the 6th outfan of adaptive circuit (1105) is connected with the grid of IGBT pipe (1126);
The PFCO end of HVIC pipe (1101) is connected with the 7th input of adaptive circuit (1105), and the 7th outfan of adaptive circuit (1105) is connected with the grid of IGBT pipe (1127);
Further, adaptive circuit (1105) is internal is additionally provided with diode (2011) and diode (2013), and wherein, the anode of diode (2011) meets GND, and the negative electrode of diode (2013) meets VCC.
SPM the most according to claim 1, it is characterized in that, when it not yet powers on, first outfan of adaptive circuit (1105), the second outfan, the 3rd outfan, the 4th outfan, the 5th outfan, the 6th outfan, the 7th outfan produce electrical connection and also present high-impedance state, and with the first input end of adaptive circuit (1105), the second input, the 3rd input, four-input terminal, the 5th input, the 6th input, the 7th input signal unrelated.
nullSPM the most according to claim 1,It is characterized in that,When after its electricity,The signal homophase of the first input end of the signal of the first outfan of adaptive circuit (1105) and adaptive circuit (1105),The signal homophase of the second input of the signal of the second outfan of adaptive circuit (1105) and described adaptive circuit (1105),The signal of the 3rd outfan of adaptive circuit (1105) and the signal homophase of the 3rd input of adaptive circuit (1105),The signal of the 4th outfan of adaptive circuit 1105 and the signal homophase of the four-input terminal of adaptive circuit (1105),The signal of the 5th outfan of adaptive circuit (1105) and the signal homophase of the 5th input of adaptive circuit (1105),The signal of the 6th outfan of adaptive circuit (1105) and the signal homophase of the 6th input of adaptive circuit (1105),The signal of the 7th outfan of adaptive circuit (1105) and the signal homophase of the 7th input of adaptive circuit (1105).
SPM the most according to claim 1, it is characterized in that, adaptive circuit (1105) is internally provided with resistance (2016), resistance (2012), voltage comparator (2015), not gate (2010), not gate (2017), resistance (2021), resistance (2022), resistance (2023), resistance (2024), resistance (2025), resistance (2026), resistance (2027), and analog switch (2001), analog switch (2002), analog switch (2003), analog switch (2004), analog switch (2005), analog switch (2006) and analog switch (2007);
Wherein;Resistance (2016) one terminates VCC, resistance (2016) other end connecting resistance (2012) and voltage comparator (2015);Output termination not gate (2010) of voltage comparator (2015), the input of output termination not gate (2017) of not gate (2010);The outfan of not gate (2017) connects the control end of analog switch (2001), the control end of analog switch (2002), the control end of analog switch (2003), the control end of analog switch (2004), the control end of analog switch (2005), the control end of analog switch (2006) and the control end of analog switch (2007) respectively;
nullThe first input end of adaptive circuit (1105) is connected with one end of resistance (2021),The first input end of adaptive circuit (1105) is connected with one end of resistance (2021),The first input end of adaptive circuit (1105) is connected with one end of resistance (2021),Second input of adaptive circuit (1105) is connected with one end of resistance (2022),3rd input of adaptive circuit (1105) is connected with one end of resistance (2023),The four-input terminal of adaptive circuit (1105) is connected with one end of resistance (2024),5th input of adaptive circuit (1105) is connected with one end of resistance (2025),6th input of adaptive circuit (1105) is connected with one end of resistance (2026),7th input of adaptive circuit (1105) is connected with one end of resistance (2027);
And, the fixing end of analog switch (2001) is the first outfan of adaptive circuit (1105), the fixing end of analog switch (2002) is the 2nd 1 outfan of adaptive circuit (1105), the fixing end of analog switch (2003) is the 3rd outfan of adaptive circuit (1105), the fixing end of analog switch (2004) is the 4th outfan of adaptive circuit (1105), the fixing end of analog switch (2005) is the 5th outfan of adaptive circuit (1105), the fixing end of analog switch (2006) is the 6th outfan of adaptive circuit (1105), the fixing end of analog switch (2007) is the 7th outfan of adaptive circuit (1105);
Further, 0 selection end of analog switch (2001), 0 selection end of analog switch (2002), 0 selection end of analog switch (2003), 0 selection end of analog switch (2004), 0 selection end of analog switch (2005), 0 selection end of analog switch (2006), 0 selection end of analog switch (2001) be connected and connect the negative electrode of diode (2011), diode (2013) anode connected.
SPM the most according to claim 4, it is characterised in that the resistance that resistance (2016) and resistance (2012) select resistance to be 30k Ω.
SPM the most according to claim 4, it is characterized in that, resistance (2021), resistance (2022), resistance (2023), resistance (2024), resistance (2025), the resistance of resistance (2026) are 100 Ω, the 7th outfan making adaptive circuit (1105) is connected with the 7th input of adaptive circuit (1105) by resistance (2027), and the resistance of resistance (2027) is 50 Ω.
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