CN105895665A

CN105895665A - Structure of back doped regions of semiconductor power device

Info

Publication number: CN105895665A
Application number: CN201410571144.2A
Authority: CN
Inventors: 苏冠创
Original assignee: Nanjing Lisheng Semiconductor Technology Co Ltd
Current assignee: Nanjing Lisheng Semiconductor Technology Co Ltd
Priority date: 2014-10-21
Filing date: 2014-10-21
Publication date: 2016-08-24

Abstract

The invention discloses a structure of back doped regions of a semiconductor power device. The back of the semiconductor power device is characterized in that at least one independent P+ region 12 close to the back is contacted with back metal, two sides of the P+ region close to the back metal are provided with an N-type region 17, the thickness of the N-type region is less than 1um, the concentration ranges from 5*10<14>/cm3 to 5*10<17>/cm3, the N-type layer forms non-ohmic contact with the back metal, the N-type layer 17 is separated from an N-type buffer region 10 by a lightly-doped P-type layer 11, the N-type buffer region is deeper away from the back surface than the P-type layer 11 and the P+ region 12, junction depth of the lightly-doped P-type layer 11 away from the back surface is less than that of the P+ region, and a metal electrode is contacted with semiconductor back.

Description

A kind of structure of the back side doped region of semiconductor power device

Technical field:

The present invention relates to the structure of a kind of semiconductor power device, more particularly to the structure of back side doped region of the silicon chip of a kind of semiconductor power device.

Background technology:

1980, RCA Corp. of the U.S. applied for first IGBT patent, and within 1985, Toshiba Corp is made that first industrial IGBT.From device physically for, it is non-transparent collector punch IGBT, referred to as punch IGBT (Punchthrough IGBT-is abbreviated as PT-IGBT).PT-IGBT is to manufacture on epitaxial silicon chip.Want the extension of growth thickness thickness what 110um, technically have any problem, and cost can drastically increase, so, PT-IGBT be typically only applicable to pressure for 400V to 1200V in the range of.To manufacture pressure for 1700V or 2500V or 3300V or more than, all use non-punch through IGBT (Non-punchthrough IGBT in early days, it is abbreviated as NPT-IGBT), device is fabricated directly in thickness to be had in the FZ N-type silicon chip of hundreds of micron, and p type island region or the p-type/N-type region of device collector junction are formed by ion implanting.

In 1996, motorola inc delivered an article and has described the research about manufacturing non-break-through IGBT, stresses how to manufacture in thin silicon wafer the technique of colelctor electrode, and it is thick that the thinnest of FZ N-type silicon chip used there are about 170um.In next year, Infineon company has also delivered the NPT-IGBT making 600V by the FZ N-type silicon chip that 100um is thick.About 99 years, the IGBT of industrial a new generation starts to go into operation, the IGBT of this new generation is a kind of high-speed switching devices, its voltage reduces to positive temperature coefficient, it need not shorten minority carrier life time in device with heavy metal or irradiation, and main technology is that ultra thin silicon wafers technique is plus weak collector junction (or the most transparent collector junction).Infineon company is referred to as field cut-off IGBT, and the following years, the company of each main production IGBT all releases one after another similar product.From that time, IGBT has obtained qualitative leap on electric property, quickly grows and dominated the market of medium power range.

The structure of this kind of so-called field cut-off IGBT device mainly has a N-type cushion 10 and a collector junction P-type layer 11 as it is shown in figure 1, the thickness of P-type layer is generally no greater than 1 micron, doping content scope about 1 × 10¹⁷/cm³To 5 × 10¹⁸/cm³Between scope, this P-type layer forms weak colelctor electrode with back metal, when device turns off from opening state, N-type carrier (i.e. electronics) can easily pass through P-type layer and directly be collected by back of the body colelctor electrode, the time that these N-type carrier remain in N-type base and N-type buffering area is the shortest, so not as the Current Tail leaving a length of general PT type IGBT when turning off.

Along with the development of power device IGBT technology, the switching speed of IGBT is increasingly faster, and in application system, the IGBT with high-speed switch needs to ask the diode (FRD) using fast quick-recovery as fly-wheel diode.Switching device IGBT is each time from opening to turn off process, and fly-wheel diode can be become cut-off state from conducting state.And this is crossed range request diode and has the softest recovery characteristics.In application process, wish that the power consumption of system is little, the electromagnetic noise that reliability is high and less, IGBT and FRD is had high requirements by this, but, in a very long time, industry ignores the exploitation of fast recovery diode (FRD), because the performance of FRD does not catches up with, become the usefulness limiting whole system, so the performance of IGBT is fine, also cannot bring into play, and the effect of fast recovery diode receives the attention of height.

Since two thousand, the technological development making IGBT by thin silicon wafer technique is rapid, the maturation made along with thin silicon wafer IGBT, and naturally corresponding technology is also used to make FRD.In early days thin silicon wafer technique mainly write power in how wear down silicon chip, how to process the back of the body after grinding, how the back side of silicon chip after wear down doing ion implanting and how to do the technologic problem of annealing etc., the structure of the IGBT of field cut-off in early days is fairly simple as shown in Fig. 1.The FRD made by thin slice technique is then as in figure 2 it is shown, these structure are all only a kind of doped regions such as 11 or 14 and back metal contacts.

nullIn 2010，Ying Fei company proposes a structure-improved (US7884389B2)，This structure is to add multiple highly doped P+ type communities as shown in Figure 3 in territory, p type island region，These P+ type communities 12 can be good with back-metal formation Ohmic contact，When conducting，Hole can be effectively injected，Conduction voltage drop is made to be maintained at electronegative potential，During shutoff，Electronics effectively and rapidly can be collected not having at the weak colelctor electrode in P+ district，Device is made still to have turn-off speed quickly，The shortcoming of this structure is that the longitudinal edge of p type island region is deep，As shown in Figure 3，Breakdown voltage is affected in order to avoid there being break-through situation to occur at P district，N-type buffer layer thickness to compare thick or concentration is higher，Under using same implantation dosage and annealing conditions，Need to use the demand having the ion implantation apparatus of higher Implantation Energy could meet buffer layer thickness，The ion implantation apparatus causing some Implantation Energies relatively low should not use，Thus indirectly increase cost.

Summary of the invention:

IGBT or the FRD manufactured by thin FZ N-type silicon chip is ended in the field that the above is said, the structure of its back side part is the most crucial to the performance of device, it is an object of the invention to propose a kind of more optimize and the structure of a kind of semiconductor power device silicon chip of practical, implementing the present invention has following several different scheme:

nullScheme (1): the present invention is used to improve IGBT back structure，Its back structure is as shown in Figure 4，Near the back side at least independent P+ region and a back metal contacts，It it is N-type region territory outside P+ region，The n-type doping concentration original with FZ silicon chip and back metal contacts，Back metal is Ohmic contact with contacting of N+ district，It is non-ohmic contact with contacting of FZ N-type region，This structure is when forward conduction，Contact with the good ohmic of metal through P+ district，Hole injection efficiency is the highest，Conduction voltage drop can be lacked，When the IGBT being in conducting state is turned off，N-type carrier will not be trapped in N-type region，Electrons directly through N-type region to back metal，Turn-off speed will not be because injecting a large amount of hole-electron pair and by too much influence before，Turn-off speed is substantially fast as general field cut-off IGBT.

Scheme (2): the back metal of Fig. 4, wherein has part contact with P+, and having part is contact with N-type region, and contact with N-type region is non-ohmic contact, and this contacts will not be effectively short-circuit for P+ thus increase conduction voltage drop.If this part contact has an impact conduction voltage drop, this programme can solve this problem, the width being exactly a most at least P+ district 13 is more than 200um as shown in the structure of Fig. 5, N-type region is not had in this region, the central part in this P+ district can be easy to be biased and start to inject hole, thus reduces conduction voltage drop.

Scheme (3): scheme (1) and scheme (2) are if being used in field cut-off structure, when reverse bias, depletion layer may be made to contact with P+ district and cause punchthrough current, be directed at breakdown voltage and reduce, substandard, this programme can solve this problem.This programme and scheme before are a difference in that and add a N-type buffering area between P+ district and N-type base, as shown in the structure of Fig. 6, have one pair of N-type region added 15 to surround P+ district, and the concentration of the N-type region that this pair adds is 5 × 10¹⁴/cm³To 5 × 10¹⁷/cm³, this pair adds depletion layer when N-type region can be avoided inverting and extends to P+ district, and Fig. 7 and 8 is that another has pair structure adding N-type cushion, and this also can prevent punch-through generation.

Scheme (4): this programme places a P-type layer 11 overleaf at metal as it is shown in figure 9, concentration range is 5 × 10¹⁴/cm³To 5 × 10¹⁷/cm³Thickness is less than 1um, and junction depth is more shallow than P+ district, and this P-type layer is isolated metal with N-type base, P+ district is made not to be shorted, this can make P+ when plus turn-on bias, it is easier to injection hole, ground, makes conduction voltage drop lower, when device is turned off from conducting state, electronics can pass the p type island region that doping content is relatively low, and directly by behind metal collection, turn-off speed is quickly.

Scheme (5): this programme is the further improvement of scheme (4), its back structure is as shown in FIG. 10 and 11, advance about 0.2um to 1.5um deep toward surface direction P-type layer junction depth inner for scheme (4), then at back metal, a thin N-type layer 17 is being placed, thickness is less than 1um, and concentration range is 5 × 10¹⁴/cm³To 5 × 10¹⁷/cm³This N-type layer contacts with back metal, but will not be the short circuit of P+ district, because having a low-doped P-type layer that this N-type layer 17 is separated with N-type buffering area 10, when device is in forward direction turn-on bias, P+ can be effectively injected hole, making conduction voltage drop step-down, when being turned off from conducting state, electrons fits relatively easily through P-type layer to N-type layer, the most promptly being collected by back metal, turn-off speed can be quickly.Project plan comparison before is applicable to IGBT, only need to slightly adjust, and those structures just become being more suitable for FRD,

Scheme (6): the structure of this programme is that at least an independent N+ district contacts with back metal, is that a P-type layer contacts with back metal outside N+ district, and as shown in figure 12, P-type layer is honest and kind less than 1.0um, and concentration range is 5 × 10¹⁴/cm³To 5 × 10¹⁷/cm³, metal contacts with N+ as Ohmic contact, contact with P-type layer as non-ohmic contact, when FRD forward conduction, electronics can pass through the Ohmic contact of N+ and metal and is easily injected into the most again electronics, p type island region is non-ohmic contact with contacting of metal, it is not easy to receive from surface anode p type island region injected holes, so electronics and cavity energy are modulated effectively in N-type expansion area, make conduction voltage drop step-down, when conducting state is turned off, electrons flows through the N+ district at the back side to back metal, if the excess electron of expansion area is the most just pumped, the soft factor turned off can diminish, i.e. turning off can be hardening, this can cause circuit oscillation, even can make device failure.This programme is possible to prevent this situation to occur, main is exactly by those p-type thin layers near the back side, the concentration foot of this p-type thin layer is high so that electronics is invalid to be passed, furthermore, hole also can be injected during shutoff, through injected holes electronics in tow, the speed making electronics be pumped slows down, thus soft factor when increasing shutoff, this can be avoided causing circuit oscillation, reduces the radiation interference to periphery.Through width and the degree of depth of control N+, and the thickness of P-type layer, the region of the N+ being exposed in P-type layer can be indirectly controlled, this can efficiently control the region effectively launching and collecting electronics of N+, thus controls conducting and the characteristic turned off.

Scheme (7): this programme further increases soft factor during shutoff, it is exactly to pay at the top (i.e. N+ district is far from farthest, the back side) of N+ to add a p type island region 19 as shown in figure 13, this p type island region can pass through while injecting N+ district again with higher Implantation Energy implanting p-type foreign ion, the rate that flows away of electronics when the P-type layer at the top of this N+ can efficiently control shutoff altogether with the P-type layer near back metal, thus soft factor when efficiently controlling shutoff.

Scheme (8): scheme (6) and scheme (7) are if being used in field cut-off structure, i.e. with the FRD of thin FZ silicon wafer to manufacture, depletion layer may encounter the p type island region near back metal when reverse bias, so when reverse bias, there may be punch through and cause breakdown voltage to become the lowest.This programme can solve this problem, adds a N-type buffering area, structure as shown in figure 14 between method Shi P+ district and N-type base, and the concentration of the N-type region that this pair adds is 5 × 10¹⁴/cm³To 5 × 10¹⁷/cm³, this pair adds depletion layer when N-type region can be avoided inverting and extends to P+ district, contact therewith thus cause punchthrough current.

The above some scheme is more suitable for IGBT, and some is more suitable for FRD, the scheme of the most each structure to be used equally to semiconductor power device such as IGBT or RC-IGBT or FRD or MCT or GTO；Or power MOS pipe.

Accompanying drawing explanation

Accompanying drawing is used for providing a further understanding of the present invention, is used for together with embodiments of the present invention explaining the present invention, is not intended that limitation of the present invention, in the accompanying drawings:

Fig. 1 is the cross-sectional structure schematic diagram of general field cut-off IGBT device；

Fig. 2 is the cross-sectional structure schematic diagram of the FRD typically manufactured by thin silicon wafer technique；

Fig. 3 is the cross-sectional structure schematic diagram having two kinds of doped regions with the RC-IGBT of back metal contacts；

Fig. 4 is the cross-sectional structure schematic diagram of the device of the present invention program (1)；

Fig. 5 is the cross-sectional structure schematic diagram of the device of the present invention program (2)；

Fig. 6 is the cross-sectional structure schematic diagram of the device of the present invention program (3)；

Fig. 7 is the cross-sectional structure schematic diagram of the device of the present invention program (3)；

Fig. 8 is the cross-sectional structure schematic diagram of the device of the present invention program (3)；

Fig. 9 is the cross-sectional structure schematic diagram of the device of the present invention program (4)；

Figure 10 is the cross-sectional structure schematic diagram of the device of the present invention program (5)；

Figure 11 is the cross-sectional structure schematic diagram of the device of the present invention program (5)；

Figure 12 is the cross-sectional structure schematic diagram of the device of the present invention program (6)；

Figure 13 is the cross-sectional structure schematic diagram of the device of the present invention program (7)；

Figure 14 is the cross-sectional structure schematic diagram of the device of the present invention program (8)；

Figure 15 is the surface texture schematic diagram forming power device of the embodiment of the present invention 1；

Figure 16 be the embodiment of the present invention 1 complete schematic diagram after grinding step；

Figure 17 is that the back surface to silicon chip 200 of embodiment 1 injects hydrogen doping matter ion schematic diagram；

Figure 18 is that the back surface to silicon chip of embodiment 1 injects boron doping ion schematic diagram through mask plate；

Figure 19 is that the embodiment of the present invention 1 completes the cross-sectional structure schematic diagram of device after backplate 20；

Figure 20 is that the back surface to silicon chip of embodiment 2 injects boron doping ion schematic diagram；

Figure 21 is that the embodiment of the present invention 2 completes the cross-sectional structure schematic diagram of device after backplate 20；

Figure 22 is that the back surface to silicon chip of embodiment 3 injects As doping ion schematic diagram；

Figure 23 is that the embodiment of the present invention 3 completes the cross-sectional structure schematic diagram of device after backplate 20；

Figure 24 is the surface texture schematic diagram forming power device of the embodiment of the present invention 4；

Figure 25 be the embodiment of the present invention 4 complete schematic diagram after grinding step；

Figure 26 is that the back surface to silicon chip of embodiment 4 injects boron doping ion schematic diagram；

Figure 27 is that the back surface to silicon chip of embodiment 4 injects P31 doping ion schematic diagram through mask plate；

Figure 28 is that the embodiment of the present invention 4 completes the cross-sectional structure schematic diagram of device after backplate 20；

Figure 29 is that the embodiment of the present invention 5 completes the cross-sectional structure schematic diagram of device after backplate 20；

Figure 30 is that the back surface to silicon chip of embodiment 6 injects B11 doping ion schematic diagram through mask plate；

Figure 31 is that the embodiment of the present invention 6 completes the cross-sectional structure schematic diagram of device after backplate 20.

Reference symbol table:

1 passivation layer

2 aluminium alloy layers

3 inter-level dielectrics

4 highly doped polysilicons

5 N-type source regions

The p-type high-doped zone of 6 contact hole channel bottoms

7 p-type bases

The N-type region of 8 trench bottom

9 N-type bases

10 N-type cushions

11 near the p type island region of back metal

12 near the P+ type district of back metal

13 near the width of back metal more than the P+ type district of 200um

14 near the N+ type district of back metal

15 surround P+ district pays the N-type region added

16 surround top, P+ district pays the N-type region added

17 N-type layer contacted with each other with metal

18 N+ independent zones

The p type island region added is paid in 19 top, N+ independent zones

20 metal layer on back

100 originally thinning before substrate

200 complete the substrate after wear down operation

Detailed description of the invention

Embodiment 1:

As shown in figure 15, the manufacturing process of the chip of whole power device can be divided into preceding working procedure and later process, preceding working procedure is the surface cell of device, if the UMOS unit making on IGBT device surface is at the front surface of silicon chip 100, it it is the inter-level dielectric 3 of UMOS unit on the front surface of silicon chip, metal level 2 (titanium/titanium nitride layer, tungsten and aluminium alloy) and passivation layer 1.The device manufactured on silicon chip 100 surface can also be MCT or GTO, silicon chip described here is FZ N-type silicon chip, or CZ N-type silicon chip, resistance value regarding manufactured device pressure depending on, it is 1200V as pressure, resistance value scope is about 50 Ω .cm to 120 Ω .cm, and thickness is the most conventional the most thinning thickness used, and about 400um to 720um is thick.

As shown in figure 16, completing silicon chip 100 wear down of front road technique to desired thickness, voltage device as resistance in 1200V to be manufactured, then after wear down operation completes, thickness is about 110um, and silicon chip 100 becomes silicon chip 200.

As shown in figure 17, the back surface of silicon chip 200 being injected N type dopant such as hydrogen doping agent, implant angle is 0 degree, and dosage range is 1 × 10¹⁴/cm²To 1 × 10¹⁵/cm², Implantation Energy scope is 100KeV to 2MeV, and this step is used for being formed the N-type cushion 10 of structure.

As shown in figure 18, the back surface of silicon chip 200 being passed through mask plate implanting p-type adulterant such as boron dope agent, injector angle is 0 degree to 7 degree, and dosage range is 1 × 10¹⁵/cm²To 1 × 10¹⁶/cm², Implantation Energy scope is 20KeV to 200KeV, and this step is used for being formed the P+ type district 12 of Figure 19 structure.

As shown in figure 19, it is 300 DEG C to 450 DEG C that silicon chip 200 is placed in temperature range, annealing 30mins to 100mins, annealing steps activates the boron injected and hydrogen doping agent, form P+ type district 12 and N-type cushion 10, with sputtering or deposition process, silicon chip 200 back surface being metallized afterwards, as the backplate 20 of device, metal layer material can be Al/Ti/Ni/Ag or Ti/Ni/Ag or Al/Ti/Ni/Au etc..

In embodiment 1, annealing can also be carried out in the middle of electrode metallization step after completing backplate metallization or overleaf.

Embodiment 2:

The technical scheme of the present embodiment is roughly the same with embodiment 1, and it differs only in:

In above-described embodiment 1, after silicon chip 100 wear down to desired thickness；Before the back surface of silicon chip 200 is made any injection, or after completing described injection P+ district and N-type buffering area, pay and add following implantation step:

As shown in figure 20, the back surface implanting p-type adulterant such as boron dope agent to silicon chip 200, injector angle is 0 degree to 7 degree, and dosage range is 1 × 10¹⁴/cm²To 1 × 10¹⁵/cm², Implantation Energy scope is 20KeV to 200KeV, and this step is used for being formed the P-type layer 11 of structure.

Step such as embodiment 1 step after implantation is completed afterwards, the Structure of cross section of device is as shown in figure 21.

Embodiment 3:

The technical scheme of the present embodiment is roughly the same with embodiment 2, and it differs only in:

In above-described embodiment 2, before or after completing described injection P+ district 12, P-type layer 11 and N-type buffering area 10 or between, pay and add following implantation step:

As shown in figure 22, the back surface of silicon chip 200 being injected N type dopant such as arsenic (As) adulterant, injector angle is 0 degree to 7 degree, and dosage range is 1 × 10¹²/cm²To 5 × 10¹⁴/cm², Implantation Energy scope is 50KeV to 200KeV, and this step is used for forming the N-type layer 17 contacted with back metal.

Step such as embodiment 2 step after implantation is completed afterwards, the Structure of cross section of device is as shown in figure 23.

Embodiment 4:

As shown in figure 24, the manufacturing process of the chip of whole power device can be divided into preceding working procedure and later process, preceding working procedure is the surface cell of device, if the unit making of FRD device surface is at the front surface of silicon chip 100, it it is the inter-level dielectric 3 of UMOS unit on the front surface of silicon chip, metal level 2 (titanium/titanium nitride layer, tungsten and aluminium alloy) and passivation layer 1.The device manufactured on silicon chip 100 surface can also be MCT or GTO, silicon chip described here is FZ N-type silicon chip, or CZ N-type silicon chip, resistance value regarding manufactured device pressure depending on, it is 1200V as pressure, resistance value scope is about 50 Ω .cm to 120 Ω .cm, and thickness is the most conventional the most thinning thickness used, and about 400um to 720um is thick.

As shown in figure 25, completing silicon chip 100 wear down of front road technique to desired thickness, voltage device as resistance in 1200V to be manufactured, then after wear down operation completes, thickness is about 110um, and silicon chip 100 becomes silicon chip 200.

As shown in figure 26, the back surface implanting p-type adulterant such as boron dope agent to silicon chip 200, injector angle is 0 degree to 7 degree, and dosage range is 1 × 10¹⁴/cm²To 1 × 10¹⁵/cm², Implantation Energy scope is 20KeV to 200KeV, and this step is used for being formed the P-type layer 11 of structure.

As shown in figure 27, through mask plate, the back surface of silicon chip 200 being injected N type dopant such as P31, implant angle is 0 degree to 7 degree, and dosage range is 1 × 10¹⁵/cm²To 1 × 10¹⁶/cm², Implantation Energy scope is 100KeV to 2MeV, and this step is used for being formed the N+ type district 18 of Figure 28 structure.

As shown in figure 28, it is 300 DEG C to 450 DEG C that silicon chip 200 is placed in temperature range, annealing 30mins to 100mins, annealing steps activates the boron injected and P31 adulterant, form type district 18, p type island region 11 and N+, with sputtering or deposition process, silicon chip 200 back surface being metallized afterwards, as the backplate 20 of device, metal layer material can be Al/Ti/Ni/Ag or Ti/Ni/Ag or Al/Ti/Ni/Au etc..

In example 4, annealing can also be carried out in the middle of electrode metallization step after completing backplate metallization or overleaf.

Embodiment 5:

In above-described embodiment 1, after silicon chip 100 wear down to desired thickness；Before the back surface of silicon chip 200 is made any injection, or after completing described injection P+ district and N-type buffering area, pay and add following implantation step: the back surface of silicon chip 200 is injected N type dopant such as hydrogen doping agent, and implant angle is 0 degree, and dosage range is 1 × 10¹⁴/cm²To 1 × 10¹⁵/cm², Implantation Energy scope is 100KeV to 2MeV, and this step is used for being formed the N-type cushion 10 of structure.

As shown in figure 29, it is 300 DEG C to 450 DEG C that silicon chip 200 is placed in temperature range, annealing 30mins to 100mins, annealing steps activates the boron injected and hydrogen and P31 adulterant, form p type island region 11 and N-type cushion 10 and N+ type district 18, with sputtering or deposition process, silicon chip 200 back surface being metallized afterwards, as the backplate 20 of device, metal layer material can be Al/Ti/Ni/Ag or Ti/Ni/Ag or Al/Ti/Ni/Au etc..

In embodiment 5, annealing can also be carried out in the middle of electrode metallization step after completing backplate metallization or overleaf.

Embodiment 6:

The technical scheme of the present embodiment is roughly the same with embodiment 5, and it differs only in:

In above-described embodiment 5, before or after completing described injection N+ district 18, P-type layer 11 and N-type buffering area 10 or between, pay and add following implantation step:

As shown in figure 30, after completing described injection N+ district 18 or, keep mask plate and the relative position before silicon chip, then the back surface to silicon chip 200 passes through the mask plate implanting p-type adulterant such as boron of previous step, and implant angle is 0 degree, and dosage range is 1 × 10¹³/cm²To 1 × 10¹⁵/cm², Implantation Energy scope is 200KeV to 2MeV, and this step is used for being formed the p type island region 19 of Figure 31 structure.

Step such as embodiment 5 step after implantation is completed afterwards, the Structure of cross section of device is as shown in figure 31.

Last it is noted that these are only the preferred embodiments of the present invention, it is not limited to the present invention, the present invention can be used for relating to manufacturing semiconductor power device (such as, insulated trench gate bipolar transistor Trench IGBT or MCT or GTO), the summary of the invention of presents and embodiment are to make an explanation with N-type passage device, the present invention also can be used for p-type passage device, although the present invention being described in detail with reference to embodiment, for a person skilled in the art, technical scheme described in foregoing embodiments still can be modified by it, or wherein portion of techniques feature is carried out equivalent, but all within the spirit and principles in the present invention, the any amendment made, equivalent, improve, should be included within the scope of the present invention.

Claims

1. the structure of the back side doped region of a semiconductor power device at least includes with lower part:

(1) near a semiconductor back surface at least independent P+ district, width is more than 20um, this P+ district The formation Ohmic contact while being connected with back metal, another side is surrounded by N-type base, the doping in this P+ district Concentration range is 1 × 10¹⁹/cm³To 1 × 10²⁰/cm³；

(2) semiconductor back surface has two different doped regions and back metal contacts, and the two is different Doped region is P+ district 12 and N-type base 9；

(3) metal layer on back is connected with semiconductor back surface formation backplate, wherein metal level and P+ District 12 forms Ohmic contact, forms non-ohmic contact with N-type base 9.

The most according to claim 1 in the P+ district of part (1), it is characterised in that have more than one P+ district, wherein At least the width in a P+ district is more than 200um.

The most according to claim 1 in the P+ district of part (1), it is characterised in that in addition to N-type base 9, have The N-type region that one pair adds is surrounded and is write P+ district, and the N-type region that this pair adds thickness outside P+ district is more than 0.5um, this The doping content scope paying the N-type added is 5 × 10¹⁴/cm³To 5 × 10¹⁷/cm³。

4. the structure of the back side doped region of a semiconductor power device at least includes with lower part:

(1) semiconductor back surface has a N-type cushion 10, and this N-type cushion is in N-type base 9 The degree of depth from semiconductor back surface is more than 1um, and doping content scope is 1 × 10¹⁵/cm³To 5 × 10¹⁷/cm³；

(2) having a P-type layer 11 near semiconductor back surface, this P-type layer with back metal shape Becoming non-ohmic contact, another side is connected with N-type cushion 10, and this P-type layer 11 is at N-type cushion 10 While the degree of depth from the back side is less than 1um, doping content scope is 1 × 10¹⁵/cm³To 5 × 10¹⁷/cm³；

(3) near a semiconductor back surface at least independent P+ district, width range is more than 20um, this P+ District while forming Ohmic contact with back metal, has part overlapping with P-type layer 11 in the P+ district near the back side, Beyond overlap, part is surrounded by N-type buffering area 10, and the knot that this P+ district is formed with N-type cushion compares p type island region 11 is more deep with the knot that N-type cushion is formed, i.e. further from back surface, and the doping content scope in this P+ district It is 1 × 10¹⁹/cm³To 1 × 10²⁰/cm³。

5. the structure of the back side doped region of a semiconductor power device at least includes with lower part:

(1) semiconductor back surface has a N-type cushion 10, and this N-type cushion is in the one of N-type base 9 While the degree of depth from semiconductor back surface is more than 1um, doping content scope is 1 × 10¹⁵/cm³To 5 × 10¹⁷/cm³；

(2) having a N-type layer 17 near semiconductor back surface, this N-type layer with back metal shape Become non-ohmic contact, another side is connected with P-type layer 11, this N-type layer 17 P-type layer 11 from The degree of depth at the back side is less than 1um, and doping content scope is 5 × 10¹⁴/cm³To 5 × 10¹⁷/cm³；

(3) near a semiconductor back surface at least independent P+ district, width range is more than 20um, this P+ District while forming Ohmic contact with back metal, and another side is connected or mutually close with N-type cushion 10, The doping content scope in this P+ district is 1 × 10¹⁹/cm³To 1 × 10²⁰/cm³；

(4) having a P-type layer 11 between N-type layer 17 and N-type cushion 10, this P-type layer is N Type layer 17 separates with N-type cushion 10, P-type layer thickness between 0.5um to 1.5um, doping content Scope is 5 × 10¹⁴/cm³To 5 × 10¹⁷/cm³；

(5) be connected with semiconductor back surface forms Ohmic contact for metal, this metal level and P+ district 12, Forming non-ohmic contact with N-type layer 17, this metal level forms backside collector with semiconductor back surface.

The most according to claim 5, in the P-type layer 11 of part (4), its feature is delayed in N-type in this p type island region 11 Rush floor while more deeper from back surface than P+ district.

7. the structure of the back side doped region of a semiconductor power device at least includes with lower part:

(1) having a P-type layer 11 near semiconductor back surface, this P-type layer with back metal shape Becoming non-ohmic contact, another side is connected with N-type base 9, and this P-type layer 11 is in N-type base 9 The little 1um of the degree of depth from the back side in, doping content scope is 1 × 10¹⁵/cm³To 5 × 10¹⁷/cm³；

(2) near a semiconductor back surface at least independent N+ district 18, width range is more than 20um, , there are part and P-type layer 11 in this N+ district while forming Ohmic contact with back metal in the N+ district near the back side Overlap, beyond overlap, part is surrounded by N-type base 9, and p type island region is compared on the limit away from back surface in this N+ district 11 is more deep with the knot that N-type base 9 is formed, and the doping content scope in this N+ district is 1 × 10¹⁹/cm³Extremely 1×10²⁰/cm³。

The most according to claim 7 part (2) N+ district 18, it is characterized in that N+ district 18 top (i.e. N+ district is far from farthest, the back side) to pay added with a p type island region 19, the p type island region that this pair adds thickness outside N+ district is more than 0.5um, width such as N+ district, the doping content scope in the P district that this pair adds is 5 × 10¹⁴/cm³To 5 × 10¹⁷/cm³。

9. the structure of the back side doped region of a semiconductor power device at least includes with lower part:

(3) near a semiconductor back surface at least independent N+ district, width range is more than 20um, this N+ District while forming Ohmic contact with back metal, has part overlapping with P-type layer 11 in the N+ district near the back side, Beyond overlap, part is surrounded by N-type buffering area 10, and the limit away from back surface in this N+ district is than p type island region 11 More deep with the knot that N-type cushion is formed, the doping content scope in this N+ district is 1 × 10¹⁹/cm³Extremely 1×10²⁰/cm³。

The most according to claim 9 part (3) N+ district 18, it is characterized in that N+ district 18 top (i.e. N+ district is far from farthest, the back side) to pay added with a p type island region 19, the p type island region that this pair adds thickness outside N+ district is more than 0.5um, width such as N+ district, the doping content scope in the P district that this pair adds is 5 × 10¹⁴/cm³To 5 × 10¹⁷/cm³。