CN105891695B - A kind of IC card parallel test method based on single IO - Google Patents
A kind of IC card parallel test method based on single IO Download PDFInfo
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- CN105891695B CN105891695B CN201410189178.5A CN201410189178A CN105891695B CN 105891695 B CN105891695 B CN 105891695B CN 201410189178 A CN201410189178 A CN 201410189178A CN 105891695 B CN105891695 B CN 105891695B
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Abstract
A kind of IC card parallel test method based on single IO, is related to IC card technical field.The present invention carries out concurrent testing to the chip in IC card to be measured using test machine.The parallel test method includes that card receives command method and card transmission data method, using internal clocking sample command IO, every bit alignment transmitting-receiving order.Wherein card receives the method and step of order are as follows: 1) uses the low level of an external clock cycle as beginning flag；2) IC card to be measured carries out sample count using length of the internal clocking sample command IO to low and high level；3) IC card to be measured judges the counting of each group of low and high level；4) order bit0 ~ bit2 transmits command type, that is, the length of the order has been determined, IC card sequential sampling to be measured jumps out the circulation for receiving order after receiving enough data of designated length.The present invention uses internal clocking sample command IO, and every bit alignment carries out order transmitting-receiving, reduces clock IO, increases with number of cards is surveyed, effectively reduce testing cost.
Description
Technical field
The present invention relates to IC card technical fields, can especially carry out simultaneously in the case where no external clock to multiple IC card
Row test.
Background technique
IC card is widely used in the application such as mobile communication, Credit Card Payments.With being constantly progressive for IC card technology, IC card
Unit area increasingly reduce, the output value on individual wafer continues to increase.Incident is the ratio that testing cost accounts for totle drilling cost
Weight is significant to be increased, and this contradiction is more obvious with becoming larger for IC card memory capacity.
In the prior art, due to the internal clocking of chip in IC card, both there are certain models for clock caused by internal crystal oscillator
The deviation enclosed, so traditional mode of production test is all made of external clock, i.e. the issued clock of test machine carries out concurrent testing.The method
Benefit be IC card system with the order received be same clock source, the available effective control of order length, concurrent testing
IC card act in agreement, it is easy to operate.And cost be then every chips need test machine provide two IO, that is, order IO and
Clock IO can not accomplish with the maximization for surveying number of cards.
Summary of the invention
In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a kind of IC card based on single IO is parallel
Test method.It uses internal clocking sample command IO, and every bit alignment carries out order transmitting-receiving, reduces clock IO, increase with survey
Number of cards effectively reduces testing cost.
In order to achieve the above object of the invention, technical solution of the present invention is realized as follows:
A kind of IC card parallel test method based on single IO, it carries out the chip in IC card to be measured using test machine parallel
Test.The parallel test method includes that card receives command method and card transmission data method, is sampled using internal clocking
Order IO, every bit alignment transmitting-receiving order.Wherein card receives the method and step of order are as follows:
1) use the low level of an external clock cycle as beginning flag, a high level and a low level are one
Group indicates 1bit data；
2) IC card to be measured carries out sample count using length of the internal clocking sample command IO to low and high level；
3) IC card to be measured judges the counting of each group of low and high level, adopts if the number for adopting high level is greater than
Low level number, that is, judge the bit for 1, it is on the contrary then be 0；
4) order bit0 ~ bit2 transmits command type, that is, the length of the order has been determined, IC card sequential sampling to be measured is received
After the data of enough designated lengths, that is, jump out the circulation for receiving order.
Wherein card sends the method and step of data are as follows:
1) it after IC card to be measured receives reading instruction, into data flow is sent, waits on internal clocking sample command IO
Low level pulse indication signal；
2) it often detects a low level pulse, sends a bit data, i.e., in internal clock sampling order IO low level arteries and veins
After rushing rising edge, output 0 or 1 is simultaneously kept for a period of time, and test machine takes data away in this period；
3) after sending end of data, internal clocking sample command IO returns input pattern, waits low level pulse next time
Until total data is sent.
The present invention compared with the existing technology has a characteristic that due to using the above method
When card is received and is ordered:
1) card only judges the low and high level counting in a bit, does not judge the absolute quantity of counting, institute
The parsing of order will not be impacted with deviation existing for different card internal clockings.
2) length ordered can be adjusted, it is only necessary to which order width and internal clocking meet certain proportionate relationship i.e.
It can.
When card sends data:
1) send data process be aligned by bit with external clock, avoid as internal clocking it is asynchronous caused by reception
Error in data.
Present invention will be further explained below with reference to the attached drawings and specific embodiments.
Detailed description of the invention
Fig. 1 is the timing diagram that card receives order in the embodiment of the present invention；
Fig. 2 is the timing diagram that card sends data in the embodiment of the present invention.
Specific embodiment
The method of the present invention carries out concurrent testing to the chip in IC card to be measured using test machine, and parallel test method includes card
Piece receives command method and card sends data method, using internal clocking sample command IO, every bit alignment transmitting-receiving order.This
Card in invention receives the method and step of order are as follows:
1) use the low level of an external clock cycle as beginning flag, a high level and a low level are one
Group indicates 1bit data.
2) IC card to be measured carries out sample count using length of the internal clocking sample command IO to low and high level.
3) IC card to be measured judges the counting of each group of low and high level, adopts if the number for adopting high level is greater than
Low level number, that is, judge the bit for 1, it is on the contrary then be 0.
4) order bit0 ~ bit2 transmits command type, that is, the length of the order has been determined.IC card sequential sampling to be measured is received
After the data of enough designated lengths, that is, jump out the circulation for receiving order.
Card in the present invention sends the method and step of data are as follows:
1) it after IC card to be measured receives reading instruction, into data flow is sent, waits on internal clocking sample command IO
Low level pulse indication signal.
2) it often detects a low level pulse, sends a bit data, i.e., in internal clock sampling order IO low level arteries and veins
After rushing rising edge, output 0 or 1 is simultaneously kept for a period of time, and test machine takes data away in this period.
3) after sending end of data, internal clocking sample command IO returns input pattern, waits low level pulse next time
Until total data is sent.
Referring to Fig. 1, rising edge of the card after adopting start bit is started counting in the embodiment of the present invention, in the case where adopting
Drop record before is high level number, is low level number before from failing edge to rising edge next time.It is high in bit0
The significant lower level of level wants short, and bit0 data are 0, and similarly, bit2 kind high level will be longer than low level, and bit2 data are 1.
Referring to Fig. 2, in the embodiment of the present invention after card receives reading instruction, into data flow is sent, adopt for the first time
After low level on internal clocking sample command IO, bit0 data are sent, i.e., export 0 on internal clock sampling order IO.Card 1
Internal clock frequencies be higher than card 2, so the low level on its internal clocking sample command IO can be adopted first, be introduced into afterwards
Send the state of bit0 data.And the time of test machine sampled point 1 is most slow effective internal clocking and most fast effective inside
Clock COMPREHENSIVE CALCULATING obtains, therefore ensure that two cards non-data in sampled point 1 send state, internal after transmission
Clock sampling order IO returns input pattern, and the low level on second of internal clocking sample command IO is waited to send bit1 number
According to.
Claims (1)
1. a kind of IC card parallel test method based on single IO, it surveys the chip in IC card to be measured using test machine parallel
Examination, the parallel test method include that card receives command method and card transmission data method, are sampled and are ordered using internal clocking
IO is enabled, every bit alignment receives order, and every bit alignment sends data；Wherein card receives the method and step of order are as follows:
1) use the low level of an external clock cycle as beginning flag, a high level and a low level are one group,
Indicate 1bit data；
2) IC card to be measured carries out sample count using length of the internal clocking sample command IO to low and high level；
3) IC card to be measured judges the counting of each group of low and high level, if the number for adopting high level, which is greater than, is adopted low electricity
Flat number, that is, judge the bit for 1, it is on the contrary then be 0；
4) order bit0 ~ bit2 transmits command type, that is, the length of the order has been determined, IC card sequential sampling to be measured is received and enough referred to
After the data of measured length, that is, jump out the circulation for receiving order；
Wherein card sends the method and step of data are as follows:
1) after IC card to be measured receives reading instruction, into data flow is sent, the low electricity on internal clocking sample command IO is waited
Flat pulse indication signal；
2) it often detects a low level pulse, sends a bit data, i.e., on internal clock sampling order IO low level pulse
It rises along rear, output 0 or 1 simultaneously keeps a period of time, and test machine takes data away in this period；
3) send end of data after, internal clocking sample command IO return input pattern, wait next time low level pulse until
Total data is sent.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410189178.5A CN105891695B (en) | 2014-05-07 | 2014-05-07 | A kind of IC card parallel test method based on single IO |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410189178.5A CN105891695B (en) | 2014-05-07 | 2014-05-07 | A kind of IC card parallel test method based on single IO |
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| CN105891695A CN105891695A (en) | 2016-08-24 |
| CN105891695B true CN105891695B (en) | 2019-01-11 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1211323A (en) * | 1996-02-06 | 1999-03-17 | 三星电子株式会社 | Utilizes the Joint Test Action Organization standard I/O state flip test method |
| CN1499599A (en) * | 2002-10-25 | 2004-05-26 | �Ҵ���˾ | Device and method for parallel testing semiconductor device |
| CN1979200A (en) * | 2005-12-08 | 2007-06-13 | 上海华虹Nec电子有限公司 | Method for parallelly detecting multiple chips of synchronous communication |
| CN1979201A (en) * | 2005-12-08 | 2007-06-13 | 上海华虹Nec电子有限公司 | Method for parallelly detecting synchronous communication chips |
| CN101324654A (en) * | 2007-06-15 | 2008-12-17 | 冲电气工业株式会社 | Semiconductor integrated device |
| CN102081139A (en) * | 2009-11-30 | 2011-06-01 | 上海华虹Nec电子有限公司 | Method for accurately calculating waiting time in semiconductor test |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2674338B2 (en) * | 1991-02-27 | 1997-11-12 | 日本電気株式会社 | Semiconductor integrated circuit test circuit |
-
2014
- 2014-05-07 CN CN201410189178.5A patent/CN105891695B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1211323A (en) * | 1996-02-06 | 1999-03-17 | 三星电子株式会社 | Utilizes the Joint Test Action Organization standard I/O state flip test method |
| CN1499599A (en) * | 2002-10-25 | 2004-05-26 | �Ҵ���˾ | Device and method for parallel testing semiconductor device |
| CN1979200A (en) * | 2005-12-08 | 2007-06-13 | 上海华虹Nec电子有限公司 | Method for parallelly detecting multiple chips of synchronous communication |
| CN1979201A (en) * | 2005-12-08 | 2007-06-13 | 上海华虹Nec电子有限公司 | Method for parallelly detecting synchronous communication chips |
| CN101324654A (en) * | 2007-06-15 | 2008-12-17 | 冲电气工业株式会社 | Semiconductor integrated device |
| CN102081139A (en) * | 2009-11-30 | 2011-06-01 | 上海华虹Nec电子有限公司 | Method for accurately calculating waiting time in semiconductor test |
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Address after: 100083 18 floor, West Tower, block D, Tongfang science and Technology Plaza, 1 Wang Zhuang Road, Wudaokou, Haidian District, Beijing. Applicant after: ZIGUANG TONGXIN MICROELECTRONICS CO.,LTD. Address before: 100083 18 floor, West Tower, block D, Tongfang science and Technology Plaza, 1 Wang Zhuang Road, Wudaokou, Haidian District, Beijing. Applicant before: BEIJING TONGFANG MICROELECTRONICS Co.,Ltd. |
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Effective date of registration: 20220928 Address after: In Xinxing Electronic Industrial Park, Yutian County, Tangshan City, Hebei Province, 063000 (west of Yuzun West Road) Patentee after: Tangshan jiezhun core measurement information technology Co.,Ltd. Address before: 100083 18 floor, West Tower, block D, Tongfang science and Technology Plaza, 1 Wang Zhuang Road, Wudaokou, Haidian District, Beijing. Patentee before: ZIGUANG TONGXIN MICROELECTRONICS CO.,LTD. |