CN105871893A - Electric system measurement and communication integrated chip supporting IEC61850 - Google Patents

Abstract

The invention discloses an integrated power system measurement and communication chip supporting IEC61850, which includes an acquisition module, a storage module, a processing module, an encryption and decryption module, a communication module, an Ethernet module, a transmission module and an on-chip bus. The acquisition module includes an analog-to-digital converter ADC for measuring analog signals, and a general-purpose digital input and output port GPIO for acquiring digital signals; the on-chip bus includes AHB high-speed system bus and APB low-speed peripheral bus, connected through two AHB2APB bridges. The chip realizes the functions of analog signal measurement, digital signal measurement, IEC103 data packet conversion, IEC61850 data packet conversion, etc. It has the characteristics of small size, low cost, low power consumption, convenient use, flexible communication, strong reliability and high security.

Description

An integrated chip for power system measurement and communication supporting IEC61850

technical field

The invention relates to the technical field of power communication, in particular to an integrated chip for power system measurement and communication supporting IEC61850.

Background technique

IEC103 communication protocol and IEC61850 communication protocol are two important communication standards in power system communication network. At present, many measurement and protection equipment in the power system adopt the IEC103 communication standard, and gradually convert to the IEC61850 communication standard. Taking the digital substation as an example, the system's operating data (three-phase voltage, current, switch status, etc.) needs to be collected from the electronic transformer, transmitted through the network in the station, received by the receiving device or processed by the application device to realize monitoring Or issue an action command, the entire communication process is based on the IEC61850 communication specification. The current equipment collects data from sensors, but does not support IEC103 and IEC61850 standard conversion of data, and requires an external protocol converter. There are problems such as complex hardware circuit connections, complex structures, large volumes, and high investment costs.

With the rapid development of the system-on-chip of power automation equipment, the measurement and communication functions of the power system are chip-based, and a chip that can collect analog signals and digital signals and convert the collected data into data packets conforming to the IEC103 protocol and the IEC61850 protocol is designed. It helps to reduce the development cost and difficulty of substation intelligent equipment, shorten the development cycle, and simplify the hardware circuit. In addition, integrating a security module into the chip helps to improve the security and reliability of power system communication data.

Contents of the invention

The purpose of the present invention is to overcome the shortcomings and deficiencies of the prior art, and provide an integrated chip for power system measurement and communication supporting IEC61850.

The object of the present invention is achieved through the following technical solutions:

An integrated chip for power system measurement and communication supporting IEC61850, the integrated chip includes an acquisition module, a storage module, a processing module, an encryption and decryption module, a communication module, an Ethernet module, a transmission module and an on-chip bus;

The on-chip bus includes an AHB high-speed system bus and an APB low-speed peripheral bus, connected through two AHB2APB bridges AHB2APB Bridege 0 and AHB2APB Bridege 1;

The acquisition module includes an analog-to-digital converter ADC and a general-purpose digital input and output port GPIO, which are respectively used for measuring analog signals and collecting digital signals;

The storage module includes an embedded fast memory EFLASH, a read-only memory ROM, and a static random access memory SRAM for storing data and programs;

The processing module is a high-performance ARM926EJS microprocessor, which converts the collected data into data packets conforming to the IEC103 communication protocol and the IEC61850 communication protocol;

The encryption and decryption module is an advanced encryption and decryption AES unit, which is used to realize the encryption and decryption functions of communication data;

Described communication module comprises universal asynchronous transceiver transmitter UART 0 and UART 1, serial peripheral interface SPI, two-way serial interface I2C;

The Ethernet module includes a physical address access controller MAC and a physical layer transceiver controller PHY;

The transmission module is a direct memory access controller DMA;

The high-performance ARM926EJS microprocessor, embedded fast memory EFLASH, read-only memory ROM, static random access memory SRAM, advanced encryption and decryption AES unit, physical address access controller MAC, direct memory access controller DMA and the AHB high-speed system Bus connection, the universal asynchronous transceiver transmitter UART 0, serial peripheral interface SPI, bidirectional serial interface I2C, general purpose digital input and output port GPIO and the APB low-speed system bus are connected and passed through AHB2APBBridege 0 and the AHB high-speed system Bus connection, the UART 1, the analog-to-digital converter ADC, the physical layer transceiver controller PHY are connected to the APB low-speed system bus and connected to the AHB high-speed system bus through AHB2APB Bridege 1.

Further, the analog-to-digital converter ADC is used to measure analog signals, and is a 16-bit analog-to-digital converter with 6 channels, and the sampling rate of each channel is as high as 16K, and the input voltage range is set to +/-10V or +/-5V;

The general-purpose digital input and output ports GPIO are used for collecting digital signals, and are 32 32-bit digital input and output ports, and the input voltage range is 0-3.3V.

Further, the embedded fast memory EFLASH is an on-chip integrated 2M EFLASH for storing boot loader programs and protocol conversion configuration files;

The read-only memory ROM is an integrated 16KB ROM in the chip, which is used to store the control program of the integrated chip;

The static random access memory (SRAM) is an on-chip integrated 16KB SRAM, which is used for data storage during protocol conversion.

Further, the control program of the high-performance ARM926EJS microprocessor is written under the Keil4 development environment, the chip is embedded in the UCOS-II real-time operating program, and the ARM processor controls the acquisition module to collect data and store it in the on-chip memory, and then the collected The data is converted into a data packet conforming to the IEC103 communication protocol and the IEC61850 communication protocol, and finally the Ethernet module and the communication interface are controlled to send the data packet.

Further, the advanced encryption and decryption AES unit adopts the AES algorithm with a packet length of 128bits and a key length of 128bits, and the encryption mode adopts the CBC grouping mode, which is used to realize the encryption and decryption functions of communication data. Data packets are encrypted individually.

Further, the UART 0 of the communication module is used to send the data packet obtained after the advanced encryption and decryption AES unit encrypts the IEC103 data packet, and the UART 1, SPI, and I2C of the communication module are expansion interfaces for communicating with peripherals Connect communication.

Further, the Ethernet module includes two 10/100M physical address access controllers MAC and two physical layer transceiver controllers PHY, which respectively support Ethernet port and optical fiber port connection, and are used to send advanced encryption and decryption AES units to IEC61850 The data packet obtained after the data packet is encrypted.

Further, the direct memory access controller DMA includes 4 channels DMA, wherein, channel 0 transmits the measurement data of the analog-to-digital converter ADC to the static random access memory SRAM, and channel 1 transmits the general digital input and output ports GPIO, UART 0 , SPI, and I2C measurement data are transmitted to SRAM, and channel 3 transmits the IEC103 data packets and IEC61850 data packets converted by the high-performance ARM926EJS microprocessor to the advanced encryption and decryption AES unit.

Compared with the prior art, the present invention has the following advantages and effects:

(1) The present invention directly converts the collected analog and digital data into data packets conforming to the IEC103 protocol and the IEC61850 protocol, without the need for an external protocol converter, which reduces the development difficulty and shortens the development cycle.

(2) The present invention integrates a PHY chip, supports Ethernet port and optical fiber communication, simplifies hardware circuits, and reduces development costs.

(3) The present invention integrates an advanced encryption and decryption AES unit, which can encrypt data and improve the reliability and security of communication.

Description of drawings

Fig. 1 is a structural block diagram of a power system measurement and communication integrated chip supporting IEC61850 disclosed by the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention more clear and definite, the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

Example

The structural diagram of a power system measurement and communication integrated chip supporting IEC61850 disclosed by the present invention is shown in Figure 1. The chip includes an acquisition module, a storage module, a processing module, an encryption and decryption module, a communication module, an Ethernet module, Transport modules and on-chip bus.

The on-chip bus includes an AHB high-speed system bus and an APB low-speed peripheral bus, which are connected through two AHB2APB bridges, AHB2APB Bridege 0 and AHB2APB Bridege 1.

The acquisition module includes an analog-to-digital converter ADC and a general-purpose digital input and output port GPIO.

The storage module includes an embedded fast memory EFLASH, a read-only memory ROM, and a static random access memory SRAM for storing data and programs.

The processing module is a high-performance ARM926EJS microprocessor, which converts the collected data into data packets conforming to the IEC103 communication protocol and the IEC61850 communication protocol.

The encryption and decryption module is an advanced encryption and decryption AES unit.

The communication module includes UART 0 and UART 1, a serial peripheral interface SPI, and a bidirectional serial interface I2C.

The Ethernet module includes a physical address access controller MAC and a physical layer transceiver controller PHY.

The transmission module is a direct memory access controller DMA.

The high-performance ARM926EJS microprocessor, embedded fast memory EFLASH, read-only memory ROM, static random access memory SRAM, advanced encryption and decryption AES unit, physical address access controller MAC, direct memory access controller DMA and the AHB high-speed system Bus connection, the universal asynchronous transceiver transmitter UART 0, serial peripheral interface SPI, bidirectional serial interface I2C, general purpose digital input and output port GPIO and the APB low-speed system bus are connected and passed through AHB2APBBridege 0 and the AHB high-speed system Bus connection, the UART 1, the analog-to-digital converter ADC, the physical layer transceiver controller PHY are connected to the APB low-speed system bus and connected to the AHB high-speed system bus through AHB2APB Bridege 1.

The above acquisition module includes an analog-to-digital converter ADC and a general-purpose digital input and output port GPIO, wherein the analog-to-digital converter ADC is used to measure analog signals, and is a 16-bit analog-to-digital converter with 6 channels, and the sampling rate of each channel is up to 16K , the input voltage range can be set to +/-10V or +/-5V;

The general-purpose digital input and output ports GPIO are used for collecting digital signals, and are 32 32-bit digital input and output ports, and the input voltage range is 0-3.3V.

The embedded fast memory EFLASH is an on-chip integrated 2M EFLASH for storing bootloader programs and protocol conversion configuration files;

The read-only memory ROM is a 16KB ROM integrated in the chip, which is used to store the control program of the integrated chip;

The static random access memory (SRAM) is an on-chip integrated 16KB SRAM, which is used for data storage during protocol conversion.

The control program of the high-performance ARM926EJS microprocessor is written under the Keil4 development environment, the chip is embedded in the UCOS-II real-time operating program, and the ARM processor controls the acquisition module to collect data and store it in the on-chip memory, and then convert the collected data In order to comply with the data packets of the IEC103 communication protocol and the IEC61850 communication protocol, finally control the Ethernet module and the communication interface to send the data packets.

The advanced encryption and decryption AES unit adopts the AES algorithm with a packet length of 128bits and a key length of 128bits, and the encryption mode adopts the CBC packet mode, which is used to realize the encryption and decryption functions of communication data. encryption.

The UART 0 of the communication module is used to send the data packet obtained after the AES unit encrypts the IEC103 data packet, and the UART 1, SPI, and I2C of the communication module are expansion interfaces for connecting and communicating with peripherals.

The Ethernet module includes two 10/100M physical address access controllers MAC and two physical layer transceiver controllers PHY, which respectively support Ethernet port and optical fiber port connections, and are used to send advanced encryption and decryption AES units to perform IEC61850 data packets Encrypted data packets.

The direct memory access controller DMA includes 4 channels DMA, wherein, the channel 0 transmits the measurement data of the analog-to-digital converter ADC to the static random access memory SRAM, and the channel 1 transmits the general digital input and output ports GPIO, UART 0, SPI, The measured data of I2C is transmitted to SRAM, and the channel 3 transmits the IEC103 data packet and IEC61850 data packet converted by the high-performance ARM926EJS microprocessor to the advanced encryption and decryption AES unit.

The normal working process of the above-mentioned integrated chip is as follows:

(1) ARM controls the ADC to collect the analog signal of each channel and transmits it to SRAM storage through DMA channel 0, and ARM controls GPIO, UART 0, SPI, I2C and other interfaces to collect digital signals and transmits it to SRAM storage through DMA channel 1.

(2) ARM reads the data stored in SRAM, converts the collected data into data packets conforming to IEC103 communication protocol and IEC61850 communication protocol, and stores the data in SRAM.

(3) ARM transmits the IEC103 data packet and IEC61850 data packet stored in the SRAM to the AES unit through DMA channel 3 for encryption.

(4) The encrypted IEC103 data packet is sent through the ARM control serial port UART 1, and the encrypted IEC61850 data packet is sent by the ARM control MAC and PHY chip, and supports Ethernet port and optical fiber interface.

The above-mentioned embodiment is a preferred embodiment of the present invention, but the embodiment of the present invention is not limited by the above-mentioned embodiment, and any other changes, modifications, substitutions, combinations, Simplifications should be equivalent replacement methods, and all are included in the protection scope of the present invention.

Claims (8)

1. A power system measurement and communication integrated chip supporting IEC61850, characterized in that, the integrated chip includes an acquisition module, a storage module, a processing module, an encryption and decryption module, a communication module, an Ethernet module, a transmission module and a chip internal bus; The on-chip bus includes an AHB high-speed system bus and an APB low-speed peripheral bus, connected through two AHB2APB bridges AHB2APB Bridege 0 and AHB2APB Bridege 1; The acquisition module includes an analog-to-digital converter ADC and a general-purpose digital input and output port GPIO, which are respectively used for measuring analog signals and collecting digital signals; The storage module includes an embedded fast memory EFLASH, a read-only memory ROM, and a static random access memory SRAM for storing data and programs; The processing module is a high-performance ARM926EJS microprocessor, which converts the collected data into data packets conforming to the IEC103 communication protocol and the IEC61850 communication protocol; The encryption and decryption module is an advanced encryption and decryption AES unit, which is used to realize the encryption and decryption functions of communication data; Described communication module comprises universal asynchronous transceiver transmitter UART 0 and UART 1, serial peripheral interface SPI, two-way serial interface I2C; The Ethernet module includes a physical address access controller MAC and a physical layer transceiver controller PHY; The transmission module is a direct memory access controller DMA; The high-performance ARM926EJS microprocessor, embedded fast memory EFLASH, read-only memory ROM, static random access memory SRAM, advanced encryption and decryption AES unit, physical address access controller MAC, direct memory access controller DMA and the AHB high-speed system Bus connection, the universal asynchronous transceiver transmitter UART 0, serial peripheral interface SPI, bidirectional serial interface I2C, general purpose digital input and output port GPIO and the APB low-speed system bus are connected and passed through AHB2APBBridege 0 and the AHB high-speed system Bus connection, the UART 1, the analog-to-digital converter ADC, the physical layer transceiver controller PHY are connected to the APB low-speed system bus and connected to the AHB high-speed system bus through AHB2APB Bridege 1. 2. A kind of power system measurement and communication integrated chip supporting IEC61850 according to claim 1, characterized in that, the analog-to-digital converter ADC is used to measure analog signals, and is a 16-bit analog-to-digital converter with 6 channels , the sampling rate of each channel is up to 16K, and the input voltage range is set to +/-10V or +/-5V; The general-purpose digital input and output ports GPIO are used for collecting digital signals, and are 32 32-bit digital input and output ports, and the input voltage range is 0-3.3V. 3. A kind of power system measurement and communication integrated chip supporting IEC61850 according to claim 1, characterized in that, The embedded fast memory EFLASH is an on-chip integrated 2M EFLASH for storing bootloader programs and protocol conversion configuration files; The read-only memory ROM is an integrated 16KB ROM in the chip, which is used to store the control program of the integrated chip; The static random access memory (SRAM) is an on-chip integrated 16KB SRAM, which is used for data storage during protocol conversion. 4. A kind of power system measurement and communication integration chip supporting IEC61850 according to claim 1, characterized in that, The control program of the high-performance ARM926EJS microprocessor is written under the Keil4 development environment, the chip is embedded in the UCOS-II real-time operating program, and the ARM processor controls the acquisition module to collect data and store it in the on-chip memory, and then convert the collected data In order to comply with the data packets of the IEC103 communication protocol and the IEC61850 communication protocol, finally control the Ethernet module and the communication interface to send the data packets. 5. A kind of power system measurement and communication integrated chip supporting IEC61850 according to claim 1, characterized in that, The advanced encryption and decryption AES unit adopts the AES algorithm with a packet length of 128bits and a key length of 128bits, and the encryption mode adopts the CBC packet mode, which is used to realize the encryption and decryption functions of communication data, and encrypts IEC103 data packets and IEC61850 data packets respectively. 6. A power system measurement and communication integrated chip supporting IEC61850 according to claim 1, characterized in that, The UART 0 of the communication module is used to send the data packet obtained after the advanced encryption and decryption AES unit encrypts the IEC103 data packet, and the UART 1, SPI, and I2C of the communication module are expansion interfaces for connecting and communicating with peripherals. 7. A kind of power system measurement and communication integrated chip supporting IEC61850 according to claim 1, characterized in that, The Ethernet module includes two 10/100M physical address access controllers MAC and two physical layer transceiver controllers PHY, which respectively support Ethernet port and optical fiber port connections, and are used to send advanced encryption and decryption AES units to perform IEC61850 data packets Encrypted data packets. 8. A power system measurement and communication integrated chip supporting IEC61850 according to claim 1, characterized in that, The direct memory access controller DMA includes 4 channels DMA, wherein, the channel 0 transmits the measurement data of the analog-to-digital converter ADC to the static random access memory SRAM, and the channel 1 transmits the general digital input and output ports GPIO, UART 0, SPI, The measured data of I2C is transmitted to SRAM, and the channel 3 transmits the IEC103 data packet and IEC61850 data packet converted by the high-performance ARM926EJS microprocessor to the advanced encryption and decryption AES unit.