CN105871761A - High order matrix switch, network on chip and communication method - Google Patents

Abstract

The present invention provides a high-order matrix switch, an on-chip network, and a communication method. The high-order matrix switch may include: at least one input port, at least one input queue, control logic, a switch matrix, and at least one output port; the input port uses The input queue is used to buffer the messages input from the corresponding input port; the control logic is used to determine the corresponding output port according to the messages buffered in the input queue; the switch matrix is used to The input queue and output port of a message create a data path for connecting the input queue and the output port, and use the data path to read the message from its corresponding input queue and transmit it to the corresponding output port; An output port is used to send each received message to the corresponding destination node. According to the solution, asynchronous communication can be realized, thereby reducing the integration area and power consumption of the network on chip.

Description

A high-order matrix switch, on-chip network and communication method

technical field

The invention relates to the technical field of integrated circuits, in particular to a high-order matrix switch, an on-chip network and a communication method.

Background technique

With the continuous development of integrated circuit technology, packaging and testing technologies, the degree of integration of a single chip is getting higher and higher, and the integration functions are becoming more and more complex.

At present, SOC (System On Chip, system on chip) is generally used as an integrated circuit, and multiple nodes and on-chip buses may be included in the SOC, wherein the on-chip bus is used to realize interconnection between various nodes in the SOC, and each node Data transmission is realized by sharing the on-chip bus.

However, the SOC uses an on-chip bus to realize data transmission as a main feature, and there will be a problem of a single global clock, which leads to problems of large integration area and power consumption of the SOC.

Contents of the invention

Embodiments of the present invention provide a high-order matrix switch, an on-chip network and a communication method to solve the problem of a single global clock.

In the first aspect, an embodiment of the present invention provides a high-order matrix switch, including: at least one input port, at least one input queue, control logic, switching matrix, and at least one output port; wherein,

Each input port is used to receive the message sent by the source node;

Each of the input queues corresponds to each input port and is used for buffering messages input from the corresponding input port;

The control logic is configured to determine a corresponding output port according to the messages buffered in the input queue;

The switching matrix is used to create a data path for connecting the input queue and the output port according to the input queue and output port of each message, and use the data path to read the message from its corresponding input queue , transmitted to the corresponding output port;

Each output port is used to send each received message to a corresponding destination node.

Wherein, the input queue includes: at least one input virtual channel and an input buffer space corresponding to each input virtual channel; wherein, each input virtual channel includes a corresponding number to distinguish it from other input virtual channels;

It further includes: a control unit, used for analyzing the virtual channel number in the virtual channel field in the packet header microchip when monitoring the message input from the input port; passing the message through the virtual channel number The corresponding input virtual channel is sent to the corresponding input buffer space.

Wherein, the control unit is specifically configured to use the message to lock the input virtual channel corresponding to the virtual channel number after parsing the virtual channel number, and pass the header chip of the message through the input Send the virtual channel to the corresponding input buffer space, and send the body flits and trailer flits of the message to the corresponding input buffer space through the input virtual channel in sequence, and release the input virtual channel after sending, for other messages.

Wherein, the control logic includes: a routing calculation submodule; wherein, the routing calculation submodule includes: a routing algorithm unit and an output request generation unit; where,

The routing algorithm unit is used to calculate the corresponding target output port according to the routing information of the target message cached in the input queue, and resolve the virtual channel number in the virtual channel field in the target message header chip, And determine the corresponding target output virtual channel according to the virtual channel number; wherein, each output port corresponds to at least one output virtual channel;

an output request generation unit, configured to generate a first request for the target output virtual channel and a second request for the target output port for the target message, and send the first request and the second request ask.

Wherein, the control logic further includes: an arbitration submodule; wherein, the arbitration submodule includes: an output virtual channel arbitration unit and an output port arbitration unit; wherein,

The output virtual channel arbitration unit is configured to, when receiving the first request, judge whether the first request satisfies the first condition, and when the judging result includes that the first request satisfies the first condition, arbitrate succeed, and allocate the target output virtual channel to the target message;

The output port arbitration unit is configured to judge whether the second request satisfies the second condition when receiving the second request, and if the judgment result includes that the second request satisfies the second condition, the arbitration is successful , assigning the target output port to the target packet, and triggering the switching matrix to perform a corresponding operation.

Wherein, it further includes: a priority configuration unit, which is used to configure the priority of the message buffered in each input queue, and is used to configure the priority of each output virtual channel;

The first request satisfies the first condition, including: the output buffer space corresponding to the target output virtual channel includes free space, and the entire message of the last round of arbitration has been transmitted in the target output virtual channel End; wherein, each output virtual channel corresponds to an output buffer space;

and / or,

The second request meeting the second condition includes: among the multiple output virtual channels simultaneously requesting the target output port, the target output virtual channel has the highest priority.

Wherein, the switching matrix is specifically used to open up the target output virtual channel between the input queue in which the target message is buffered and the target output port, and use the target output virtual channel to transmit the target message to the target output port;

The priority configuration unit is further configured to adjust the priority of the target output virtual channel to the highest when the switch matrix uses the target output virtual channel to transmit the target message, and After the head flit, body flit and tail flit are transmitted, the priority of each output virtual channel corresponding to the target output port is adjusted according to the polling mechanism.

In the second aspect, the embodiment of the present invention also provides an on-chip network, including the high-order matrix switch described in the above-mentioned one, and a plurality of nodes; wherein,

A source node among the plurality of nodes is configured to send a target message to the high-order matrix switch;

A destination node among the multiple nodes is configured to receive the target message sent by the high-order matrix switch.

In the third aspect, the embodiment of the present invention also provides a communication method based on the above-mentioned network-on-chip, which is applied to a high-order matrix switch, including:

Receive the target message sent by the source node through the target input port;

Buffering the target packet into a target input queue corresponding to the target input port;

determining a corresponding target output port according to the target message;

creating a target data path connecting said target input queue and said target output port;

Using the target data path to read the target message from the target input queue and transmit it to the target output port;

The target message is sent to a corresponding destination node by using the target output port.

Wherein, the buffering of the target message into the target input queue corresponding to the target input port includes:

When monitoring the target message input from the target input port, parsing the virtual channel number in the virtual channel field in the target message header chip;

And using the target message to lock the target input virtual channel corresponding to the parsed virtual channel number;

sending the header flake of the target message to the corresponding target input buffer space through the target input virtual channel;

sending the body flits and trailer flits of the target message to the target input buffer space through the target input virtual channel in sequence;

The target input virtual channel is released after the sending is completed for use by other messages.

An embodiment of the present invention provides a high-order matrix switch, an on-chip network, and a communication method. By using at least one input port and at least one output port in the high-order matrix switch, data is transmitted between the input port and the output port through a data path. Therefore, each node can work in an independent clock domain, and asynchronous communication can be realized between different nodes through the high-order matrix switch, so that the integration area and power consumption of the network on chip can be reduced.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present invention, those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of a high-order matrix switch provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of another high-order matrix switch provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of a network-on-chip structure provided by an embodiment of the present invention;

Fig. 4 is a flow chart of a communication method provided by an embodiment of the present invention;

Fig. 5 is a flowchart of another communication method provided by an embodiment of the present invention.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the protection of the present invention. scope.

Please refer to FIG. 1, an embodiment of the present invention provides a high-order matrix switch, which may include the following: at least one input port 101, at least one input queue 102, control logic 103, switching matrix 104 and at least one Output port 105; where,

Each input port 101 is used to receive the message sent by the source node;

Each of the input queues 102 corresponds to each input port 101 and is used for buffering messages input from the corresponding input port 101;

The control logic 103 is configured to determine the corresponding output port 105 according to the messages buffered in the input queue 102;

The switching matrix 104 is configured to create a data path for connecting the input queue 102 and the output port 105 according to the input queue 102 and the output port 105 of each message, and use the data path to transfer the message from its corresponding Read out from the input queue 102 and transmit to the corresponding output port 105;

Each output port 105 is used to send each received message to a corresponding destination node.

It can be seen that using at least one input port and at least one output port in the high-order matrix switch, data transmission is performed between the input port and the output port through a data path, so each node can work in an independent clock domain, different Asynchronous communication can be realized between nodes through the high-order matrix switch, thereby reducing the integration area and power consumption of the network on chip.

It should be noted that the high-order matrix switch can be a communication node used to realize data communication between the source node and the destination node in the NOC (Network On Chip, network on chip), and the message sent by the source node passes through the high-order matrix switch. The input port is input, and the output port of the high-order matrix switch is output to the destination node.

The following takes the high-order matrix switch including input port 1, input port 2, ..., input port n, output port 1, output port 2, ..., output port m as an example, wherein n and m are integers not less than 1 , the high-order matrix switch provided by the embodiment of the present invention will be further described in detail.

In an embodiment of the present invention, each input interface corresponds to an input queue, and each input queue may include at least one input virtual channel and an input buffer space corresponding to each input virtual channel, and each input virtual channel includes a corresponding number to distinguish it from other input virtual channels.

For example, each input queue includes 4 input virtual channels and 4 input buffer spaces respectively corresponding to the input virtual channels. Then, taking input port 1 as an example, it can correspond to the four input virtual channels of input virtual channel 1, input virtual channel, input virtual channel 3 and input virtual channel 4, and corresponding input buffer space 1, input buffer space 2, input buffer Space 3 and input cache space 4.

Please refer to FIG. 2, in an embodiment of the present invention, the high-order matrix switch may further include: a control unit 201, connected to each input port and each input array, for monitoring the input from the input port When the message is sent, the virtual channel number is analyzed in the virtual channel field in the header flit Flit; and the message is sent to the corresponding input buffer space through the input virtual channel corresponding to the virtual channel number.

During the generation of the message, the source node adds the virtual channel number to the virtual channel field in the header Flit of the message to ensure that the high-order matrix switch can use the corresponding input virtual channel to cache the message in the corresponding input buffer space middle.

For example, the virtual channel number analyzed by the control unit 201 in the virtual channel field in the message header Flit is 1, then the control unit may buffer the message into the input buffer space 1 through the input virtual channel 1 for storage.

In an embodiment of the present invention, since a message generally includes a header Flit, at least one body Flit, and a tail Flit, the control unit 201 can use the message to perform The input virtual channel corresponding to the channel number is locked, and the head slice of the message is sent to the corresponding input buffer space through the input virtual channel, and the body slice and tail slice of the message are sequentially passed through the The input virtual channel is sent to the corresponding input buffer space until the entire message is buffered in the input buffer space, then the input virtual channel is released for use by other messages.

Wherein, when the body Flit and the tail Flit of the message are buffered, it is not necessary to judge the virtual channel number on them, and only need to transmit them along with the header Flit.

In an embodiment of the present invention, the input queue 102 may adopt a first-in-first-out (FIFO) policy, and messages buffered first are read out first.

Please refer to FIG. 2 , in an embodiment of the present invention, the control logic 103 may include: a routing calculation submodule 1031 and an arbitration submodule 1032 .

The functions of the routing sub-module 1031 and the arbitration sub-module 1032 will be described respectively below.

First, the route calculation sub-module 1031 may include: a route algorithm unit 10311 and an output request generation unit 10312; wherein,

The routing algorithm unit 10311 is used to calculate the target output port and the target output virtual channel of each message to be read in the input buffer queue, specifically, calculate the corresponding target output port according to the routing information of the target message cached in the input queue port, and analyze the virtual channel number in the virtual channel field in the target packet header chip, and determine the corresponding target output virtual channel according to the virtual channel number, and send the determined target output port and target output virtual channel to Output request generation unit 10312.

Wherein, each output port corresponds to at least one output virtual channel and a corresponding output buffer queue.

Wherein, the routing information may include the IP address of the destination node.

The output request generation unit 10312 is configured to receive the target output port and the target output virtual channel sent by the routing algorithm unit 10311, and generate a first request for the target output virtual channel and a second request for the target output port for the target message request, and send the first request and the second request.

In one embodiment of the present invention, the target output port and the target output virtual channel calculated by the routing algorithm unit 10311 can be stored in the register until the next header Flit arrives, so that the entire message in which the header Flit is located uses the output Virtual channels and output ports for data transmission. After the output request generating unit 10312 receives the calculation result of the routing algorithm unit 10311, the first request and the second request are kept until the target output port receives a release signal.

Secondly, the arbitration sub-module 1032 may include: an output virtual channel arbitration unit 10321 and an output port arbitration unit 10322 . in,

Output virtual channel arbitration unit 10321, configured to judge whether the first request satisfies the first condition when receiving the first request, and if the judging result includes that the first request satisfies the first condition, the arbitration is successful , and allocate the target output virtual channel to the target message.

In an embodiment of the present invention, a Round-Robin polling mechanism may be used to arbitrate these requests.

Please refer to FIG. 2, in one embodiment of the present invention, the high-order matrix switch may further include: a priority configuration unit 202, configured to configure priorities for messages buffered in each input queue, and for each Output virtual channel configuration priority. Wherein, the configuration of the priority can be configured according to information such as the importance and urgency of the message, so as to ensure that the message with a higher priority is transmitted first.

In an embodiment of the present invention, the first request meets the first condition to determine that the arbitration is successful, and the following two conditions need to be met simultaneously:

1. The output buffer space corresponding to the target output virtual channel includes free space; this embodiment uses a credit-based flow control mechanism to prevent packet loss caused by the upstream module continuing to forward data when the buffer space of the downstream module is full question.

2. The target has completed the transmission of the entire packet of the last round of arbitration in the output virtual channel.

The output port arbitration unit 10322 is configured to judge whether the second request satisfies the second condition when receiving the second request, and if the judgment result includes that the second request satisfies the second condition, the arbitration is successful, and assigning the target output port to the target message, and triggering the switching matrix to perform a corresponding operation.

In an embodiment of the present invention, the second request satisfies the second condition to determine that the arbitration is successful, which may satisfy the following condition: Among the multiple output virtual channels that simultaneously request the target output port, the priority of the target output virtual channel Highest.

In an embodiment of the present invention, after the first request and the second request are successfully arbitrated, the target output port and the target output virtual channel are allocated to the target message.

In an embodiment of the present invention, the switch matrix 104 is a path structure that fully interconnects the input port and the output port, and is specifically used to connect the input queue with the target message buffered and the target output port. The target output virtual channel is opened, so that the target output virtual channel is used as a data path, and a read signal is sent to the input queue of the target message, so as to read the target message from the input queue, and use the The target output virtual channel transmits the target message to the target output port.

Further, the priority configuration unit 202 may be further configured to adjust the priority of the target output virtual channel to be the highest when the switch matrix uses the target output virtual channel to transmit the target message, and After the header flit, body flit and trailer flit of the target message are transmitted, the priority of each output virtual channel corresponding to the target output port is adjusted according to the polling mechanism.

According to the above embodiment, each input port can send a message at the same clock, and each output port can output a message at the same clock, so that parallel communication of multiple CPU cores can be supported, and the overall performance and throughput of the system can be improved. As well as good scalability, there is no limit to the address space, and theoretically the number of integrated source nodes and destination nodes is not limited. In addition, using the global asynchronous and local synchronous mechanism, each node works in an independent clock domain, and different nodes realize asynchronous communication through the high-order matrix switch, which can well solve the area and power consumption problems caused by the global single clock .

Please refer to FIG. 3 , an embodiment of the present invention also provides an on-chip network, including any one of the high-order matrix switches 301 described above, and a plurality of nodes 302; wherein,

A source node among the plurality of nodes is configured to send a target message to the high-order matrix switch;

A destination node among the multiple nodes is configured to receive the target message sent by the high-order matrix switch.

According to the network on chip provided by the embodiment of the present invention, parallel communication of each node can be realized, the efficiency of data transmission is improved, the integration area of the network on chip is reduced, and the power consumption can be reduced.

In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

Please refer to FIG. 4, an embodiment of the present invention also provides a network-on-chip communication method, which is applied to a high-order matrix switch, and may include the following steps:

Step 401: Receive the target message sent by the source node through the target input port;

Step 402: buffer the target packet into the target input queue corresponding to the target input port;

Step 403: Determine the corresponding target output port according to the target message;

Step 404: Create a target data path for connecting the target input queue and the target output port;

Step 405: Using the target data path to read the target message from the target input queue, and transmit it to the target output port;

Step 406: Send the target message to a corresponding destination node by using the target output port.

Please refer to FIG. 5, in one embodiment of the present invention, step 402 may include:

Step 501: When detecting the target message input from the target input port, parse out the virtual channel number in the virtual channel field in the target message header flake;

Step 502: and use the target message to lock the target input virtual channel corresponding to the parsed virtual channel number;

Step 503: Send the header flake of the target message to the corresponding target input buffer space through the target input virtual channel;

Step 504: sending the body flits and trailer flits of the target message to the target input buffer space through the target input virtual channel in sequence;

Step 505: Release the target input virtual channel for use by other messages after sending.

In an embodiment of the present invention, a message buffered into the input buffer space generally can go through the following steps: output port allocation, output virtual channel allocation, arbitration and data transmission. After the message is processed through these four stages, the final Forward it.

Since only the header Flit contains the routing information in the message, after the header Flit is assigned the output port and the output virtual channel successfully, other body Flits and tail Flits can directly use the allocation result of the header Flit, skipping the output port allocation and output The process of virtual channel allocation directly enters arbitration and data transmission.

In summary, the embodiments of the present invention can at least achieve the following beneficial effects:

1. In the embodiment of the present invention, using at least one input port and at least one output port in the high-order matrix switch, data transmission is performed between the input port and the output port through a data path, so each node can work In an independent clock domain, different nodes can realize asynchronous communication through the high-order matrix switch, so that the integrated area and power consumption of the network on chip can be reduced.

2. In the embodiment of the present invention, each input port can send a message under the same clock, and each output port can output a message under the same clock, so that parallel communication of multiple CPU cores can be supported, and the overall performance and performance of the system can be improved. throughput. As well as good scalability, there is no limit to the address space, and theoretically the number of integrated source nodes and destination nodes is not limited. In addition, using the global asynchronous and local synchronous mechanism, each node works in an independent clock domain, and different nodes realize asynchronous communication through the high-order matrix switch, which can well solve the area and power consumption problems caused by the global single clock .

3. In the embodiment of the present invention, parallel communication of each node can be realized, the data transmission efficiency is improved, the integration area of the network on chip is reduced, and the power consumption can be reduced.

The information exchange and execution process among the units in the above-mentioned device are based on the same concept as the method embodiment of the present invention, and the specific content can refer to the description in the method embodiment of the present invention, and will not be repeated here.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or sequence. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional same elements in the process, method, article or apparatus comprising said element.

Those of ordinary skill in the art can understand that all or part of the steps to realize the above method embodiments can be completed by program instructions related hardware, and the aforementioned programs can be stored in a computer-readable storage medium. When the program is executed, the It includes the steps of the above method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other various media that can store program codes.

Finally, it should be noted that the above descriptions are only preferred embodiments of the present invention, and are only used to illustrate the technical solution of the present invention, and are not used to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present invention are included in the protection scope of the present invention.

Claims (10)

1. A high-order matrix switch, characterized in that, includes: at least one input port, at least one input queue, control logic, switching matrix and at least one output port; wherein, Each input port is used to receive the message sent by the source node; Each of the input queues corresponds to each input port and is used for buffering messages input from the corresponding input port; The control logic is configured to determine a corresponding output port according to the messages buffered in the input queue; The switching matrix is used to create a data path for connecting the input queue and the output port according to the input queue and output port of each message, and use the data path to read the message from its corresponding input queue , transmitted to the corresponding output port; Each output port is used to send each received message to a corresponding destination node. 2. high-order matrix switch according to claim 1, is characterized in that, The input queue includes: at least one input virtual channel and an input buffer space corresponding to each input virtual channel; wherein, each input virtual channel includes a corresponding number to distinguish it from other input virtual channels; It further includes: a control unit, used for analyzing the virtual channel number in the virtual channel field in the packet header microchip when monitoring the message input from the input port; passing the message through the virtual channel number The corresponding input virtual channel is sent to the corresponding input buffer space. 3. The high-order matrix switch according to claim 2, wherein the control unit is specifically configured to, after parsing out the virtual channel number, use the message to input virtual channel number corresponding to the virtual channel number. The channel is locked, and the header slice of the message is sent to the corresponding input buffer space through the input virtual channel, and the body slice and tail slice of the message are sent to the corresponding input buffer through the input virtual channel in sequence. The input buffer space, and release the input virtual channel after sending, for other messages to use. 4. The high-order matrix switch according to claim 1, wherein said control logic comprises: a routing calculation submodule; wherein said routing calculation submodule comprises: a routing algorithm unit and an output request generation unit; wherein, The routing algorithm unit is used to calculate the corresponding target output port according to the routing information of the target message cached in the input queue, and resolve the virtual channel number in the virtual channel field in the target message header chip, And determine the corresponding target output virtual channel according to the virtual channel number; wherein, each output port corresponds to at least one output virtual channel; an output request generation unit, configured to generate a first request for the target output virtual channel and a second request for the target output port for the target message, and send the first request and the second request ask. 5. The high-order matrix switch according to claim 4, wherein the control logic further comprises: an arbitration submodule; wherein the arbitration submodule comprises: an output virtual channel arbitration unit and an output port arbitration unit; wherein , The output virtual channel arbitration unit is configured to, when receiving the first request, judge whether the first request satisfies the first condition, and when the judging result includes that the first request satisfies the first condition, arbitrate succeed, and allocate the target output virtual channel to the target message; The output port arbitration unit is configured to judge whether the second request satisfies the second condition when receiving the second request, and if the judgment result includes that the second request satisfies the second condition, the arbitration is successful , assigning the target output port to the target packet, and triggering the switching matrix to perform a corresponding operation. 6. high-order matrix switch according to claim 5, is characterized in that, It further includes: a priority configuration unit, configured to configure the priority of the messages buffered in each input queue, and configured to configure the priority of each output virtual channel; The first request satisfies the first condition, including: the output buffer space corresponding to the target output virtual channel includes free space, and the entire message of the last round of arbitration has been transmitted in the target output virtual channel End; wherein, each output virtual channel corresponds to an output buffer space; and / or, The second request meeting the second condition includes: among the multiple output virtual channels simultaneously requesting the target output port, the target output virtual channel has the highest priority. 7. high-order matrix switch according to claim 6, is characterized in that, The switching matrix is specifically configured to open the target output virtual channel between the input queue in which the target message is buffered and the target output port, and use the target output virtual channel to transmit the target message to said target output port; The priority configuration unit is further configured to adjust the priority of the target output virtual channel to the highest when the switch matrix uses the target output virtual channel to transmit the target message, and After the head flit, body flit and tail flit are transmitted, the priority of each output virtual channel corresponding to the target output port is adjusted according to the polling mechanism. 8. An on-chip network, characterized in that it comprises the high-order matrix switch and a plurality of nodes according to any one of the above-mentioned claims 1-7; wherein, A source node among the plurality of nodes is configured to send a target message to the high-order matrix switch; A destination node among the multiple nodes is configured to receive the target message sent by the high-order matrix switch. 9. A method for communicating with a network on chip based on the above-mentioned claim 7, characterized in that, being applied to a high-order matrix switch, comprising: Receive the target message sent by the source node through the target input port; Buffering the target packet into a target input queue corresponding to the target input port; determining a corresponding target output port according to the target message; creating a target data path connecting said target input queue and said target output port; Using the target data path to read the target message from the target input queue and transmit it to the target output port; The target message is sent to a corresponding destination node by using the target output port. 10. The method according to claim 9, wherein said buffering said target message into a target input queue corresponding to said target input port comprises: When monitoring the target message input from the target input port, parsing the virtual channel number in the virtual channel field in the target message header chip; And using the target message to lock the target input virtual channel corresponding to the parsed virtual channel number; sending the header flake of the target message to the corresponding target input buffer space through the target input virtual channel; sending the body flits and trailer flits of the target message to the target input buffer space through the target input virtual channel in sequence; The target input virtual channel is released after the sending is completed for use by other messages.