CN105870066B - Method for manufacturing non-volatile memory - Google Patents

Abstract

The invention discloses a method for manufacturing a non-volatile memory. A composite layer, a first conductor layer and a first capping layer are sequentially formed on the substrate. A plurality of element isolation structures extending along a first direction are formed in the substrate, and surfaces of the above element isolation structures are located between the first capping layer and the substrate. The first capping layer, the first conductor layer, the composite layer and the substrate are patterned to form a plurality of trenches extending along a second direction in the substrate, where the first direction and the second direction are interleaved. An insulating layer and a second conductor layer are formed in the trench, wherein the insulating layer surrounds and covers the second conductor layer. The first top cover layer is removed, and a second top cover layer is formed on both sides of the exposed insulation layer. Using the second top cover layer as a mask, the first conductor layer and the composite layer are patterned so that the first conductor layer forms a control gate.

Description

Manufacturing method of non-volatile memory

technical field

The present invention relates to a manufacturing method of a memory element, and in particular to a manufacturing method of a non-volatile memory.

Background technique

With the rapid development of the electronic information industry, the production of memory components is one of the important technologies in the current semiconductor industry. Among all kinds of memory-related products, non-volatile memory has become a personal memory because it can store, read or erase data multiple times, and the stored data will not disappear after power off. A memory element widely used in computers and electronic equipment.

A typical non-volatile memory device may have a stacked-gate structure, including a floating gate and a control gate made of doped polysilicon. The floating gate is located between the control gate and the substrate, and is not connected to any circuit, while the control gate is connected to the word line (Word Line), and also includes tunneling oxide (Tunneling Oxide) and inter-gate dielectric Layers (Inter-Gate Dielectric Layer) are respectively located between the substrate and the floating gate and between the floating gate and the control gate.

In recent years, in the manufacturing technology of memory devices, a charge trapping layer including silicon nitride has appeared to replace the traditional polysilicon floating gate design. This kind of silicon nitride charge trapping layer usually has a layer of silicon oxide on the upper and lower layers, forming a stacked structure consisting of silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide, ONO for short) layers. ), the device with such a gate structure may be called silicon/silicon oxide/silicon nitride/silicon oxide/silicon (silicon-oxide-nitride-oxide-silicon, SONOS for short) memory device.

With the rapid development of technology, the integration level of semiconductor-related components continues to increase, so the size of various memory components must be further reduced in order to speed up the operation. However, when the size of the memory device is to be reduced, serious problems such as short channel effect and stability degradation will occur. In order to further improve the reliability and stability of components, it is necessary to provide a technical solution capable of improving the above problems.

Contents of the invention

The object of the present invention is to provide a manufacturing method of a non-volatile memory, which can avoid short channel effects and further improve the reliability and stability of memory elements.

In order to achieve the above-mentioned purpose, the manufacturing method of the non-volatile memory provided by the present invention includes: sequentially forming a composite layer, a first conductor layer, and a first top cover layer on a substrate; , the composite layer, and the substrate are patterned to form a plurality of shallow grooves in the substrate, and the shallow grooves extend along the first direction; element isolation structures are respectively formed in the shallow grooves, and the surface of the element isolation structures is located in the first direction. Between a top cover layer and the base; patterning the first top cover layer, the first conductor layer, the composite layer and the base to form a plurality of grooves in the base, the grooves extending along the second direction, wherein the first One direction is interlaced with the second direction; an insulating layer and a second conductor layer are formed in the trench, wherein the insulating layer surrounds and covers the second conductor layer; the first top cover layer is removed, and the exposed insulating layer is forming a second top cover layer on both sides; and using the second top cover layer as a mask to pattern the first conductor layer and the composite layer, so that the first conductor layer is formed as a control gate.

In an embodiment of the present invention, the step of forming the insulating layer and the second conductor layer in the trench includes: forming a first insulating material layer on the inner wall of the trench; forming a second conductor material layer to fill the trench; layer; removing at least a portion of the second layer of conductive material in the trench; and forming a second layer of insulating material to cover the second layer of conductive material.

In an embodiment of the present invention, the step of forming a second top cover layer on both sides of the exposed insulating layer includes: forming a top cover material layer on the insulation layer and the first conductor layer; removing the top cover material part of the layer.

In an embodiment of the present invention, the above method further includes performing a doping process on the substrate to form a source region and a drain region.

In an embodiment of the present invention, the step of forming the element isolation structure includes: forming an insulating material layer in each shallow trench; planarizing the insulating material layer; and removing a part of the insulating material layer.

In an embodiment of the present invention, the composite layer includes silicon oxide/silicon nitride/silicon oxide.

In an embodiment of the present invention, the material of the first conductive layer and the second conductive layer includes doped polysilicon.

In an embodiment of the present invention, the material of the first capping layer includes silicon nitride.

In an embodiment of the present invention, the material of the second capping layer includes silicon nitride.

In an embodiment of the present invention, the insulating layer is made of silicon oxide.

Based on the above, through the manufacturing method of the non-volatile memory provided by the present invention, the short channel effect of the memory element can be avoided, and the reliability and stability of the semiconductor element can be further improved. In addition, in the manufacturing method provided by the present invention, the manufacturing steps can be further simplified by adopting a self-aligned process, so that the non-volatile memory element can be manufactured more efficiently.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Description of drawings

1A to 1G are schematic cross-sectional flow diagrams of a manufacturing method of a non-volatile memory according to an embodiment of the present invention;

FIG. 2A to FIG. 2F are another schematic cross-sectional views of the flow of the manufacturing method of the non-volatile memory according to the embodiment of the present invention.

Symbol Description

100: base

102: composite layer

102a: Charge Storage Structures

104: first conductor layer

104a: Control grid

106: First cap layer

108: Groove

110, 200: insulation layer

110a: first insulating material layer

110b: second insulating material layer

112: Second conductor layer

112a: Second layer of conductive material

114: Second capping layer

114a: Top cover material layer

116: source region

118: drain region

Detailed ways

1A to 1G are schematic cross-sectional flow diagrams of a manufacturing method of a non-volatile memory according to an embodiment of the present invention. It should be noted that the cross sections shown in FIGS. 1A to 1G are parallel to the direction of the bit line (bit-line) of the memory cell (or perpendicular to the direction of the word line (word line) of the memory cell); The section is parallel to the direction of the word line of the memory cell (or perpendicular to the direction of the bit line of the memory cell).

First, referring to FIG. 1A and FIG. 2A , a composite layer 102 , a first conductor layer 104 and a first capping layer 106 are sequentially formed on a substrate 100 . The substrate 100 is, for example, a silicon substrate.

The composite layer 102 is composed of, for example, a bottom dielectric layer, a charge trapping layer and a top dielectric layer. The material of the bottom dielectric layer is, for example, silicon oxide, and its formation method is, for example, thermal oxidation. The material of the charge trapping layer is, for example, silicon nitride, and its formation method is, for example, chemical vapor deposition. The material of the top dielectric layer is, for example, silicon oxide, and its formation method is, for example, chemical vapor deposition. Certainly, the bottom dielectric layer and the top dielectric layer may also be made of other similar materials. The material of the charge trapping layer is not limited to silicon nitride, and can also be other materials capable of trapping charges therein, such as tantalum oxide layer, strontium titanate layer, hafnium oxide layer, or doped polysilicon. In this embodiment, the material of the composite layer 102 is, for example, a silicon oxide/silicon nitride/silicon oxide composite layer.

The material of the first conductive layer 104 is, for example, doped polysilicon, and its formation method is, for example, to form a layer of undoped polysilicon layer by chemical vapor deposition, and then perform ion implantation to form it. formed by chemical vapor deposition.

The material of the first capping layer 106 is, for example, silicon nitride, and its formation method is, for example, chemical vapor deposition.

Next, the first capping layer 106, the first conductive layer 104, the composite layer 102, and the substrate 100 are patterned to form a plurality of shallow trenches in the substrate 100, and the shallow trenches are along the first direction (ie , extending in a direction parallel to the bit line direction of the memory cell to be formed), and then forming an insulating layer 200 in each shallow trench, so as to obtain the structure shown in FIG. 2A . The material of the insulating layer 200 is, for example, silicon oxide. The method for forming the above-mentioned insulating layer 200 is, for example, to first form an insulating material layer in each shallow trench by chemical vapor deposition, then, after planarizing the insulating material layer by chemical mechanical polishing, etch back to remove a part of the insulating material. material layer to form an insulating layer 200 , wherein the surface of the insulating layer 200 is located between the first capping layer 106 and the substrate 100 , and the insulating layer 200 serves as an element isolation structure.

Next, please refer to FIG. 1B and FIG. 2B , use a mask (not shown) to pattern the first capping layer 106, the first conductor layer 104, the composite layer 102, and the substrate 100 to form multiple layers in the substrate 100. trenches 108 extending along the second direction (ie, the direction parallel to the direction of the word line of the memory cell to be formed, which is crossed with the aforementioned first direction). The bottoms of these trenches 108 are located in the substrate 100, and counted from the surface of the first capping layer 106, the depth of the trenches 108 is, for example, 100nm˜500nm, and the bottoms of the trenches 108 and the unpatterned The distance between the surfaces of the substrate 100 is, for example, 10 nm˜100 nm, but not limited thereto. Those skilled in the art should understand that by removing a portion of the substrate 100 so that the bottom of the trench 108 is located within the substrate 100, a longer channel length can be obtained, thereby avoiding the short channel effect. occur.

Afterwards, please refer to FIG. 1C and FIG. 2C , first form a conformal first insulating material layer 110 a on the inner wall of the trench 108 , and then form on the first insulating material layer 110 a to fill the remaining part of the trench 108 . The second conductive material layer 112a. The material of the first insulating material layer 110 a is, for example, silicon oxide. The material of the second conductive material layer 112a is, for example, doped polysilicon. The method for forming the first insulating material layer 110a is, for example, chemical vapor deposition, and the method for forming the second conductive material layer 112a is, for example, using chemical vapor deposition in conjunction with ion implantation steps, or by in-situ doping. Formed with chemical vapor deposition.

Then, referring to FIG. 1D and FIG. 2D , at least a part of the second conductive material layer 112 a in the trench 108 is removed, and then a second insulating material layer 110 b is formed. The second insulating material layer 110b covers the surface of the second conductive material layer 112a. Thus, the insulating layer 110 and the second conductive layer 112 can be formed in the trench 108 , and the insulating layer 110 composed of the first insulating material layer 110 a and the second insulating material layer 110 b surrounds and covers the second conductive layer 112 .

The material of the second conductive layer 112 is, for example, doped polysilicon. In addition, the above-mentioned method of removing at least a part of the second conductive material layer 112a in the trench and then forming the second insulating material layer 110b is, for example, first performing planarization by chemical mechanical polishing, and then performing etch back to remove At least a part of the second conductive material layer 112a is removed, and then the second insulating material layer 110b is deposited by chemical vapor deposition, and finally chemical mechanical polishing is performed again. In addition, the material of the second insulating material layer 110b can be the same as that of the first insulating material layer 110a, such as silicon oxide.

Next, referring to FIG. 1E and FIG. 2E , the first capping layer 106 is removed. The method of removing the first capping layer 106 is, for example, wet etching using an etchant such as phosphoric acid (H ₃ PO ₄ ). Then, a cap material layer 114 a is formed on the insulating layer 110 and the first conductor layer 104 exposed after the removal of the first cap layer 106 . The material of the cap material layer 114 a is, for example, silicon nitride. The method of forming the cap material layer 114a is, for example, chemical vapor deposition.

Referring to FIG. 1F and FIG. 2F , a part of the cap material layer 114 a is removed, and second cap layers 114 are respectively formed on both sides of the exposed insulating layer 110 . A method for removing a part of the cap material layer 114 a is, for example, an anisotropic etching method.

Finally, referring to FIG. 1G, the first conductive layer 104 and the composite layer 102 are patterned using the second capping layer 114 as a mask, and the patterning uses an anisotropic etching process, so that the first conductive layer 104 is formed as Control grid 104a. The patterned composite layer 102 is, for example, a charge storage structure 102a, and the second conductive layer 112 is, for example, a word line gate. In addition, a doping process can be further performed on the substrate 100 to form a source region 116 and a drain region 118 , where 116 can also be a drain region and 118 can be a source region.

To sum up, the manufacturing method of the non-volatile memory provided by the present invention can avoid the short channel effect of the memory element, and can further improve the reliability and stability of the semiconductor element. Specifically, in the manufacturing method provided by the present invention,

By removing a part of the substrate to form a deep trench, a device with a longer channel length can be obtained, thereby avoiding the occurrence of short channel effects; in addition, by using a damascene process and self-alignment The manufacturing process (self-aligned process), etc., can further simplify the manufacturing process steps that had to use photomasks in the past, so that components such as single memory cell binary (2bit/cell) SONOS memory can be manufactured more efficiently.

Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the appended claims.

Claims (10)

1. a kind of manufacturing method of non-volatility memorizer, including：

A composite layer, one first conductor layer and one first cap layer are sequentially formed in a substrate；

First cap layer, first conductor layer, the composite layer and the substrate are patterned, to be formed in the substrate Multiple shallow trench, those shallow trench extend along a first direction；

A component isolation structure is respectively formed in those shallow trench, the surface of the component isolation structure is located at the cap layer and is somebody's turn to do Between substrate；

First cap layer, first conductor layer, the composite layer and the substrate are patterned, to be formed in the substrate Multiple grooves, those grooves extend along a second direction, and wherein the first direction interlocks with the second direction；

An insulating layer and one second conductor layer are formed in those grooves, the wherein insulating layer surround and coats second conductor Layer；

First cap layer is removed, and one second cap layer is respectively formed in the both sides of the insulating layer exposed；And

Using second cap layer as mask, first conductor layer and the composite layer are patterned, so that first conductor layer is formed Grid in order to control.

2. the manufacturing method of non-volatility memorizer as described in claim 1, wherein forming the insulating layer in those grooves And the step of second conductor layer, includes：

One first insulation material layer is formed on those trench walls；

Form one second conductor material layer for filling up those grooves；

At least remove a part for second conductor material layer in those grooves；And

One second insulation material layer is formed, to cover second conductor material layer.

3. the manufacturing method of non-volatility memorizer as described in claim 1, wherein in the both sides of the insulating layer exposed The step of being respectively formed second cap layer include：

A cap material layer is formed on the insulating layer and first conductor layer；And

Remove a part for the cap material layer.

4. the manufacturing method of non-volatility memorizer as described in claim 1, further includes：A doping is carried out to the substrate to make Technique, to form source area and drain region.

5. the manufacturing method of non-volatility memorizer as described in claim 1, wherein the step of forming the component isolation structure Including：

An insulation material layer is formed in the respectively shallow trench；

The insulation material layer is planarized；And

Remove the insulation material layer of a part.

6. the manufacturing method of non-volatility memorizer as described in claim 1, the material of the wherein composite layer include silica/ Nitrogenize silicon/oxidative silicon.

7. the manufacturing method of non-volatility memorizer as described in claim 1, wherein first conductor layer and second conductor The material of layer includes DOPOS doped polycrystalline silicon.

8. the manufacturing method of non-volatility memorizer as described in claim 1, wherein the material of first cap layer includes nitrogen SiClx.

9. the manufacturing method of non-volatility memorizer as described in claim 1, wherein the material of second cap layer includes nitrogen SiClx.

10. the manufacturing method of non-volatility memorizer as described in claim 1, wherein the material of the insulating layer includes oxidation Silicon.