CN105826261A - Transistor forming method - Google Patents
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- CN105826261A CN105826261A CN201510010126.1A CN201510010126A CN105826261A CN 105826261 A CN105826261 A CN 105826261A CN 201510010126 A CN201510010126 A CN 201510010126A CN 105826261 A CN105826261 A CN 105826261A
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- 239000000463 material Substances 0.000 claims abstract description 187
- 239000004065 semiconductor Substances 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 125000006850 spacer group Chemical group 0.000 claims description 150
- 238000005530 etching Methods 0.000 claims description 37
- 239000000243 solution Substances 0.000 claims description 29
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 28
- 238000000151 deposition Methods 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 20
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 18
- 238000001039 wet etching Methods 0.000 claims description 17
- 238000005516 engineering process Methods 0.000 claims description 16
- 150000002500 ions Chemical class 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 13
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 9
- 238000005137 deposition process Methods 0.000 claims description 9
- 239000002019 doping agent Substances 0.000 claims description 7
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- 238000002955 isolation Methods 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
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- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 208000014674 injury Diseases 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- PDKGWPFVRLGFBG-UHFFFAOYSA-N hafnium(4+) oxygen(2-) silicon(4+) Chemical compound [O-2].[Hf+4].[Si+4].[O-2].[O-2].[O-2] PDKGWPFVRLGFBG-UHFFFAOYSA-N 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
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- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- 230000001105 regulatory effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a transistor forming method. The method comprises steps: a semiconductor substrate is provided, wherein the semiconductor substrate comprises a PMOS area and an NMOS area; gate structures with mask layers at the top are formed on the PMOS area and the NMOS area; a first side wall is formed on the surface of the side wall of each gate structure; a second side wall material layer and a third side wall material layer are formed on the surface of the semiconductor substrate, the first side wall and the surface of the mask layer; the third side wall material layer and the second side wall material layer are etched to form a second side wall and a third side wall located on the surface of the first side wall; a fourth side wall material layer is formed; the fourth side wall material layer on the PMOS area is etched, and a fourth side wall is formed on the surface of the third side wall on the PMOS area; a first source and drain is formed in the PMOS area at two sides of the gate structure; and the fourth side wall, the fourth side wall material layer located on the NMOS area, the third side wall, the second side wall and the mask layer are removed. The method of the invention can improve the performance of the formed transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to the forming method of a kind of transistor.
Background technology
Along with the development of semiconductor technology, the integrated level of integrated circuit is more and more higher, and the size of transistor reduces the most therewith.Transistor size declines, and the short-channel effect causing transistor is the most notable.
For PMOS transistor, carrier is hole, compared with the carrier electrons of nmos pass transistor, hole mobility in silicon substrate is less than the mobility of electronics, existing usual employing SiGe stress material is as the source-drain electrode material of PMOS transistor, apply compressive stress with the channel region of pair pmos transistor, thus improve the mobility in hole.
In prior art, generally after forming the source-drain electrode of PMOS transistor, then form nmos pass transistor.
Concrete, refer to Fig. 1 to Fig. 5, for the forming process of existing transistor.
Refer to Fig. 1, it is provided that Semiconductor substrate 10, described Semiconductor substrate 10 includes PMOS area and NMOS area, has fleet plough groove isolation structure 11 between described PMOS area and NMOS area；Forming grid structure 20 in PMOS area and NMOS area respectively, described grid structure 20 top has mask layer 21, and described grid structure 20 sidewall surfaces has the first side wall 22；Silicon oxide layer 23 and silicon nitride layer 24 is sequentially formed on described Semiconductor substrate 10 surface, the first side wall 22, mask layer 21 surface.
Refer to Fig. 2, etch the silicon nitride layer 24 in described PMOS area and silicon oxide layer 23, the first side wall 22 surface in PMOS area forms monox lateral wall 23a, is positioned at the silicon nitride spacer 24a on monox lateral wall surface, exposes part semiconductor substrate 10 surface between the neighboring gate structures 20 in PMOS area；Then form SiGe source-drain electrode 41 in the Semiconductor substrate 100 of grid structure 20 both sides in PMOS area, there is in described SiGe source-drain electrode 41 p-type dopant ion, and form silicon cap layer 42 on described SiGe source-drain electrode 41 surface.In said process, silicon nitride layer 24 and silicon oxide layer 23 in NMOS area are not etched, for protecting the Semiconductor substrate 10 of NMOS area.During forming SiGe source-drain electrode 41, the depositing temperature of SiGe is higher, and needs to make annealing treatment, and activates the dopant ion in SiGe source-drain electrode 41.In annealing process, causing the silicon oxide layer 23 in NMOS area easily to form silicon oxynitride layer 25 on the interface of silicon nitride layer 24, mask layer 21 and the first side wall 20, refer to Fig. 5, Fig. 5 is the enlarged diagram that in Fig. 4, dotted line irises out part.This is to be formed in silicon nitride layer 24, mask layer 21 and the first side wall 20 owing to the oxygen atom in silicon oxide layer 23 is diffused into silicon oxide layer 23.
Refer to Fig. 4, the silicon oxide layer 23 (refer to Fig. 2) in etching NMOS area and silicon nitride layer 24 (refer to Fig. 2), form monox lateral wall 23a and silicon nitride spacer 24a.Concrete, after first using the dry etch process described silicon nitride layer 24 of etching to form silicon nitride spacer 24a, use hydrofluoric acid solution to etch the silicon oxide layer 23 exposed, form silicon oxide layer 23a.Existence due to described silicon oxynitride layer 25 (refer to Fig. 3), the etch rate of silicon oxynitride layer 25 etch rate less than silicon oxide layer 23a, after removing the silicon oxide layer being positioned at Semiconductor substrate 10 surface, the silicon oxide layer 23a at mask layer 21 top is not also completely removed, and remains part silicon oxynitride and silicon oxide.
Refer to Fig. 5, use wet-etching technology to remove silicon nitride layer 24a (refer to Fig. 4), silicon oxide layer 23a (refer to Fig. 4) and the mask layer 21 (refer to Fig. 4) in described NMOS area and PMOS area.Phosphoric acid solution is used to carry out above-mentioned wet etching, owing to mask layer 21 top of NMOS area has silicon oxynitride and the silicon oxide of part residual, causing the mask layer 21 in final NMOS area not to be completely removed, easily residual is caused at grid structure 20 top in NMOS area.
The residue at grid structure 20 top of described NMOS area can affect follow-up grid structure 20 top on an nmos area and form metal silicide layer, causes the connection resistance at described grid structure 20 top to improve, the performance of the transistor that impact is formed.
The performance of the transistor that prior art is formed needs further to be improved.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of transistor, improves the performance of the transistor formed.
For solving the problems referred to above, the present invention provides the forming method of a kind of transistor, including: providing Semiconductor substrate, described Semiconductor substrate includes PMOS area and NMOS area；Forming grid structure in described PMOS area and NMOS area, described grid structure top has mask layer；The first side wall is formed on described gate structure sidewall surface；Sequentially form the second spacer material layer on described semiconductor substrate surface, the first side wall and mask layer surface and cover the 3rd spacer material layer of described second spacer material layer；Etching described 3rd spacer material layer and the second spacer material layer, formation is positioned at second side wall on the first side wall surface, is positioned at the 3rd side wall on the second side wall surface；The 4th spacer material layer is formed on described semiconductor substrate surface, the 3rd side wall and mask layer surface；Etching the 4th spacer material layer in described PMOS area, the 3rd side wall surface in PMOS area forms the 4th side wall；The first source-drain electrode is formed in the PMOS area of grid structure both sides；The 4th spacer material layer, the 3rd side wall, the second side wall and the mask layer remove described 4th side wall, being positioned in NMOS area.
Optionally, the method forming the second side wall and the 3rd side wall includes: use dry etch process to etch described 3rd spacer material layer to the second spacer material layer, form the 3rd side wall, expose part the second spacer material layer being positioned at semiconductor substrate surface and mask layer surface；Use the second spacer material layer of the exposure being positioned at semiconductor substrate surface and mask layer surface described in wet-etching technology etching removal, form the second side wall being positioned at the first side wall surface.
Optionally, the material of described mask layer, the first side wall, the 3rd spacer material layer and the 4th spacer material layer is silicon nitride.
Optionally, the material of described second spacer material layer is silicon oxide.
Optionally, the etching solution of the wet-etching technology that the second spacer material layer of the exposure being positioned at semiconductor substrate surface and mask layer surface described in removal is used is hydrofluoric acid solution, and the mass fraction of described hydrofluoric acid solution is 0.01%～1%.
Optionally, using furnace process, chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process to form described second spacer material layer, depositing temperature is 100 DEG C～600 DEG C.
Optionally, the thickness of described second spacer material layer is
Optionally, using furnace process, chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process to form described 3rd spacer material layer, depositing temperature is 100 DEG C～600 DEG C.
Optionally, the thickness of described 3rd spacer material layer is
Optionally, using furnace process, chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process to form described 4th spacer material layer, depositing temperature is 100 DEG C～600 DEG C.
Optionally, the thickness of described 4th spacer material layer is
Optionally, the 4th spacer material layer, the 3rd side wall, the second side wall and mask layer that wet-etching technology is removed described 4th side wall, is positioned in NMOS area are used.
Optionally, phosphoric acid solution is used to remove described 4th side wall, the 4th spacer material layer being positioned in NMOS area, the 3rd side wall and mask layer.
Optionally, the mass fraction of described phosphoric acid solution is 80%～90%, and temperature is 100 DEG C～200 DEG C.
Optionally, hydrofluoric acid solution is used to remove described second side wall.
Optionally, the mass fraction of described hydrofluoric acid solution is 0.01%～1%.
Optionally, the method forming the 4th side wall in described PMOS area includes: the 4th spacer material layer using dry etch process to be pointed in PMOS area performs etching, remove and be positioned at the semiconductor substrate surface of PMOS area and part the 4th spacer material layer on mask layer surface, form the 4th side wall on the 3rd side wall surface being positioned in PMOS area.
Optionally, the forming method of described first source-drain electrode includes: perform etching Semiconductor substrate uncovered between neighboring gate structures in PMOS area, forms groove；The stressor layers with p-type dopant ion is filled, as the first source-drain electrode in described groove.
Optionally, also include: form silicon cap layer on described first source-drain electrode surface.
Optionally, also include: after the 4th spacer material layer, the 3rd side wall, the second side wall and the mask layer that remove described 4th side wall, are positioned in NMOS area, ion implanting is lightly doped in the Semiconductor substrate of the grid structure both sides in NMOS area；Then form the 5th side wall on described first side wall surface, with described grid structure and the first side wall, the 5th side wall as mask, carry out heavy doping ion injection in the Semiconductor substrate of the grid structure both sides in described NMOS area, form the second source-drain electrode.
Compared with prior art, technical scheme has the advantage that
In the inventive solutions, forming grid structure in the PMOS area and NMOS area of Semiconductor substrate, described grid structure top has mask layer；Then form the first side wall on described gate structure sidewall surface, cover semiconductor substrate surface, the first side wall and the second spacer material layer on mask layer surface and cover the 3rd spacer material layer of described second spacer material layer；Then the second spacer material layer in described PMOS area and NMOS area and the 3rd spacer material layer are performed etching simultaneously, form the second side wall and the 3rd side wall.Form the 4th spacer material layer the most again, and etch described 4th spacer material layer, form the 4th side wall on the 3rd side wall surface of PMOS area.Then in the Semiconductor substrate of the grid structure both sides of described PMOS area, the first source-drain electrode is formed.Due to during forming the first source-drain electrode, eliminate the second spacer material layer being positioned at mask layer top surface, compared with prior art, can avoid follow-up during forming the first source-drain electrode, atoms permeating in second spacer material layer enters the 3rd spacer material layer, on mask layer, second spacer material layer and the 3rd side wall layer interface are formed diffusing material layer, thus follow-up removing during mask layer and described mask layer can removed completely, the grid structure in NMOS area is avoided to form residue, such that it is able to improve the performance of the transistor formed.
Further, the method forming described second side wall and the 3rd side wall includes: use dry etch process to etch described 3rd spacer material layer to the second spacer material layer, form the 3rd side wall, expose part the second spacer material layer being positioned at semiconductor substrate surface and mask layer surface；Use the second spacer material layer of the exposure being positioned at semiconductor substrate surface and mask layer surface described in wet-etching technology etching removal, form the second side wall being positioned at the first side wall surface.Described second spacer material layer is as the etching stop layer of etching the 3rd spacer material layer, then wet-etching technology is used to etch described second spacer material layer, compared with etching the second spacer material layer with employing dry etch process, it is possible to reduce the etching injury to Semiconductor substrate.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is the structural representation of the forming process of the transistor of the prior art of the present invention；
Fig. 6 to Figure 13 is the structural representation of the forming process of the transistor of embodiments of the invention.
Detailed description of the invention
As described in the background art, the performance of the transistor that prior art is formed needs further to be improved.
In embodiments of the invention, before the first source-drain electrode formed in PMOS area, etch the 3rd spacer material layer in NMOS area and PMOS area and the second spacer material layer simultaneously, form the second side wall and the 3rd side wall, thus during avoiding being subsequently formed the first source-drain electrode, atoms permeating in second spacer material layer enters the 3rd spacer material layer, on mask layer, second spacer material layer and the 3rd side wall layer interface are formed diffusing material layer, thus follow-up removing during mask layer and mask layer can removed completely, the grid structure in NMOS area is avoided to form residue.Such that it is able to improve the performance of the transistor formed.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with the accompanying drawings the specific embodiment of the present invention is described in detail.
Refer to Fig. 6, it is provided that Semiconductor substrate 100, described Semiconductor substrate 100 includes PMOS area and NMOS area.
Described Semiconductor substrate 100 can be silicon or silicon-on-insulator (SOI), and described Semiconductor substrate 100 can also be germanium, germanium silicon, GaAs or germanium on insulator, and the material of Semiconductor substrate 100 described in this enforcement is body silicon.Follow-up formation nmos pass transistor and PMOS transistor respectively in described NMOS area and PMOS area.
It is also formed with fleet plough groove isolation structure 101 in described Semiconductor substrate 100.Described fleet plough groove isolation structure includes the pad oxide being positioned at flute surfaces and is positioned at described pad oxide surface, fills the sealing coat of full groove.
In the present embodiment, isolated by fleet plough groove isolation structure 101 between described NMOS area and PMOS area.
Refer to Fig. 7, form grid knot 200 in described PMOS area and NMOS area, described grid structure 200 top has mask layer 201.
Described grid structure 200 includes being positioned at the gate dielectric layer on Semiconductor substrate 100 surface and being positioned at the grid (not shown) on gate dielectric layer surface.The material of described gate dielectric layer can be silicon oxide, or high K dielectric material, such as hafnium oxide, zirconium oxide, aluminium oxide or silicon hafnium oxide etc..The material of described grid is polysilicon or metal material.
The forming method of described grid structure 200 includes: sequentially forms gate dielectric material layer on described Semiconductor substrate 100, fleet plough groove isolation structure 101 surface and is positioned at the gate material layers on gate dielectric material layer surface；Mask layer 201, described mask layer 201 covering part gate material layers is formed on described gate material layers surface；With described mask layer 201 as mask, etch described gate material layers and gate dielectric material layer to Semiconductor substrate 100 surface, form grid structure 200.
The material of described mask layer 201 is silicon nitride.
In the present embodiment, form two grid structures 200 as example using each in PMOS area and NMOS area.
Refer to Fig. 8, form the first side wall 202 in described grid structure 200 sidewall surfaces；Sequentially form the second spacer material layer 203 on described Semiconductor substrate 100 surface, the first side wall 202 and mask layer 201 surface and cover the 3rd spacer material layer 204 of described second spacer material layer 203.
In the present embodiment, the material of described first side wall 202 is silicon nitride, and described first side wall 202 covers grid structure 200 sidewall, also the sidewall of mask film covering layer 201.
The method forming described first side wall 202 includes: form the first spacer material layer on Semiconductor substrate 100, grid structure 200 and mask layer 201 surface；Use and etch described first spacer material layer without mask etching technique, remove the first spacer material layer being positioned at Semiconductor substrate 100 surface and mask layer 201 top surface, form the first side wall 202.
Described first side wall 202 is used for protecting the sidewall of grid structure 200, and as the etching stop layer of follow-up the second spacer material layer formed on the first side wall 202 surface.
After forming described first side wall 202, can also be with the grid structure 200 in described PMOS area and the first side wall 202 as mask, the Semiconductor substrate 100 of grid structure 200 both sides in described PMOS area is lightly doped ion implanting, is formed and district is lightly doped.Described first side wall 202 may be used for distance ion implanted regions grid structure 200 between being lightly doped described in restriction.
After forming described first side wall 202, sequentially form described second spacer material layer 203 and cover the 3rd spacer material layer 204 of described second spacer material layer 203.
Furnace process, chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process can be used to form described second spacer material layer 203, and depositing temperature is 100 DEG C～600 DEG C.
In the present embodiment, the material of described second spacer material layer 203 is silicon oxide, uses chemical vapor deposition method to form described second spacer material layer 203, and concrete, the reacting gas that described chemical vapor deposition method uses includes SiH4And O2, wherein, SiH4Flow be 200sccm～2000sccm, O2Flow be 200sccm～2000sccm, depositing temperature is 100 DEG C～600 DEG C.
The thickness of described second spacer material layer 203 isThe thickness of described second spacer material layer 203 may be used for limiting the distance between the first source-drain electrode in the PMOS area being subsequently formed and grid structure 200.
After forming described second spacer material layer 203, furnace process, chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process can be used to form described 3rd spacer material layer 204, depositing temperature is 100 DEG C～600 DEG C.The material of described 3rd spacer material layer 203 and the material of the second spacer material layer 203 are different so that described second spacer material layer 203 can be as the etching stop layer of subsequent etching the 3rd spacer material layer 204.
In the present embodiment, the material of described 3rd spacer material layer 204 is silicon nitride, chemical vapor deposition method can be used to form described 3rd spacer material layer 204, concrete, the reacting gas that described chemical vapor deposition method uses includes SiH4 and NH3, and wherein, the flow of SiH4 is 200sccm～2000sccm, the flow of NH3 is 200sccm～2000sccm, and depositing temperature is 100 DEG C～600 DEG C.
The thickness of described 3rd spacer material layer 204 isThe thickness of described second spacer material layer 203 can be used for limiting the distance between the first source-drain electrode in the PMOS area being subsequently formed and grid structure 200.
Refer to Fig. 9, etching described 3rd spacer material layer 204 (refer to Fig. 8) and the second spacer material layer 203 (refer to Fig. 8), formation is positioned at the second side wall 203a on the first side wall 202 surface, is positioned at the 3rd side wall 204a on the second side wall 203a surface.
The method forming described second side wall 203a and the 3rd side wall 204a includes: use dry etch process to etch described 3rd spacer material layer 204 to the second spacer material layer 203, form the 3rd side wall 203a, expose part the second spacer material layer 203 being positioned at Semiconductor substrate 100 surface and mask layer 201 surface；Use the second spacer material layer 203 of the exposure being positioned at Semiconductor substrate 100 surface and mask layer 201 surface described in wet-etching technology etching removal, form the second side wall 203a being positioned at the first side wall 202 surface.
Described second spacer material layer 203 is as the etching stop layer of etching the 3rd spacer material layer 204, then wet-etching technology is used to etch described second spacer material layer 203, compared with etching the second spacer material layer 203 with employing dry etch process, it is possible to reduce the etching injury to Semiconductor substrate 100.
In the present embodiment, the material of described second spacer material layer 203 is silicon oxide, the etching solution of the wet-etching technology that the second spacer material layer 203 of the exposure being positioned at Semiconductor substrate 100 surface and mask layer 201 surface described in removal is used is hydrofluoric acid solution, and the mass fraction of described hydrofluoric acid solution is 0.01%～1%.Described hydrofluoric acid solution has higher Etch selectivity for the second spacer material layer 203, will not damage Semiconductor substrate 100 and the 3rd side wall 204a.
After forming described second side wall 203a and the 3rd side wall 204a, eliminate the second spacer material layer 203 being positioned at mask layer 201 top surface, compared with prior art, can avoid being formed on the interface between described second spacer material layer 203 and mask layer 201 and the 3rd spacer material layer 204 silicon oxynitride layer, thus affect the follow-up removal to mask layer 201.
Refer to Figure 10, form the 4th spacer material layer 205 on described Semiconductor substrate 100 surface, the 3rd side wall 204a and mask layer 201 surface.
Furnace process, chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process can be used to form described 4th spacer material layer 205, and depositing temperature is 100 DEG C～600 DEG C.
In the present embodiment, the material of described 4th spacer material layer 205 is silicon nitride, and the thickness of described 4th spacer material layer 205 isThe material of described 4th spacer material layer 205 is identical with the material of mask layer the 201, the 3rd side wall 204a.
Refer to Figure 11, etch the 4th spacer material layer 205 in described PMOS area, the 3rd side wall 204a surface in PMOS area forms the 4th side wall 205a.
The method of the 4th side wall 205a being positioned at described in formation in PMOS area includes: the 4th spacer material layer 205 using dry etch process to be pointed in PMOS area performs etching, remove and be positioned at Semiconductor substrate 100 surface of PMOS area and part the 4th spacer material layer 205 on mask layer 201 surface, form the 4th side wall 205a on the 3rd side wall 204a surface being positioned in PMOS area.Before described 4th spacer material layer 205 is performed etching, protective layer can be formed on an nmos area, protect the 4th spacer material layer 205 in described NMOS area.
After forming described 4th spacer material layer 204, grid structure 200 sidewall surfaces in described PMOS area has first side wall the 202, second side wall 203a, the 3rd side wall 204a and the 5th side wall 205a, and described first side wall the 202, second side wall 203a, the gross thickness of the 3rd side wall 204a and the 5th side wall 205a define the distance between the first source-drain electrode and the described grid structure 200 of follow-up grid structure 200 both sides in described PMOS area.
The distance between the first source-drain electrode and described grid structure 200 being subsequently formed can be regulated by the thickness of the one or more side walls in described first side wall the 202, second side wall 203a, the 3rd side wall 204a and the 5th side wall 205a is adjusted.
Mask layer 201 surface at grid structure 200 top of NMOS area directly contacts with described 4th spacer material layer 205, and, described 4th spacer material layer 205 is identical with the material of mask layer 201, other materials layer will not be formed due to reasons such as atoms permeating on both interfaces, thus during the described mask layer of follow-up removal 201, residual will not be caused at grid structure 200 top surface.Further, the 4th spacer material layer 205 NMOS area not being etched as mask material, can protect the Semiconductor substrate 100 of described NMOS area.
Refer to Figure 12, in the PMOS area of grid structure 200 both sides, form the first source-drain electrode 401.
The forming method of described first source-drain electrode 401 includes: perform etching Semiconductor substrate 100 uncovered between neighboring gate structures in PMOS area 200, forms groove；The stressor layers with p-type dopant ion is filled, as the first source-drain electrode 401 in described groove.
In the present embodiment, the material of described stressor layers is SiGe, it is possible to the channel region of the transistor in PMOS area is applied compressive stress, thus improves the hole mobility in described transistor, thus improve the performance of described PMOS transistor.
In the present embodiment, described groove has Σ shape sidewall, can improve the contact area between the channel region below the follow-up stressor layers formed in groove and grid structure 200, improve channel region subjected to stress effect.
Concrete, the method forming described groove includes: concrete, described Semiconductor substrate 100 is etched initially with dry etch process, form opening, then wet-etching technology is used to continue along opening etch semiconductor substrates 100, owing to the etch rate on described each crystal orientation of Semiconductor substrate 100 is different, ultimately form the groove with Σ shape sidewall.The etching gas that described dry etch process uses is Cl2、CCl2F2, HBr or HCl, described wet etching use etching solution be Tetramethylammonium hydroxide (TMAH) solution.In other embodiments of the invention, it is also possible to form the groove that sidewall is U-shaped or V-arrangement.
After forming described groove, use selective epitaxial process, in described groove, fill stressor layers, doping process in situ can be used simultaneously in making described stressor layers, to have p-type dopant ion, and by annealing, make described p-type dopant ion be activated.
In the present embodiment, after forming the first source-drain electrode 401 of the full groove of described filling, being additionally included in described first source-drain electrode 401 surface and form silicon cap layer 402, described silicon cap layer 402 is used for forming metal silicide, reduces the contact resistance on described first source-drain electrode 401 surface.
Refer to Figure 13, the 4th spacer material layer 205 (refer to Figure 12), the 3rd side wall 204a (refer to Figure 12), the second side wall 203a (refer to Figure 12) and the mask layer 201 (refer to Figure 12) remove described 4th side wall 205a (refer to Figure 12), being positioned in NMOS area.
Use the 4th spacer material layer the 205, the 3rd side wall 204a, the second side wall 203a and mask layer 201 that wet-etching technology is removed described 4th side wall 205a, is positioned in NMOS area.
Concrete, in the present embodiment, first, use the 4th spacer material layer the 205, the 3rd side wall 204a and the mask layer 201 that phosphoric acid solution is removed described 4th side wall 205a, is positioned in NMOS area.The mass fraction of described phosphoric acid solution is 80%～90%, and temperature is 100 DEG C～200 DEG C.After removing described mask layer 201, described phosphoric acid solution also can etched portions the second side wall 202.
Then, hydrofluoric acid solution is used to remove described second side wall 203a.The mass fraction of described hydrofluoric acid solution is 0.01%～1%.
Owing to grid structure 200 top in described NMOS area has mask layer 201 and the 4th spacer material layer 205, during carrying out wet etching, described mask layer 201 is identical with the material of the 4th spacer material layer 205, for silicon nitride, can be removed completely by phosphoric acid solution, from without causing residual at grid structure 200 top surface, thus do not interfere with and follow-up form metal silicide layer at grid structure 200 top, and then the performance of the grid structure 200 of formation can be improved.
In an embodiment of the present invention, after the 4th spacer material layer the 205, the 3rd side wall 204a, the second side wall 203a and the mask layer 201 that remove described 4th side wall 205a, are positioned in NMOS area, it is also possible to ion implanting is lightly doped in the Semiconductor substrate 100 of grid structure 200 both sides in NMOS area；Then the 5th side wall is formed on described first side wall 202 surface, with described grid structure 200 and the first side wall the 202, the 5th side wall as mask, heavy doping ion injection is carried out in the Semiconductor substrate 100 of grid structure 200 both sides in described NMOS area, form second source-drain electrode with n-type doping ion, thus form the nmos pass transistor being positioned in NMOS area.
Follow-up can also at described grid structure 200 top, the first source-drain electrode 401 and the second source-drain electrode surface form metal silicide layer, thus reduce described grid structure the 200, first source-drain electrode 401 and the surface contacted resistance of the second source-drain electrode.
In an embodiment of the present invention, forming grid structure in the PMOS area and NMOS area of Semiconductor substrate, described grid structure top has mask layer；Then form the first side wall on described gate structure sidewall surface, cover semiconductor substrate surface, the first side wall and the second spacer material layer on mask layer surface and cover the 3rd spacer material layer of described second spacer material layer；Then the second spacer material layer in described PMOS area and NMOS area and the 3rd spacer material layer are performed etching simultaneously, form the second side wall and the 3rd side wall.Form the 4th spacer material layer the most again, and etch described 4th spacer material layer, form the 4th side wall on the 3rd side wall surface of PMOS area.Then in the Semiconductor substrate of the grid structure both sides of described PMOS area, the first source-drain electrode is formed.Due to during forming the first source-drain electrode, eliminate the second spacer material layer being positioned at mask layer top surface, compared with prior art, can avoid follow-up during forming the first source-drain electrode, atoms permeating in second spacer material layer enters the 3rd spacer material layer, on mask layer, second spacer material layer and the 3rd side wall layer interface are formed diffusing material layer, thus follow-up removing during mask layer and described mask layer can removed completely, the grid structure in NMOS area is avoided to form residue, such that it is able to improve the performance of the transistor formed.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. the forming method of a transistor, it is characterised in that including:
Thering is provided Semiconductor substrate, described Semiconductor substrate includes PMOS area and NMOS area；
Forming grid structure in described PMOS area and NMOS area, described grid structure top has mask layer；
The first side wall is formed on described gate structure sidewall surface；
Sequentially form the second spacer material layer on described semiconductor substrate surface, the first side wall and mask layer surface and cover the 3rd spacer material layer of described second spacer material layer；
Etching described 3rd spacer material layer and the second spacer material layer, formation is positioned at second side wall on the first side wall surface, is positioned at the 3rd side wall on the second side wall surface；
The 4th spacer material layer is formed on described semiconductor substrate surface, the 3rd side wall and mask layer surface；
Etching the 4th spacer material layer in described PMOS area, the 3rd side wall surface in PMOS area forms the 4th side wall；
The first source-drain electrode is formed in the PMOS area of grid structure both sides；
The 4th spacer material layer, the 3rd side wall, the second side wall and the mask layer remove described 4th side wall, being positioned in NMOS area.
The forming method of transistor the most according to claim 1, it is characterized in that, the method forming the second side wall and the 3rd side wall includes: use dry etch process to etch described 3rd spacer material layer to the second spacer material layer, form the 3rd side wall, expose part the second spacer material layer being positioned at semiconductor substrate surface and mask layer surface；Use the second spacer material layer of the exposure being positioned at semiconductor substrate surface and mask layer surface described in wet-etching technology etching removal, form the second side wall being positioned at the first side wall surface.
The forming method of transistor the most according to claim 2, it is characterised in that the material of described mask layer, the first side wall, the 3rd spacer material layer and the 4th spacer material layer is silicon nitride.
The forming method of transistor the most according to claim 2, it is characterised in that the material of described second spacer material layer is silicon oxide.
The forming method of transistor the most according to claim 4, it is characterized in that, the etching solution of the wet-etching technology that the second spacer material layer of the exposure being positioned at semiconductor substrate surface and mask layer surface described in removal is used is hydrofluoric acid solution, and the mass fraction of described hydrofluoric acid solution is 0.01%～1%.
The forming method of transistor the most according to claim 1, it is characterised in that using furnace process, chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process to form described second spacer material layer, depositing temperature is 100 DEG C～600 DEG C.
The forming method of transistor the most according to claim 6, it is characterised in that the thickness of described second spacer material layer is
The forming method of transistor the most according to claim 1, it is characterised in that using furnace process, chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process to form described 3rd spacer material layer, depositing temperature is 100 DEG C～600 DEG C.
The forming method of transistor the most according to claim 8, it is characterised in that the thickness of described 3rd spacer material layer is
The forming method of transistor the most according to claim 1, it is characterised in that using furnace process, chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process to form described 4th spacer material layer, depositing temperature is 100 DEG C～600 DEG C.
The forming method of 11. transistors according to claim 10, it is characterised in that the thickness of described 4th spacer material layer is
The forming method of 12. transistors according to claim 1, it is characterised in that use the 4th spacer material layer, the 3rd side wall, the second side wall and mask layer that wet-etching technology is removed described 4th side wall, is positioned in NMOS area.
The forming method of 13. transistors according to claim 12, it is characterised in that use phosphoric acid solution to remove described 4th side wall, the 4th spacer material layer being positioned in NMOS area, the 3rd side wall and mask layer.
The forming method of 14. transistors according to claim 13, it is characterised in that the mass fraction of described phosphoric acid solution is 80%～90%, temperature is 100 DEG C～200 DEG C.
The forming method of 15. transistors according to claim 12, it is characterised in that use hydrofluoric acid solution to remove described second side wall.
The forming method of 16. transistors according to claim 15, it is characterised in that the mass fraction of described hydrofluoric acid solution is 0.01%～1%.
The forming method of 17. transistors according to claim 1, it is characterized in that, the method forming the 4th side wall in described PMOS area includes: the 4th spacer material layer using dry etch process to be pointed in PMOS area performs etching, remove and be positioned at the semiconductor substrate surface of PMOS area and part the 4th spacer material layer on mask layer surface, form the 4th side wall on the 3rd side wall surface being positioned in PMOS area.
The forming method of 18. transistors according to claim 1, it is characterised in that the forming method of described first source-drain electrode includes: perform etching Semiconductor substrate uncovered between neighboring gate structures in PMOS area, forms groove；The stressor layers with p-type dopant ion is filled, as the first source-drain electrode in described groove.
The forming method of 19. transistors according to claim 18, it is characterised in that also include: form silicon cap layer on described first source-drain electrode surface.
The forming method of 20. transistors according to claim 1, it is characterized in that, also include: after the 4th spacer material layer, the 3rd side wall, the second side wall and the mask layer that remove described 4th side wall, are positioned in NMOS area, ion implanting is lightly doped in the Semiconductor substrate of the grid structure both sides in NMOS area；Then form the 5th side wall on described first side wall surface, with described grid structure and the first side wall, the 5th side wall as mask, carry out heavy doping ion injection in the Semiconductor substrate of the grid structure both sides in described NMOS area, form the second source-drain electrode.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101483190A (en) * | 2008-01-09 | 2009-07-15 | 国际商业机器公司 | MOSFET having a high stress in the channel region and fabricating method thereof |
| US20130260519A1 (en) * | 2009-10-01 | 2013-10-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained structure of semiconductor device |
| CN103456736A (en) * | 2012-06-01 | 2013-12-18 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
| CN103531454A (en) * | 2012-07-03 | 2014-01-22 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN103972173A (en) * | 2013-01-30 | 2014-08-06 | 中芯国际集成电路制造(上海)有限公司 | CMOS (complementary metal oxide semiconductor) transistor forming method |
-
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101483190A (en) * | 2008-01-09 | 2009-07-15 | 国际商业机器公司 | MOSFET having a high stress in the channel region and fabricating method thereof |
| US20130260519A1 (en) * | 2009-10-01 | 2013-10-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained structure of semiconductor device |
| CN103456736A (en) * | 2012-06-01 | 2013-12-18 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of forming the same |
| CN103531454A (en) * | 2012-07-03 | 2014-01-22 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN103972173A (en) * | 2013-01-30 | 2014-08-06 | 中芯国际集成电路制造(上海)有限公司 | CMOS (complementary metal oxide semiconductor) transistor forming method |
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