CN105789400B - A kind of LED chip and its manufacturing method of parallel-connection structure - Google Patents

Abstract

The invention discloses a parallel structure LED chip and a manufacturing method thereof, comprising a substrate, an epitaxial structure located on the substrate, and a P electrode and an N electrode located on the epitaxial structure, and the epitaxial structure sequentially comprises an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer, which is characterized in that a plurality of isolation grooves are formed between the epitaxial structures, and the epitaxial structures are isolated by the isolation grooves to form a plurality of isolation regions, and the isolation grooves include first isolation grooves etched to the substrate and etched to the N-type semiconductor layer. The second isolation groove of the semiconductor layer, the second isolation groove is located in the area surrounded by the first isolation groove, the N electrode is located in the second isolation groove and is electrically connected to the N-type semiconductor layer in each isolation area, and the P electrode It is located in the first isolation groove and electrically connected with the P-type semiconductor layer in each isolation region. The invention can make the current of the LED chip evenly distributed through the parallel structure, reduce the light absorption of the electrodes and pins, increase the light output of the side wall, and improve the luminous brightness of the LED chip.

Description

LED chip with parallel structure and manufacturing method thereof

technical field

The invention relates to the technical field of semiconductor light emitting devices, in particular to an LED chip with a parallel structure and a manufacturing method thereof.

Background technique

A light-emitting diode (Light-Emitting Diode, LED) is a semiconductor electronic component that can emit light. This kind of electronic component appeared as early as 1962. In the early days, it could only emit low-brightness red light. Later, other monochromatic light versions were developed. Today, the light that can be emitted has covered visible light, infrared rays and ultraviolet rays, and the brightness has also increased to a considerable level. brightness. The use has also been used as indicator lights, display panels, etc. from the beginning; with the continuous advancement of technology, light-emitting diodes have been widely used in displays, decoration and lighting.

The structure of LED chips is currently divided into three types: front-mount, flip-chip, and vertical. At present, the front-mount structure is the most used. For LED chips with a front-mounted structure, as the size of the LED chip becomes larger, in order to reduce the voltage and increase the brightness, it is usually achieved by increasing the electrode pins in the prior art, but the increased electrode pins are not conducive to the light output of the chip and reduce the LED’s brightness. Luminous brightness.

Therefore, in view of the above technical problems, it is necessary to provide an LED chip with a parallel structure and a manufacturing method thereof.

Contents of the invention

The object of the present invention is to provide a LED chip with a parallel structure and a manufacturing method thereof, which can effectively improve the luminance of the LED chip.

In order to achieve the above object, the technical solutions provided by the embodiments of the present invention are as follows:

An LED chip with a parallel structure, the LED chip includes a substrate, an epitaxial structure on the substrate, and a P electrode and an N electrode on the epitaxial structure, and the epitaxial structure includes an N-type semiconductor layer, a light-emitting layer, and a P type semiconductor layer, a number of isolation grooves are formed between the epitaxial structures, the epitaxial structures are isolated by the isolation grooves to form a number of isolation regions, and the isolation grooves include the first isolation groove etched to the substrate and the first isolation groove etched to the N-type The second isolation groove of the semiconductor layer, the second isolation groove is located in the area surrounded by the first isolation groove, the N electrode is located in the second isolation groove and is separated from the N-type semiconductor layer in each isolation region Electrically connected, the P electrode is located in the first isolation groove and is electrically connected to the P-type semiconductor layer in each isolation region.

As a further improvement of the present invention, the epitaxial structure further includes a transparent conductive layer on the P-type semiconductor layer, and the shape of the transparent conductive layer is the same as that of the P-type semiconductor layer.

As a further improvement of the present invention, the LED chip further includes a current blocking layer, the current blocking layer is located in the first isolation groove, and all the P electrodes are located on the current blocking layer.

As a further improvement of the present invention, the LED chip further includes a first pad electrically connected to the N electrode and a second pad electrically connected to the P electrode.

As a further improvement of the present invention, the LED chip further includes a protection layer, the protection layer covers at least the isolation region, and the first pad and the second pad are located in a region not covered by the protection layer.

As a further improvement of the present invention, the isolation regions are distributed in a rectangular array, the first isolation groove is located between adjacent row isolation regions and the outer area of the LED chip, and the second isolation groove is located between adjacent column isolation regions.

Correspondingly, a method for manufacturing an LED chip with a parallel structure, the method includes the following steps:

A substrate is provided, and an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer are epitaxially grown on the substrate to form an epitaxial structure;

Etching the epitaxial structure to the surface of the substrate to form a first isolation groove, the first isolation groove isolates the epitaxial structure to form several rows;

Etching the epitaxial structure to the N-type semiconductor layer to form a second isolation groove, the second isolation groove isolates the epitaxial structure to form several columns, and the epitaxial structure is isolated by the first isolation groove and the second isolation groove to form several isolation regions;

forming a current blocking layer in the first isolation groove outside the epitaxial structure;

An N electrode is formed in the second isolation groove, and the N electrode is electrically connected to the N-type semiconductor layer in each isolation region;

A P electrode is formed above the current blocking layer in the first isolation groove, and the P electrode is electrically connected with the P-type semiconductor layer in each isolation region.

As a further improvement of the present invention, in the manufacturing method, before "forming the P-electrode above the current blocking layer in the first isolation trench", it also includes:

A transparent conductive layer is formed on the P-type semiconductor layer in each isolation region.

As a further improvement of the present invention, in the manufacturing method, after "forming the N electrode in the second isolation groove", it also includes: forming a first pad electrically connected to the N electrode on the epitaxial structure; After forming the P electrode above the current blocking layer in the trench, it further includes: a second pad electrically connected to the P electrode formed on the epitaxial structure.

As a further improvement of the present invention, the manufacturing method also includes:

A protection layer covering at least the isolation region is formed on the epitaxial structure, and the first pad and the second pad are located in a region not covered by the protection layer.

The beneficial effects of the present invention are:

The present invention isolates the epitaxial structure into a plurality of isolation regions, and realizes the LED chip of the parallel structure of the plurality of isolation regions. Through the parallel structure, the current of the LED chip can be evenly distributed, the absorption of light by the electrodes and pins is reduced, and the side wall is increased. The light output improves the luminous brightness of the LED chip.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments described in the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is a schematic plan view of a parallel structure LED chip in a specific embodiment of the present invention;

Fig. 2 is a schematic cross-sectional structure diagram at A-A of the parallel structure LED chip in Fig. 1;

3 is a schematic diagram of a single LED chip divided into parallel structure LED chips in a specific embodiment of the present invention;

4a-4f are process steps diagrams of a method for manufacturing LED chips with a parallel structure in a specific embodiment of the present invention.

Detailed ways

In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described The embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

The invention discloses an LED chip with a parallel structure. The LED chip includes a substrate, an epitaxial structure located on the substrate, and a P electrode and an N electrode located on the epitaxial structure. The epitaxial structure sequentially includes an N-type semiconductor layer, a light-emitting layer and In the P-type semiconductor layer, several isolation grooves are formed between the epitaxial structures, and the epitaxial structures are isolated by the isolation grooves to form several isolation regions. The isolation grooves include a first isolation groove etched to the substrate and a second isolation groove etched to the N-type semiconductor layer. The isolation groove, the second isolation groove is located in the area surrounded by the first isolation groove, the N electrode is located in the second isolation groove and is electrically connected to the N-type semiconductor layer in each isolation area, and the P electrode is located in the first isolation groove. The isolation trench is electrically connected to the P-type semiconductor layer in each isolation region.

Referring to Fig. 1 and Fig. 2, in a specific embodiment of the present invention, the LED chip 100 in parallel structure comprises in turn:

Substrate 10, the substrate can be sapphire, Si, SiC, GaN, ZnO, etc.;

N-type semiconductor layer 20, the N-type semiconductor layer can be N-type GaN, etc.;

A light-emitting layer 30, the light-emitting layer can be GaN, InGaN, etc.;

P-type semiconductor layer 40, the P-type semiconductor layer can be P-type GaN, etc.;

The N electrode 50 and the P electrode 60 , the N electrode 50 is disposed on the N-type semiconductor layer 20 and electrically connected to the N-type semiconductor layer 20 , and the P electrode 60 is electrically connected to the P-type semiconductor layer 40 .

In this embodiment, the epitaxial structure includes an N-type semiconductor layer 20, a light-emitting layer 30, and a P-type semiconductor layer 40. Several isolation grooves are formed between the epitaxial structures, and the isolation grooves isolate the epitaxial structures to form several isolation regions. Preferably, this embodiment 6 isolation areas 101 , 102 , 103 , 104 , 105 and 106 in three rows and two columns are taken as an example for illustration.

Wherein, the isolation trench includes a first isolation trench 91 etched to the substrate 10 and a second isolation trench 92 etched to the N-type semiconductor layer 20, as in this embodiment, the first isolation trench 91 is formed outside the epitaxial structure Between the three borders and the isolation regions of adjacent rows, the second isolation groove 92 is formed between the isolation regions of adjacent columns, and the second isolation groove 92 is located in the area surrounded by the first isolation groove 91. The trench 91 and the second isolation trench 92 separate the epitaxial structure into six isolation regions 101 , 102 , 103 , 104 , 105 and 106 .

Preferably, in this embodiment, the upper four isolation regions 101, 102, 103, and 104 are completely isolated, only the lower N-type semiconductor layer is not isolated in the second isolation trench 92, and the lower two isolation regions 105 and 106 are Partial isolation. In other implementation manners, other complete isolation or partial isolation methods may also be used, which will not be described in detail here.

Furthermore, in this embodiment, the P-type semiconductor layer 40 is further provided with a transparent conductive layer 70 , the shape of the transparent conductive layer is exactly the same as that of the P-type semiconductor layer 40 , and it is also separated by isolation grooves and located in each isolation region. The transparent conductive layer 70 in this embodiment is an ITO transparent conductive layer, and in other embodiments, it can also be a transparent conductive layer such as ZITO, ZIO, GIO, ZTO, FTO, AZO, GZO, In ₄ Sn ₃ O ₁₂ , NiAu, etc., further Specifically, the transparent conductive layer may be one layer, or may be a combined layer structure of two or more of the above-mentioned transparent conductive layers.

A current blocking layer 80 is formed in the first isolation grooves 91 at the three outer borders of the epitaxial structure, the current blocking layer 80 is formed of an insulating material such as SiO ₂ , the P electrode 60 is formed above the current blocking layer 80, and the P electrode 60 are respectively electrically connected to the transparent conductive layer 70 in each isolation region, and furthermore, the P electrode 60 is also indirectly electrically connected to the P-type semiconductor layer 40 . Through the setting of the current blocking layer 80, the current under the P electrode 60 can be blocked, and the light extraction efficiency can be improved.

Simultaneously, an N-electrode 50 is formed on the N-type semiconductor layer 20 in the second isolation trench 92. Since the N-type semiconductor layer 20 in the second isolation trench 92 is not etched, the N-electrode 50 can be connected to each The N-type semiconductor layer 20 in the isolation region is electrically connected.

Through the design of the above structure, the N-type semiconductor layer 20 in each isolation region is electrically connected to the N electrode 50, and the P-type semiconductor layer 40 in each isolation region is electrically connected to the P electrode 60. Therefore, all isolation The epitaxial structure in the region is a parallel structure between the P electrode and the N electrode.

Further, by setting the first pad 51 electrically connected to the N electrode 50 and the second pad 61 electrically connected to the P electrode 60 above the epitaxial structure, through the first pad 51 and the second pad 61 That is, the N electrode 50 and the P electrode 60 can be drawn out, and the first pad 51 and the second pad 61 can be used as the lead-out electrodes of the entire parallel LED chip.

Correspondingly, the present invention also discloses a method for manufacturing LED chips with a parallel structure, including the following steps:

A substrate is provided, and an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer are epitaxially grown on the substrate to form an epitaxial structure;

Etching the epitaxial structure to the surface of the substrate to form a first isolation groove, the first isolation groove isolates the epitaxial structure to form several rows;

Etching the epitaxial structure to the N-type semiconductor layer to form a second isolation groove, the second isolation groove isolates the epitaxial structure to form several columns, and the epitaxial structure is isolated by the first isolation groove and the second isolation groove to form several isolation regions;

forming a current blocking layer in the first isolation groove outside the epitaxial structure;

An N electrode is formed in the second isolation groove, and the N electrode is electrically connected to the N-type semiconductor layer in each isolation region;

A P electrode is formed above the current blocking layer in the first isolation groove, and the P electrode is electrically connected with the P-type semiconductor layer in each isolation region.

The method for manufacturing LED chips with a parallel structure in the present invention will be further described below in combination with specific embodiments.

In the present invention, by isolating the epitaxial structure, a single LED chip can be changed into a plurality of LED chips with epitaxial structures in parallel structure. As shown in FIG. 3, a single LED chip can be changed into n rows, m LED chips with a column-parallel structure are distributed on the substrate in a (n, m) rectangular array. In order to simplify the manufacturing method of the LED chip, n=3 and m=2 are taken in this embodiment, with 3 rows and 2 columns, a total of 6 An LED chip with a parallel structure is used as an example to illustrate.

First, a GaN epitaxial layer is epitaxially grown on a sapphire substrate by MOCVD to form an epitaxial structure including an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer;

Use a plasma etching machine to perform an ICP etching process on the GaN epitaxial layer, deeply etch the shaded part in FIG. Form several lines. The first isolation groove 91 in this embodiment covers the sides surrounding the three sides of the epitaxial structure and several parts parallel to each other and extending from the corresponding two sides to the middle. disk position;

Then use a plasma etching machine to etch the N-electrode contact area of the GaN epitaxial layer, that is, etch the shaded part in FIG. The isolation forms several columns, and the second isolation groove 92 is the N electrode contact area. In this embodiment, the second isolation trench 92 is vertically intersected with part of the first isolation trench 91 , and the epitaxial structure is isolated by the first isolation trench 91 and the second isolation trench 92 to form several isolation regions. At the same time, a first pad position is reserved on the epitaxial structure, and the position is etched synchronously with the second isolation groove 92;

Then part of the first isolation groove 91 is filled with materials such as silicon dioxide or silicon nitride to form a current blocking layer 80, as shown in FIG. 4c, the current blocking layer 80 covers the shaded part in FIG. 4c, and the current blocking layer is at least At the three sides of the epitaxial structure, at least one of the current blocking layers extends to the isolation region for supporting the corresponding P electrodes;

Preferably, in this embodiment, a transparent conductive layer 70, such as an ITO transparent conductive layer, is also formed on the light-emitting region of the epitaxial structure. Referring to FIG. 4d, the epitaxial structure is divided into 6 outer isolation areas 101, 102, 103, 104, 105 and 106 distributed in a matrix array;

Carry out the making of metal electrode at last, vapor-deposit metal electrode respectively in the shaded position in Fig. The pads 61 are used to lead out the corresponding electrodes.

Specifically, the N electrode 50 needs to be formed in the second isolation groove 92, and the N electrode 50 is electrically connected to the N-type semiconductor layer in each isolation region; The electrode 60, the P electrode 60 is electrically connected to the P-type semiconductor layer in each isolation area, so that an LED chip with a parallel structure of 6 isolation areas can be obtained, and the P-type semiconductor layer and the N-type semiconductor layer in each isolation area are electrically connected to the P electrode and the N electrode respectively. Finally, the first bonding pad and the second bonding pad are respectively formed in corresponding regions. Certainly, in other implementation manners, the N electrode, the P electrode, and the first pad and the second pad can also be prepared simultaneously in one evaporation process, which will not be described in detail here.

Preferably, as shown in FIG. 4f, after preparing the N electrode 50, the P electrode 60, the first pad 51 and the second pad 61, a protective layer 110 can also be prepared on the surface of the LED chip, using silicon dioxide or The LED chip is protected by a transparent insulating material such as silicon nitride or aluminum oxide, and the protective layer 110 covers the entire surface except the first pad 51 and the second pad 61 .

It should be understood that, in the above embodiment, a (3, 2) rectangular array of 6 isolation regions in 3 rows and 2 columns is taken as an example to describe LED chips in parallel structure in detail. In other embodiments, the isolation regions can also be other The rectangular array distribution of the structure, such as a (3, 2) rectangular array of 3 rows and 2 columns with a total of 6 isolation areas, etc. Of course, it can also be an array distribution of other shapes, such as a total of 9 isolation areas with 3 rows and 3 columns (3 , 3) square arrays, or other circular or elliptical arrays, etc., which will not be illustrated here one by one.

No matter what kind of array is used, it is necessary to use the first isolation groove and the second isolation groove for isolation. At the same time, the P electrode and the N electrode are respectively electrically connected to the P-type semiconductor layer and the N-type semiconductor layer in each isolation region. To realize the parallel structure of each isolation area.

Preferably, the first bonding pad and the second bonding pad are arranged in the middle of the LED chip, so as to realize uniform light emission of the LED chip.

It can be seen from the above technical solutions that, compared with the prior art, the present invention realizes an LED chip with a parallel structure of multiple isolation areas by isolating the epitaxial structure into multiple isolation areas, and the current of the LED chip can be evenly distributed through the parallel structure , reducing the light absorption of the electrodes and pins, increasing the light output of the side wall, and improving the luminous brightness of the LED chip.

It will be apparent to those skilled in the art that the invention is not limited to the details of the above-described exemplary embodiments, but that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Accordingly, the embodiments should be regarded in all points of view as exemplary and not restrictive, the scope of the invention being defined by the appended claims rather than the foregoing description, and it is therefore intended that the scope of the invention be defined by the appended claims rather than by the foregoing description. All changes within the meaning and range of equivalents of the elements are embraced in the present invention. Any reference sign in a claim should not be construed as limiting the claim concerned.

In addition, it should be understood that although this specification is described according to implementation modes, not each implementation mode only includes an independent technical solution, and this description in the specification is only for clarity, and those skilled in the art should take the specification as a whole , the technical solutions in the various embodiments can also be properly combined to form other implementations that can be understood by those skilled in the art.

Claims (10)

1. a kind of LED chip of parallel-connection structure, the LED chip includes substrate, the epitaxial structure on substrate and is located at outer Prolonging the P electrode and N electrode in structure, the epitaxial structure includes n type semiconductor layer, luminescent layer and p type semiconductor layer successively, Be characterized in that, be formed with several isolation channels between the epitaxial structure, epitaxial structure be isolated by the isolation channel formed it is several every From area, the isolation channel includes the first isolation channel for being etched to substrate and the second isolation channel for being etched to n type semiconductor layer, described Second isolation channel is located at the first isolation channel and encloses in the region set, the N electrode be located in second isolation channel and with it is each every Be electrically connected from the n type semiconductor layer in area, the P electrode be located in the first isolation channel and with the P in each isolated area Type semiconductor layer is electrically connected.

2. the LED chip of parallel-connection structure according to claim 1, which is characterized in that the epitaxial structure further includes being located at P Transparency conducting layer in type semiconductor layer, the shape of the transparency conducting layer are identical as the shape of p type semiconductor layer.

3. the LED chip of parallel-connection structure according to claim 1 or 2, which is characterized in that further include in the LED chip Current barrier layer, the current barrier layer is located in the first isolation channel, and the P electrode is entirely located in the current barrier layer On.

4. the LED chip of parallel-connection structure according to claim 1 or 2, which is characterized in that the LED chip further include with The first pad that the N electrode is electrically connected and the second pad being electrically connected with the P electrode.

5. the LED chip of parallel-connection structure according to claim 4, which is characterized in that the LED chip further includes protection Layer, the protective layer at least cover the isolated area, and first pad and the second pad are located at the unlapped region of protective layer.

6. the LED chip of parallel-connection structure according to claim 1 or 2, which is characterized in that the isolated area rectangular array Distribution, the first isolation channel is between adjacent rows isolated area and LED chip lateral area, the second isolation channel are located at adjacent column isolation Between area.

7. a kind of manufacturing method of the LED chip of parallel-connection structure, which is characterized in that the manufacturing method includes the following steps：

One substrate is provided, n type semiconductor layer, luminescent layer and p type semiconductor layer are epitaxially grown on the substrate, forms epitaxial structure；

Epitaxial structure is etched to substrate surface, forms the first isolation channel, epitaxial structure is isolated to form several rows for the first isolation channel；

Epitaxial structure is etched to n type semiconductor layer, forms the second isolation channel, the second isolation channel epitaxial structure is isolated to be formed it is several Row, epitaxial structure is isolated by the first isolation channel and the second isolation channel forms several isolated areas；

Current barrier layer is formed in the first isolation channel on the outside of epitaxial structure；

N electrode is formed in the second isolation channel, N electrode is electrically connected with the n type semiconductor layer in each isolated area；

The top of current barrier layer forms P electrode, P electrode and p type semiconductor layer electricity in each isolated area in the first isolation channel Property connection.

8. manufacturing method according to claim 7, which is characterized in that " electric in the first isolation channel in the manufacturing method The top of flow barrier forms P electrode " further include before：

Transparency conducting layer is formed on p type semiconductor layer in each isolated area.

9. manufacturing method according to claim 7, which is characterized in that in the manufacturing method, " in the second isolation channel shape At N electrode " further include later：The first pad of N electrode electric connection is formed on epitaxial structure；" in the first isolation channel The top of current barrier layer forms P electrode " further include later：The second weldering of P electrode electric connection is formed on epitaxial structure Disk.

10. manufacturing method according to claim 9, which is characterized in that the manufacturing method further includes：

The protective layer at least covering the isolated area is formed on the epitaxial structure, first pad and the second pad are located at The unlapped region of protective layer.