CN105789136A - Semiconductor storage device, fabrication method thereof and electronic device - Google Patents
Semiconductor storage device, fabrication method thereof and electronic device Download PDFInfo
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Abstract
The invention relates to a semiconductor storage device, a fabrication method thereof and an electronic device. The method comprises the following steps of S1, providing a semiconductor substrate, wherein a floating grid material layer, an isolation layer, a control grid material layer and a hard mask layer are formed on the semiconductor substrate, and the hard mask layer has different wet etching rates in a vertical direction; S2, patterning the hard mask layer to form an opening, and exposing the control grid material layer; S3, wet-etching the hard mask layer to expand the opening so as to form an inverted conical opening with a wide upper part and a narrow lower part; and S4, etching the control grid material layer, the isolation layer and the floating gird material by taking the hard mask layer as a mask to form a conical floating grid and a control grid which are wide in upper parts and narrow in lower parts. With the method disclosed by the invention, the conical floating grid and the control grid can be formed in a device with a small size, and a gap between the conical floating grid and the control grid is easy to be filled.
Description
Technical field
The present invention relates to semiconductor storage unit, in particular it relates to a kind of semiconductor storage unit and preparation method thereof, electronic installation.
Background technology
Along with the high speed development (such as mobile phone, digital camera, MP3 player and PDA etc.) of portable electric appts, the requirement for data storage is more and more higher.Nonvolatile flash memory remains to preserve the feature of data owing to having under powering-off state, become topmost memory unit in these equipment, wherein, owing to flash memory (flashmemory) can reach significantly high chip-stored density, and do not introduce new material, manufacturing process is compatible, therefore, it can be easier to more reliable being integrated into and has in digital and analog circuit.
NOR and NAND is nonvolatile flash memory technology two kinds main currently on the market, NOR flash memory (Flash) device belongs to the one of nonvolatile flash memory, it is characterized in chip to perform, such application program can directly run in Flash flash memory, again code need not be read in system RAM (random access memory), thus making it have higher efficiency of transmission.
Wherein, the polysilicon gate with high-aspect-ratio is widely used in NOR and NAND, along with constantly reducing of grid size, between grid, the filling in space becomes stubborn problem, this problem can be solved by forming up-narrow and down-wide taper grid, prepare at present the method for taper polysilicon gate mostly concentrate on following some: first reduces to tilt (bias) and increase lateral etches and longitudinal etch-rate ratio by increasing pressure；Second protects the sidewall of grid by introducing polymer.
Although said method has good effect in larger-size device, but it is as constantly reducing of device size, use described method to prepare semiconductor device and produce a lot of difficulty, space filling effect is deteriorated, directly affects the performance of device and yield, it is thus desirable to current described method is improved further, in order to eliminate the problems referred to above.
Summary of the invention
Introducing the concept of a series of reduced form in Summary, this will further describe in detailed description of the invention part.The Summary of the present invention is not meant to the key feature and the essential features that attempt to limit technical scheme required for protection, does not more mean that the protection domain attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, it is provided that the preparation method of a kind of semiconductor storage unit, including:
Step S1: providing Semiconductor substrate, be formed with floating gate material layer, sealing coat, control gate material layer and hard mask layer on the semiconductor substrate, wherein, described hard mask layer in the vertical direction has different wet etch rate；
Step S2: pattern described hard mask layer, to form opening, exposes described control gate material layer；
Step S3: hard mask layer described in wet etching, to expand described opening, forms inverted cone opening wide at the top and narrow at the bottom；
Step S4: with described hard mask layer for control gate material layer, described sealing coat and described floating gate material layer described in mask etch, to form up-narrow and down-wide taper floating boom and control gate.
Alternatively, in described step S1, described hard mask layer selects SiO2。
Alternatively, in described step S1, the forming method of described hard mask layer selects CVD or high depth to compare depositing operation.
Alternatively, in described step S1, the forming method of described hard mask layer includes:
Step S11: deposit sub-hard mask layer and select oxygen plasma that this sub-hard mask layer is processed.
Step S12: perform step S11 several times, to form described hard mask layer.
Alternatively, in described step S11, the thickness range of described sub-hard mask layer is
Alternatively, in described step S11, described sub-hard mask layer adopts aumospheric pressure cvd technique to be formed, and wherein reacting gas is tetraethyl orthosilicate, SiH4In one or both, and O2Or O3In one or both, reaction temperature is 700 DEG C～1000 DEG C.
Alternatively, described oxygen plasma processes the gas adopted is O2Or O3；Wherein, O2Or O3Range of flow be 50sccm～500sccm.
Alternatively, the time that described oxygen plasma processes is 5s～60s, and radio-frequency power is 30W～1000W.
Alternatively, the number of times performing step S11 in described step S12 is 5-30.
Alternatively, described step S1 performs several times step S11.
Alternatively, the thickness of described hard mask layer is 500A-3000A.
Alternatively, in described step S2, described patterning method includes:
Step S21: form the photoresist of patterning or the mask layer of bilayer, multilamellar on described hard mask layer；
Step S22: with described mask layer for hard mask layer described in mask etch, to form described opening.
Alternatively, in described step S3, described wet etching selects the etching solution including HF.
Alternatively, in described step S3, the angle between sidewall and the described control gate material layer of described inverted cone opening is 80-88 °.
Alternatively, in described step S4, adjust described floating boom and the Sidewall angles of described control gate by controlling the etching selectivity between described hard mask layer and described floating gate material layer and described control gate material layer.
Alternatively, in described step S1, described floating gate material layer selects polysilicon；
Described control gate material layer selects polysilicon.
Present invention also offers a kind of based on being the semiconductor storage unit for preparing of the method stated.
Present invention also offers a kind of electronic installation, including above-mentioned semiconductor storage unit.
The present invention is to solve problems of the prior art, the preparation method providing a kind of semiconductor storage unit, on control gate material layer, form in the vertical direction in the process there is the hard mask layer of wet etch rate gradient, described hard mask layer is formed opening and expands described opening by wet etching, form inverted cone opening wide at the top and narrow at the bottom, then with described hard mask layer for floating gate material layer described in mask etch and control gate material layer, forming taper floating boom and control gate, the space between described taper floating boom and control gate is more prone to fill.
Accompanying drawing explanation
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, it is used for explaining assembly of the invention and principle.In the accompanying drawings,
Fig. 1 a-1d is the preparation process schematic diagram of semiconductor storage unit described in an embodiment of the present invention；
Fig. 2 is the preparation technology flow chart of semiconductor storage unit described in an embodiment of the present invention.
Detailed description of the invention
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.It is, however, obvious to a person skilled in the art that the present invention can be carried out without these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
It should be appreciated that the present invention can implement in different forms, and should not be construed as being limited to embodiments presented herein.On the contrary, provide these embodiments will make openly thoroughly with complete, and will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size are likely to be exaggerated.Same reference numerals represents identical element from start to finish.
It is understood that, when element or layer be referred to as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or during layer, its can directly on other element or layer, adjacent thereto, be connected or coupled to other element or layer, or can there is element between two parties or layer.On the contrary, when element be referred to as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or during layer, then be absent from element between two parties or layer.Although it should be understood that and term first, second, third, etc. can being used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not be limited by these terms.These terms are used merely to distinguish an element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, without departing under present invention teach that, the first element discussed below, parts, district, floor or part are represented by the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " following ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of shown in description figure a element or feature and other element or feature for convenient description.It should be understood that except the orientation shown in figure, spatial relationship term is intended to also include the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be included.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
As used herein term only for purpose of describing specific embodiment and the restriction not as the present invention.When using at this, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that term " composition " and/or " including ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but be not excluded for one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When using at this, term "and/or" includes any of relevant Listed Items and all combinations.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, in order to explaination technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but except these detailed descriptions, the present invention can also have other embodiments.
Embodiment 1
Below in conjunction with accompanying drawing 1a-1d, a specific embodiment of the present invention is illustrated.
First, perform step 101, it is provided that Semiconductor substrate 101, described Semiconductor substrate 101 is formed floating gate material layer 102, sealing coat 103 and control gate material layer 104.
First, with reference to Fig. 1 a, wherein said Semiconductor substrate 101 can be at least one in the following material being previously mentioned: stacking SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacking silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
Additionally, Semiconductor substrate 101 can be defined active area.Other active device can also be included on the active region, in order to convenient, do not indicate in shown figure.
Alternatively, it is also possible to forming gate dielectric in described Semiconductor substrate 101, wherein, described gate dielectric can select dielectric material commonly used in the art, for instance can select oxide.
When selecting oxide as described gate dielectric, the forming method of described gate dielectric can be high-temperature oxydation or deposition process, it is not limited to a certain method, it is possible to select as required.
Then on described gate dielectric, sequentially form floating gate material layer, sealing coat and control gate material layer.
Wherein, described floating gate material layer 102 selects semi-conducting material, such as silicon, polysilicon or Ge etc., being not limited to a certain material, the deposition process of described floating gate material layer 102 can select the one in molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG).
In this embodiment, forming the floating gate material layer of polysilicon, described polysilicon selects epitaxy method to be formed, and specifically, is described further for silicon in a particular embodiment, and reacting gas can include hydrogen (H2) Silicon chloride. (SiCl that carries4) or trichlorosilane (SiHCl3), silane (SiH4) and dichloro hydrogen silicon (SiH2Cl2) etc. at least one entrance be placed with the reative cell of silicon substrate, carry out high-temperature chemical reaction at reative cell, make the reduction of siliceous reacting gas or thermal decomposition, produced silicon atom is at gate dielectric surface Epitaxial growth.
Further, described floating gate material layer is formed spacer material layer, described spacer material layer can select insulant commonly used in the art, for instance ONO (the structural insulation sealing coat of oxidenitride oxide), but be not limited to that described material.
Then being formed over control gate material layer at described spacer material layer, wherein said control gate material layer can select the material identical with described floating gate material layer, it is also possible to selects different materials, for instance can form metal gates as control gate.
Perform step 102, described control gate material layer 104 is formed hard mask layer 105.
Specifically, as shown in Figure 1a, described hard mask layer has the wet etch rate (vertically-distributedwetetchrate) of distribution on vertical direction, its in the vertical direction has different wet etch rate, in order to form the reverse taper profile of sidewall slope in subsequent steps.
Wherein, described hard mask layer 105 selects SiO2。
Alternatively, the forming method of described hard mask layer selects CVD or high depth than depositing operation (HARP).Specifically, exemplarily, in order to make described hard mask layer in the vertical direction have wet etching gradient, first preparation process deposits one layer of hard mask layer, then selects O2This layer is processed, passes through O2Adjust described hard mask layer (SiO2) wet etch rate, and in the forming process of hard mask layer circulation execution deposition and O2The step carrying out processing, to required thickness, performs to change O in the process of this step in circulation2The parameter processed, to change the wet etch rate of this layer of hard mask layer, thus in the vertical direction forms wet etch rate gradient.
Alternatively, in wherein said hard mask layer, the wet etch rate at top is more than the wet etch rate of bottom, forms opening wide at the top and narrow at the bottom in subsequent steps.
Further, the thickness of described hard mask layer is 500A-3000A, but be not limited to that described thickness.
As a specifically embodiment, the forming method of wherein said hard mask layer includes: be initially formed sub-hard mask layer, and the thickness range of described sub-hard mask layer is
The material of sub-hard mask layer is silicon oxide, adopts aumospheric pressure cvd technique to form described sub-hard mask layer, and wherein reacting gas is one or both in tetraethyl orthosilicate, SiH4, and O2Or O3In one or both, reaction temperature is 700 DEG C～1000 DEG C.
Then described sub-hard mask layer being carried out Cement Composite Treated by Plasma, Cement Composite Treated by Plasma is that oxygen plasma processes, and the gas of employing is O2Or O3, wherein, O2Or O3Range of flow be 50sccm～500sccm, the time of Cement Composite Treated by Plasma is 5s～60s, and radio-frequency power is 30W～1000W.
In this step, keeping the time that oxygen plasma processes constant, with optional between sub-hard mask layer and Semiconductor substrate, the number of times circulating above-mentioned processing step is 5～30, to ultimately form described hard mask layer.
Perform step 103, pattern described hard mask layer 105, expose described control gate material layer 104 forming opening.
Specifically, as shown in Figure 1 b, described patterning method can the photoetching-engraving method of selection standard in this step, on described hard mask layer, such as form photoresist layer, then photoetching development, to form opening in described photoresist layer, then with described photoresist layer for hard mask layer described in mask etch.
In addition, mask layer double-deck, multilamellar can also be formed on described hard mask layer, on described hard mask layer, such as form photoresist layer, organic distribution layer (Organicdistributionlayer, ODL) two kinds or more of and in siliceous bottom antireflective coating (Si-BARC), then opening is formed, then with described mask layer for hard mask layer described in mask etch.
Alternatively, in this step, dry etching is selected, reactive ion etching (RIE), ion beam milling, plasma etching.
Perform step 104, hard mask layer 105 described in wet etching, to expand described opening, form inverted cone opening wide at the top and narrow at the bottom.
Specifically, as illustrated in figure 1 c, selecting wet etching in this step, this step has higher wet etch rate, to expand described opening, forms inverted cone opening.
In this step, described wet etching selects the etching solution including HF, for instance selecting DHF, described hard mask layer has different wet etch rate for DHF in the vertical direction, to ensure to form inverted cone opening wide at the top and narrow at the bottom.
Alternatively, this step (wherein comprises HF, H with the Fluohydric acid. DHF of dilution2O2And H2O) etching described hard mask layer, the concentration of described DHF does not strictly limit, in the present invention preferred HF:H2O2:H2O=0.1-1.5:1:5.
In this step, the angle between sidewall and the described control gate material layer of described inverted cone opening is 80-88 °, as illustrated in figure 1 c.
Perform step 105, with described hard mask layer for floating gate material layer 102, described sealing coat 103 and described control gate material layer 104 described in mask etch, to form up-narrow and down-wide taper floating boom and control gate.
Specifically, as shown in Figure 1 d, described floating boom and the Sidewall angles of described control gate are adjusted by controlling the etching selectivity between described hard mask layer and described floating gate material layer and described control gate material layer in this step.
Alternatively, select and described hard mask layer has the method described floating gate material layer of etching of bigger etching selectivity and described control gate material layer, in one embodiment, it is possible to select N2In conduct etching atmosphere, it is also possible to be simultaneously introduced other a small amount of gas such as CF4、CO2、O2, described etching pressure can be 2-200mTorr, is chosen as 2-30mTorr, and power is 500-900W, and described etching period is 5-80s in the present invention, is chosen as 10-60s, selects bigger gas flow in the present invention, at N of the present invention simultaneously2Flow be 30-300sccm, be chosen as 50-100sccm.
While obtaining up-narrow and down-wide floating boom and control gate, between control gate, it is formed with inverted cone opening wide at the top and narrow at the bottom, in described opening, is obtained in that better filling effect during packing material, so that the device prepared has better performance and yield.
So far, the introduction of the preparation process of the semiconductor storage unit of the embodiment of the present invention is completed.After the above step, it is also possible to include other correlation step, repeat no more herein.Further, in addition to the foregoing steps, the preparation method of the present embodiment can also include other steps among each step above-mentioned or between different steps, and these steps all can be realized by various techniques of the prior art, repeats no more herein.
The present invention is to solve problems of the prior art, the preparation method providing a kind of semiconductor storage unit, on control gate material layer, form in the vertical direction in the process there is the hard mask layer of wet etch rate gradient, described hard mask layer is formed opening and expands described opening by wet etching, form inverted cone opening wide at the top and narrow at the bottom, then with described hard mask layer for floating gate material layer described in mask etch and control gate material layer, forming taper floating boom and control gate, the space between described taper floating boom and control gate is more prone to fill.
Wherein, Fig. 2 is the process chart of semiconductor storage unit in the embodiment of the invention, specifically comprises the following steps:
Step S1: providing Semiconductor substrate, be formed with floating gate material layer, sealing coat, control gate material layer and hard mask layer on the semiconductor substrate, wherein, described hard mask layer in the vertical direction has different wet etch rate；
Step S2: pattern described hard mask layer, to form opening, exposes described control gate material layer；
Step S3: hard mask layer described in wet etching, to expand described opening, forms inverted cone opening wide at the top and narrow at the bottom；
Step S4: with described hard mask layer for control gate material layer, described sealing coat and described floating gate material layer described in mask etch, to form up-narrow and down-wide taper floating boom and control gate.
Embodiment 2
Present invention also offers a kind of semiconductor storage unit, described semiconductor storage unit selects the method described in embodiment 1 to prepare.The control gate of the semiconductor storage unit prepared by described method is pyramidal structure, inverted cone opening wide at the top and narrow at the bottom it is formed with between control gate, it is obtained in that better filling effect during packing material, so that the device prepared has better performance and yield in described opening.
Embodiment 3
Present invention also offers a kind of electronic installation, including the semiconductor storage unit described in embodiment 2.Wherein, semiconductor storage unit is the semiconductor storage unit described in embodiment 2, or the semiconductor storage unit that the preparation method according to embodiment 1 obtains.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, photographing unit, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment, it is possible to for any intermediate products including described semiconductor device.The electronic installation of the embodiment of the present invention, owing to employing above-mentioned semiconductor device, thus has better performance.
The present invention is illustrated already by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that and the invention is not limited in above-described embodiment, more kinds of variants and modifications can also be made according to the teachings of the present invention, within these variants and modifications all fall within present invention scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (17)
1. a preparation method for semiconductor storage unit, including:
Step S1: providing Semiconductor substrate, be formed with floating gate material layer, sealing coat, control gate material layer and hard mask layer on the semiconductor substrate, wherein, described hard mask layer in the vertical direction has different wet etch rate；
Step S2: pattern described hard mask layer, to form opening, exposes described control gate material layer；
Step S3: hard mask layer described in wet etching, to expand described opening, forms inverted cone opening wide at the top and narrow at the bottom；
Step S4: with described hard mask layer for control gate material layer, described sealing coat and described floating gate material layer described in mask etch, to form up-narrow and down-wide taper floating boom and control gate.
2. method according to claim 1, it is characterised in that in described step S1, described hard mask layer selects SiO2。
3. method according to claim 1 and 2, it is characterised in that in described step S1, the forming method of described hard mask layer selects CVD or high depth to compare depositing operation.
4. method according to claim 1 and 2, it is characterised in that in described step S1, the forming method of described hard mask layer includes:
Step S11: deposit sub-hard mask layer and select oxygen plasma that this sub-hard mask layer is processed.
Step S12: perform step S11 several times, to form described hard mask layer.
5. method according to claim 4, it is characterised in that in described step S11, the thickness range of described sub-hard mask layer is
6. method according to claim 4, it is characterised in that in described step S11, described sub-hard mask layer adopts aumospheric pressure cvd technique to be formed, and wherein reacting gas is tetraethyl orthosilicate, SiH4In one or both, and O2Or O3In one or both, reaction temperature is 700 DEG C～1000 DEG C.
7. method according to claim 4, it is characterised in that it is O that described oxygen plasma processes the gas adopted2Or O3；Wherein, O2Or O3Range of flow be 50sccm～500sccm.
8. method according to claim 4, it is characterised in that the time that described oxygen plasma processes is 5s～60s, and radio-frequency power is 30W～1000W.
9. method according to claim 4, it is characterised in that the number of times performing step S11 in described step S12 is 5-30.
10. method according to claim 1, it is characterised in that the thickness of described hard mask layer is
11. method according to claim 1, it is characterised in that in described step S2, described patterning method includes:
Step S21: form the photoresist of patterning or the mask layer of bilayer, multilamellar on described hard mask layer；
Step S22: with described mask layer for hard mask layer described in mask etch, to form described opening.
12. method according to claim 1, it is characterised in that in described step S3, described wet etching selects the etching solution including HF.
13. method according to claim 1, it is characterised in that in described step S3, the angle between sidewall and the described control gate material layer of described inverted cone opening is 80-88 °.
14. method according to claim 1, it is characterised in that in described step S4, adjust described floating boom and the Sidewall angles of described control gate by controlling the etching selectivity between described hard mask layer and described floating gate material layer and described control gate material layer.
15. method according to claim 1, it is characterised in that in described step S1, described floating gate material layer selects polysilicon；
Described control gate material layer selects polysilicon.
16. the semiconductor storage unit prepared based on the method one of claim 1 to 16 Suo Shu.
17. an electronic installation, including the semiconductor storage unit described in claim 17.
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