CN105789114B - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

The invention discloses a kind of semiconductor devices and its manufacturing methods.Wherein in method, semi-conductor device manufacturing method, including providing insulating layer, wherein insulating layer covers the active area and grid of at least one semiconductor devices, the connecting hole for being used for active area is formed in a insulating layer, to expose at least part of active area, wherein connecting hole includes the first part with the first width and the second part with the second width, the first part of the connecting hole is adjacent to active area, and the first width fills metal material in the connecting hole less than the second width to form the contact for the active area.So that being formed for the contact of active area also includes the first part with the first width and the second part with the second width, to increase the width of active region contact, channel stress performance is improved.

Description

Semiconductor device and method of manufacturing the same

This application is a divisional application of the original application with application number 201210358628.X (application date is September 24, 2012, title of invention: semiconductor device and its manufacturing method).

technical field

The present invention relates to semiconductor devices and methods for manufacturing semiconductor devices.

Background technique

At present, in the Back-End-of-Line (BEOL) process of a semiconductor device, after the semiconductor device layer is formed, an insulating layer needs to be covered on the semiconductor device layer. A portion of the connection holes of the active area, and the connection holes are filled with a metal material to form contacts for the active area.

Figures 1a and 1b describe prior art methods for generating the above contacts using the Damascus process:

First, the insulating layer 101 is etched to form connection holes 102 so as to expose an active region (not shown in the figure), as shown in FIG. 1a.

The contact holes 102 are filled with a metal material to form contacts 103 of the active area, and then chemical mechanical polishing is performed to planarize the surface of the formed semiconductor device, as shown in FIG. 1b.

Here, reference numeral 104 denotes a photoresist layer, reference numeral 105 denotes a gate electrode, and reference numeral 106 denotes an interlayer.

With the development of the semiconductor manufacturing industry, the size of the designed and manufactured semiconductor devices is getting smaller and smaller. As a result, for example, the width of the active region contact 103 is further reduced. The effect of dual stress liner (Dual Stress Liner, DSL for short) on channel stress enhancement is significantly reduced, thereby leading to deterioration of channel stress performance.

In order to overcome this defect, a technical solution to enhance the channel stress for N-MOS (Negative-Mental-Oxide-Semiconductor, referred to as: N-Metal Oxide Semiconductor) is currently proposed by stretching the trench contact (Tensile TrenchContact). . But the effect of this scheme is not ideal. At the same time, this solution is only applicable to N-MOS, and is not applicable to P-MOS (Positive-Mental-Oxide-Semiconductor, referred to as: P-metal oxide semiconductor).

SUMMARY OF THE INVENTION

The inventors of the present invention found that there are problems in the above-mentioned prior art, and therefore proposed a new technical solution for at least one of the problems.

According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising:

providing an insulating layer, wherein the insulating layer covers an active region and a gate of at least one semiconductor device; forming a connection hole for the active region in the insulating layer so as to expose at least a portion of the active region, wherein the The connection hole includes a first portion with a first width and a second portion with a second width, the first portion of the connection hole is adjacent to the active region, and the first width is smaller than the second width; in the connection hole A metal material is filled to form contacts for the active regions.

Preferably, the step of forming a connection hole for the active region in the insulating layer so as to expose at least a part of the active region comprises: etching the insulating layer to form an opening having a first width, in order to expose at least a part of the active region; on the basis of the formed opening with the first width, the insulating layer is etched again to widen a part of the opening with the first width; wherein the The unwidened portion of the opening serves as the first portion of the connecting hole, and the widened portion of the opening serves as the second portion of the connecting hole.

Preferably, when forming the opening, a photoresist layer having a window with a first width is coated on the surface of the insulating layer, and the insulating layer is etched by using the photoresist layer having a window with a first width, thereby forming a photoresist layer having a window with a first width. an opening of a width; filling a bottom anti-reflection layer BARC in the opening having the first width; widening the window of the photoresist layer to have a second width, using the photoresist layer of the window having the second width The insulating layer is etched to widen a portion of the opening; the bottom anti-reflection layer BARC is removed.

Preferably, the height of the first part of the connection hole is higher than the height of the gate.

Preferably, the semiconductor device is a P-MOS transistor, and the metal material is a compressive stress type metal material; or the semiconductor device is an N-MOS transistor, and the metal material is a tensile stress type metal material.

Preferably, the at least one semiconductor device includes at least a first-type transistor and a second-type transistor, wherein the active region connection hole of the first-type transistor is filled with a first metal material having a first stress type, and the The active area connection holes of the second type transistors are filled with a second metal material having a second stress type.

Preferably, a connection hole for the active region is formed in the insulating layer to expose at least a part of the active region, and a metal material is filled in the connection hole to form a contact hole for the active region The steps include: etching and forming the connection hole in the insulating layer for the first type transistor, filling the connection hole with a first metal material and performing chemical mechanical polishing; and forming the second type in the insulating layer The connection holes are formed by transistor etching, and a second metal material is filled in the connection holes and chemical mechanical polishing is performed.

Preferably, a connection hole for the active region is formed in the insulating layer to expose at least a part of the active region, and a metal material is filled in the connection hole to form a contact hole for the active region The steps include: etching the first type transistor and the second type transistor respectively to form the connection hole in the insulating layer; shielding the connection hole for the second type transistor with a mask, and using a mask for the connection hole for the second type transistor. filling the connection holes for the first type transistors with a first metal material; and shielding the connection holes for the first type transistors with a mask, filling the connection holes for the second type transistors with a second metal material ; Chemical mechanical polishing is performed to planarize the surface of the semiconductor device formed.

Preferably, the first type transistor is a P-MOS transistor, and the first metal material is a compressive stress type metal material; the second type transistor is an N-MOS transistor, and the second metal material is a tensile stress type metal material; The type transistor is an N-MOS transistor, and the first metal material is a tensile stress type metal material; the second type transistor is a P-MOS transistor, and the second metal material is a compressive stress type metal material.

Preferably, the range of the first width is 20-50 nm, and the range of the second width is 30-100 nm.

Preferably, the depth of the connection hole is 500 angstroms to 2000 angstroms.

According to another aspect of the present invention, there is provided a semiconductor device comprising: an insulating layer, wherein the insulating layer covers an active region and a gate of at least one semiconductor device; and a contact for the active region is formed in the insulating layer ; wherein the contact includes a first portion having a first width and a second portion having a second width, the first portion of the contact being adjacent to the active region of the semiconductor device, and the first width being smaller than the second width.

Preferably, the height of the first part of the contact is higher than the height of the gate.

Preferably, at least one semiconductor device includes at least a first-type transistor and a second-type transistor, wherein a first metal material having a first stress type is filled for the active region connection hole of the first-type transistor, and a first metal material having a first stress type is filled for the first-type transistor. The active area connection holes of the two-type transistors are filled with a second metal material having a second stress type.

Preferably, the first type transistor is a P-MOS transistor, and the first metal material is a compressive stress type metal material; the second type transistor is an N-MOS transistor, and the second metal material is a tensile stress type metal material.

Preferably, the range of the first width is 20-50 nm, and the range of the second width is 30-100 nm.

Preferably, the depth of the connection hole is 500 angstroms to 2000 angstroms.

Other features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings.

Description of drawings

The accompanying drawings, which form a part of the specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

The present invention may be more clearly understood from the following detailed description with reference to the accompanying drawings, wherein:

1a and 1b are schematic diagrams of manufacturing semiconductor devices in the prior art.

FIG. 2 is a schematic diagram of an embodiment of a method for manufacturing a semiconductor device according to the present invention.

3a to 3g are process diagrams of manufacturing a semiconductor device according to an embodiment of the present invention.

4a-4d are process diagrams of another embodiment of manufacturing a semiconductor device according to the present invention.

5a-5d are process diagrams of another embodiment of manufacturing a semiconductor device according to the present invention.

Detailed ways

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the invention unless specifically stated otherwise.

Meanwhile, it should be understood that, for the convenience of description, the widths of various parts shown in the accompanying drawings are not drawn according to an actual proportional relationship.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the authorized description.

In all examples shown and discussed herein, any specific value should be construed as illustrative only and not as limiting. Accordingly, other examples of exemplary embodiments may have different values.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further discussion in subsequent figures.

As shown in FIG. 1b, as the size of semiconductor devices decreases, the space available for forming contacts in the active region also decreases. It is conceivable that in such a case, the size of the active area contact has to be reduced accordingly. The reduced active area contact leads to degraded stress effects. In addition, if the original size of the contact in the active area is kept unchanged, on the one hand, there may not be enough space to accommodate the contact, and on the other hand, the contact in the active area is likely to have an impact on the gate 105 . Getting too close to the gate will cause the contact 103 to possibly come into contact with the gate 105, thereby causing failure of the semiconductor device.

In order to address the above and other problems, the present disclosure proposes solutions using contacts of varying sizes. Specifically, due to the presence of the gate, the size of a portion of the active area contacts is adaptively reduced to adapt the contacts to the reduced semiconductor size. On the other hand, as shown in Figure 1b, above the gate height, there is still room where contacts of increased size can be used. Thus, the increased contact can improve channel stress performance. Thus, the present disclosure enhances the use of active region contacts with non-uniform dimensions (variable dimensions) so that good channel stress performance can be accommodated while accommodating reduced semiconductor device dimensions.

Specific embodiments of the present disclosure are described below.

FIG. 2 is a schematic diagram of an embodiment of a method for manufacturing a semiconductor device according to the present invention. As shown in FIG. 2 , the steps of the method for manufacturing a semiconductor device provided by this embodiment are as follows:

Step 201, providing an insulating layer, wherein the insulating layer covers the active region and the gate of at least one semiconductor device.

Step 202, forming a connection hole for the active region in the insulating layer so as to expose at least a portion of the active region, wherein the connection hole includes a first portion having a first width and a first portion having a second width. Two parts, the first part of the connection hole is adjacent to the active region, and the first width is smaller than the second width.

Step 203, filling the connection hole with a metal material to form a contact for the active region.

With the method of manufacturing a semiconductor device shown in FIG. 2, since the connection hole formed in the insulating layer includes a first portion having a first width and a second portion having a second width, the first portion of the connection hole is adjacent to the an active region, and the first width is smaller than the second width. Accordingly, the contact formed for the active region also includes a first portion having a first width and a second portion having a second width, thereby increasing the width of the active region contact and improving the channel stress performance.

Preferably, the range of the first width is 20-50 nm, and the range of the second width is 30-100 nm.

Preferably, the depth of the connection hole is 500 angstroms to 2000 angstroms.

Preferably, the above step 202 specifically includes:

First, the insulating layer is etched to form an opening having a first width so as to expose the active region.

Next, on the basis of the formed opening with the first width, the insulating layer is etched again to widen a part of the opening with the first width.

The unwidened part of the opening is used as the first part of the connection hole, and the widened part of the opening is used as the second part of the connection hole.

Preferably, the height of the first part of the connection hole is higher than the height of the gate. Thereby, a short circuit caused by the contact of the second portion of the connection hole with the gate can be avoided.

3a to 3g are process diagrams of manufacturing a semiconductor device according to an embodiment of the present invention.

First, a photoresist layer 302 having a window 303 with a first width is coated on the surface of the insulating layer 301, as shown in FIG. 3a.

Next, the insulating layer 301 is etched using the photoresist layer 302 having the window 303 of the first width, thereby forming the opening 304 of the first width to expose the active region, as shown in FIG. 3b .

Then, a bottom anti-reflection layer (BARC) 305 is filled in the opening 304 having the first width, as shown in FIG. 3c.

The window of the photoresist layer 302 is widened to have a second width 306, as shown in Figure 3d.

The insulating layer 301 is etched with the photoresist layer having the window 306 of the second width, thereby widening a part of the opening 303, as shown in FIG. 3e.

The bottom anti-reflective layer BARC 305 is removed, exposing the underlying active region (not shown), as shown in Figure 3f.

At this time, the unwidened part of the opening 303 is used as the first part 307 of the connection hole, and the widened part of the opening is used as the second part 308 of the connection hole.

The contact holes are filled with metal material to form contacts 309 for the active regions, as shown in Figure 3g. As shown, a contact 309 is formed conformally with the connection hole and includes a first portion having a first width (corresponding to opening portion 307 ) and a second portion having a second width (corresponding to opening portion 308 ) .

Finally, chemical mechanical polishing is performed to planarize the surface of the formed semiconductor device.

3a-3g, the reference numeral 311 is a gate electrode, and the reference numeral 312 is an interlayer. Preferably, the interlayer 312 is a silicide layer to reduce the contact resistance of the active region.

In the above embodiments, the semiconductor device may be a P-MOS transistor or an N-MOS transistor. However, the present disclosure is not limited to the above two types of semiconductor devices, and those skilled in the art can understand that the teachings of the present disclosure can be fully applied to other occasions where stress needs to be increased.

When the semiconductor device shown is a P-MOS transistor, the metal material is a compressive stress type metal material. Alternatively, when the semiconductor device is an N-MOS transistor, the metal material is a tensile stress type metal material.

Preferably, the semiconductor device may further include a first-type transistor and a second-type transistor at the same time, wherein a metal material having a first stress type may be filled for the active area connection hole of the first-type transistor, which is the second-type transistor. The active area connection holes of the transistors are filled with a metal material having the second stress type.

For two different types of transistors, the connection holes for the active regions of the first type transistors can be etched and filled with the first type of metal material, and then the connection holes used for the active regions of the second type transistors are etched and filled A second type of metallic material, thereby forming contacts for the active area. In another embodiment, the connection holes for the active regions of the first type transistors and the active regions of the second type transistors can also be etched at the same time, and then filled with the first type of metal material and the second type of metal respectively. material, thereby forming contacts for the active region.

4a-4d are process diagrams of another embodiment of manufacturing a semiconductor device according to the present invention. In this embodiment, the method of etching the connection holes for the active regions of the first type transistors and filling them with the first type of metal material, and then etching and filling the connection holes for the active regions of the second type transistors is described. The second type of metallic material.

First, a connection hole 403 is formed by etching in the insulating layer 401 for the first type transistor 41, as shown in FIG. 4a.

Preferably, the connection holes 403 can be formed according to the embodiments shown in FIGS. 3a-3f.

Subsequently, the connection hole 403 is filled with a metal material having the first stress type to form the first contact 404 of the first type transistor 41, and chemical mechanical polishing is performed, as shown in FIG. 4b.

Next, the connection hole 405 is formed by etching in the insulating layer 401 for the second type transistor 42, as shown in FIG. 4c.

Preferably, the connection holes 405 can be formed according to the embodiments shown in FIGS. 3a-3f.

Finally, the connection holes are filled with a metal material having the second stress type to form the second contact 406 of the second type transistor 42, and chemical mechanical polishing is performed, as shown in FIG. 4d.

In FIGS. 4a-4d, reference numeral 402 is a photoresist layer, reference numeral 411 is a gate electrode, and reference numeral 412 is an interlayer. Preferably, the interlayer 412 is a silicide layer.

The above-described exemplary embodiments show examples of successively forming active region contacts for different semiconductor devices. Those skilled in the art can understand that the technology according to the embodiments of the present invention can be used to form active area contacts for different types of semiconductor devices respectively. In this embodiment, the type of semiconductor device and the order in which contacts are formed for a particular type of semiconductor device are not critical. For example, in one embodiment, a first transistor representing one semiconductor device may be a PMOS transistor, and a second transistor representing another semiconductor device may be an NMOS transistor, and vice versa. In one embodiment, active area contacts may be formed first for the PMOS transistors. In another embodiment, the active region contacts may also be formed first for the NMOS transistors.

For PMOS transistors, the corresponding filled metal is compressive stress type. For N-MOS transistors, the corresponding filled metal is tensile stress type.

5a-5d are process diagrams of another embodiment of manufacturing a semiconductor device according to the present invention. In this embodiment, the manner of simultaneously etching the connection holes for the active regions of the first type transistors and the active regions of the second type transistors, respectively, is described.

First, connecting holes 503 are formed by etching in the insulating layer 501 for the first type transistor 51 and the second type transistor 52, respectively, as shown in FIG. 5a.

Second, the connection holes for the second type transistors 52 are shielded with a mask or barrier 513 (exemplarily shown), and the connection holes for the first type transistors 51 are filled with a first stress type metal material to form the first contact 504 of the first type transistor 51, as shown in FIG. 5b.

Subsequently, the connection holes for the first type transistors 51 are shielded by a mask or a barrier 514, and a metal material having a second stress type is filled in the connection holes for the second type transistors 52 to form a second stress type. The second contact 505 of the type 2 transistor 52 is shown in Figure 5c.

Finally, chemical mechanical polishing is performed to planarize the surface of the formed semiconductor device, as shown in Fig. 5d.

In FIGS. 5a-5d, reference numeral 502 is a photoresist layer, reference numeral 511 is a gate electrode, and reference numeral 512 is an interlayer. Preferably, a silicide layer is provided on the interlayer 512 .

In this embodiment, since all the connection holes may have the same structure, the connection holes can be directly formed for all the semiconductor devices. Subsequently, metals of different stress types are filled for different semiconductor devices respectively.

For the sake of brevity, the present disclosure describes only the steps that are closely related to its implementation. It should be understood by those skilled in the art that other steps existing in the process may also be included here.

Through the above embodiments, the obtained semiconductor device includes:

an insulating layer, wherein the insulating layer covers the active region and gate of at least one semiconductor device;

contacts for the active region, formed in the insulating layer;

wherein the contact includes a first portion having a first width and a second portion having a second width, the first portion of the contact is adjacent to an active region of the semiconductor device, and the first width is less than the second width.

Since the formed contact for the active region includes a first portion having a first width and a second portion having a second width, and the first width is smaller than the second width, the width of the contact in the active region is increased and the trench is improved Road stress performance.

So far, the method of manufacturing a semiconductor device and the formed semiconductor device according to the present invention have been described in detail. Some details that are well known in the art have not been described in order to avoid obscuring the concept of the present invention. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

While some specific embodiments of the present invention have been described in detail by way of example, those skilled in the art will appreciate that the above examples are provided for illustration only and not for the purpose of limiting the scope of the invention. For example, for the step of widening the photoresist layer in FIG. 3d, the widening may be performed as described above, or the photoresist layer having the windows of the first width may be removed and the photoresist layer having the windows of the second width may be reapplied. Such embodiments should also be considered to fall within the scope of the present disclosure.

Those skilled in the art will appreciate that modifications may be made to the above embodiments without departing from the scope and spirit of the present invention. The scope of the invention is defined by the appended claims.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising: providing an insulating layer, wherein the insulating layer covers the active region and the gate of the at least one semiconductor device; forming a connection hole for the active region in the insulating layer to expose at least a portion of the active region, wherein the connection hole includes a first portion having a first width and a second portion having a second width, a first portion of the connection hole is adjacent to the active region, and the first width is smaller than the second width; filling the connection holes with a metal material to form contacts for the active regions; Wherein, the semiconductor device is a P-MOS transistor, and the metal material is a compressive stress type metal material; or, the semiconductor device is an N-MOS transistor, and the metal material is a tensile stress type metal material; or, The at least one semiconductor device includes at least a transistor of a first type and a transistor of a second type, wherein an active area connection hole of the transistor of the first type is filled with a first metal material having a first stress type, and a transistor of the second type is filled with a first metal material having a first stress type. The active area connection holes of the type transistors are filled with a second metal material having a second stress type. 2 . The method of claim 1 , wherein a connection hole for the active region is formed in an insulating layer so as to expose at least a portion of the active region, and a metal material is filled in the connection hole. 3 . The steps to form contacts for the active regions include: forming the connection hole by etching for the first type transistor in the insulating layer, and filling the connection hole with a first metal material and performing chemical mechanical polishing; and The connection hole is formed by etching for the second type transistor in the insulating layer, and the connection hole is filled with a second metal material and chemical mechanical polishing is performed. 3. The method of claim 1, wherein a connection hole for the active region is formed in an insulating layer so as to expose at least a portion of the active region, and a metal material is filled in the connection hole The steps to form contacts for the active regions include: The connection holes are formed by etching for the first type transistor and the second type transistor respectively in the insulating layer; The connection holes for the second type transistors are shielded with a mask, and a first metal material is filled in the connection holes for the first type transistors; and Using a mask to shield the connection holes for the first type transistors, and filling the connection holes for the second type transistors with a second metal material; Chemical mechanical polishing is performed to planarize the surface of the formed semiconductor device. 4. The method of claim 1, wherein The first type transistor is a P-MOS transistor, and the first metal material is a compressive stress type metal material; the second type transistor is an N-MOS transistor, and the second metal material is a tensile stress type metal material; Alternatively, the first type transistor is an N-MOS transistor, and the first metal material is a tensile stress type metal material; the second type transistor is a P-MOS transistor, and the second metal material is a compressive stress type metal material. 5. The method of claim 1, wherein The range of the first width is 20-50 nm; The second width is in the range of 30-100 nm. 6. The method of claim 1, wherein The depth of the connection holes is 500 angstroms to 2000 angstroms. 7. A semiconductor device, comprising: an insulating layer, wherein the insulating layer covers the active region and gate of at least one semiconductor device; contacts for the active region, formed in the insulating layer; wherein the contact includes a first portion having a first width and a second portion having a second width, the first portion of the contact is adjacent to an active region of the semiconductor device, and the first width is less than the second width; Wherein, the semiconductor device is a P-MOS transistor, and the metal material in contact is a compressive stress type metal material; or the semiconductor device is an N-MOS transistor, and the metal material in contact is a tensile stress type metal material; or, At least one semiconductor device includes at least a transistor of a first type and a transistor of a second type, wherein the metal material used for the contact of the active region of the first type transistor is a first metal material having a first stress type, and the metal material used for the contact of the active region of the first type transistor is The metal material of the contact of the active region of the second type transistor is a second metal material with a second stress type. 8. The semiconductor device of claim 7, wherein The first type transistor is a P-MOS transistor, and the first metal material is a compressive stress type metal material; the second type transistor is an N-MOS transistor, and the second metal material is a tensile stress type metal material; Alternatively, the first type transistor is an N-MOS transistor, and the first metal material is a tensile stress type metal material; the second type transistor is a P-MOS transistor, and the second metal material is a compressive stress type metal material. 9. The semiconductor device of claim 7, wherein: The range of the first width is 20-50 nm; The second width is in the range of 30-100 nm. 10. The semiconductor device of claim 7, wherein The depth of contact is 500 angstroms to 2000 angstroms.