CN105789069A - Method for forming stacked silicon wafers using pad hybrid bonding process - Google Patents

Abstract

The present invention provides a method for forming stacked silicon wafers using a pad hybrid bonding process. First, an anisotropic etching method is used to form a groove structure in the pad area with a middle width greater than the width of the top, and then through subsequent The characteristics of the pad metal growing along the side wall, leaving a void in the pad metal, and finally through the stacking and heat treatment between the silicon substrates, the expansion and expansion of the pad metal fills the reserved cavity, avoiding The metal voids and defects formed at the corners of the metal pads are eliminated, and finally a defect-free and void-free pad structure with arc-shaped side walls between two stacked silicon wafers is formed, which improves the bonding quality and products of the pads reliability.

Description

Method for forming stacked silicon wafers using pad hybrid bonding process

technical field

The invention relates to the technical field of semiconductors, in particular to a method for forming stacked silicon wafers by using a press-welding point hybrid bonding process.

Background technique

Usually, in the manufacture of semiconductor silicon wafers, a silicon wafer contains hundreds or thousands of identical dies, which contain electronic components such as transistors, diodes, resistors, and circuits. The combination of these components forms a certain Silicon wafers with specific functions. However, the maximum area of a silicon wafer is limited by the maximum single-exposure area in semiconductor manufacturing and the application environment. With the popularization of portable devices such as mobile phones and notebook computers, the required dies are becoming smaller and smaller, but their functions are becoming more and more complex. and comprehensive. In order to meet the requirements of realizing complex functions within a certain silicon wafer area, we can adopt a stacked silicon wafer structure, that is, silicon wafers with different functions are stacked together through processes such as bonding, thinning and scribing between silicon wafers. , so that silicon chips with different functions can be combined without increasing the area of the silicon chip. The silicon chip stacking technology can save the area of the silicon chip and improve the performance at the same time. The common technology is 3D (ThreeDimension) stacked silicon wafer technology.

Take the CMOS image sensor silicon chip as an example, which usually includes logic circuits such as image sensor arrays for light sensing, signal control, readout and processing. Using 3D stacked silicon chip technology, we can form a photosensitive The pixel unit array structure forms signal control, readout and processing circuits on another silicon chip, and then these two different silicon chips are stacked together through a hybrid bonding process to form a complete CMOS image sensor silicon chip. Of course, the 3D stacking process is also applicable to any application that requires stacking different silicon wafers together.

In a hybrid bonding process, conductive pads in one die are bonded directly to conductive pads in another wafer. As shown in Figure 1, the stacked silicon wafers formed by the traditional pad bonding process are usually bonded by fusion bonding or heat treatment to the upper silicon wafer and the lower silicon wafer. The conductive voltage pads of the silicon chips are connected together to form a conductive path between the two silicon chips, but due to the heat treatment process for bonding, the metal material used on the conductive voltage pads will stretch and expand during the process, and eventually Metal voids and defects as shown in FIG. 1 are formed between two pads, especially at the corners of the metal pads, thereby affecting bonding quality and product reliability.

Contents of the invention

In order to overcome the above problems, the present invention aims to provide a method for preventing the formation of voids and defects in metal pads in 3D stacked silicon wafers, so as to improve bonding quality and product reliability.

In order to achieve the above object, the present invention provides a method for forming stacked silicon wafers using a pad hybrid bonding process, which includes:

Step 01: Provide two silicon wafers with semiconductor devices; wherein, each of the silicon wafers has a semiconductor device structure manufactured by a previous process and an interconnection structure manufactured by a subsequent process; then, a silicon wafer is formed on the entire silicon wafer a top dielectric layer and an adhesive layer; having pad areas in the top dielectric layer and the adhesive layer;

Step 02: using an anisotropic etching process to form a groove structure with a middle width greater than a top width in the pad area;

Step 03: growing a pad metal in the trench structure, wherein the pad metal closes the top of the trench structure and forms a reserved cavity in the middle of the trench structure;

Step 04: Grinding the top of the pad metal to the surface of the adhesive layer;

Step 05: stacking the two silicon wafers completed in step 04, and bonding the two silicon substrates together through the adhesive layer;

Step 06: Bonding the pad metal by using a heat treatment process, the pad metal expands and extends when heated, and fills the reserved cavity in the trench structure.

Preferably, the trench structure has arc-shaped sidewalls.

Preferably, the material of the top dielectric layer is silicon dioxide.

Preferably, the thickness of the top dielectric layer is

Preferably, the material of the adhesive layer is a composite structure of one or more of silicon oxynitride, silicon oxide, silicon nitride, and calcium carbide.

Preferably, the thickness of the adhesive layer is

Preferably, in the step 03, a copper electroplating process is used to grow pad metal copper in the trench structure.

Preferably, in the step 04, a chemical mechanical polishing process is used to grind the top of the pad metal to the surface of the adhesive layer.

Preferably, the grinding process monitors the grinding endpoint by endpoint detection technology and stops on the adhesive layer.

Preferably, the semiconductor device structure includes a pixel unit structure; the interconnection structure manufactured by the back-end process includes a metal layer and a via layer.

The present invention first uses an anisotropic etching method to form a groove structure in the pad region with a middle width greater than the width of the top, and then uses the characteristics of the subsequent pad metal to grow along the sidewall to reserve in the pad metal Holes, finally through the stacking and heat treatment between the silicon substrates, the extension and expansion of the metal pads fill the reserved voids, avoiding the formation of metal voids and defects at the corners of the metal pads, and finally forming two stacked silicon The defect-free and void-free pad structure with arc-shaped side walls between the chips improves the bonding quality of the pads and the reliability of products.

Description of drawings

Figure 1 is a schematic diagram of a stacked silicon wafer formed by a traditional pad hybrid bonding process

Fig. 2 is the structural representation of the stacked silicon chip prepared by a preferred embodiment of the present invention

Fig. 3 is a schematic flow chart of a method for forming stacked silicon wafers according to a preferred embodiment of the present invention

4 to 9 are schematic diagrams of each preparation step of a method for forming stacked silicon wafers according to a preferred embodiment of the present invention

detailed description

In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

The present invention will be further described in detail below in conjunction with accompanying drawings 2 to 9 and specific embodiments. It should be noted that the drawings are all in a very simplified form, using imprecise scales, and are only used to facilitate and clearly achieve the purpose of assisting in describing the present embodiment.

Please refer to Fig. 2, the stacked silicon chip structure is formed by using the paddle joint hybrid bonding process in this embodiment, including: the semiconductor device on a silicon chip 500 is an array of pixel units for light sensing; the semiconductor device structure is a pixel unit Structure, including photodiode, transmission tube gate, etc.; the back-end interconnection structure manufactured by the back-end process includes a metal layer and a via layer, and the back-end interconnection structure includes the first layer of metal, the first layer of through holes, and the second layer Metal, and second-layer through holes; another semiconductor device on the silicon wafer 600 is the control and readout circuit of the pixel unit, and the semiconductor device structure includes active devices such as MOS tubes and passive devices such as resistors and capacitors; 500 has a top dielectric layer 502, an adhesive layer 503, and a pad area (dotted line frame) located in the adhesive layer 503 and the top dielectric layer 502. There is a pad metal M in the pad area; throughout the silicon wafer 600 has a top dielectric layer 602, an adhesive layer 603, and a pad area (dotted line frame) in the top dielectric layer 602, and there is a pad metal M' in the pad area; Both the pad metals 501 and 601 in the pad area have arc-shaped side walls, and the pad metals 501 and 601 are free of voids and defects.

The description of the preparation process is carried out below with a partial enlarged view of the bonding pad region in Fig. 2, but this is not intended to limit the scope of the present invention; please refer to Fig. 3, the hybrid bonding process using bonding pads of the present embodiment A method of forming stacked silicon wafers, including:

Step 01: Provide two silicon substrates with semiconductor devices; wherein, each silicon substrate has a semiconductor device structure manufactured by the previous process and an interconnection structure manufactured by the subsequent process; then, the entire silicon substrate A top dielectric layer and an adhesive layer are formed on the bottom; there is a pad area in the top dielectric layer and the adhesive layer;

Specifically, the structure of the silicon wafer substrate can be referred to the description in FIG. 2. For the convenience of expression, only the local structure with the bonding pad area is shown in FIG. 4 for description. As shown in FIG. 4, in the silicon wafer 500, chemical vapor deposition The process deposits a top dielectric layer 502 and an adhesive layer 503 on the entire silicon wafer substrate 501; the material of the top dielectric layer 502 can be dielectric materials such as silicon dioxide, and the thickness varies according to different processes, and the thickness of the top dielectric layer 502 can be for The material of the adhesive layer 503 is a composite structure of one or more of silicon oxynitride, silicon oxide, silicon nitride, and calcium carbide, and the thickness of the adhesive layer 503 can be For subsequent bonding between two stacked silicon wafers.

Step 02: Using an anisotropic etching process, a groove structure with a middle width greater than the top width is formed in the pad area;

Specifically, please refer to FIG. 5 , taking the preparation of a silicon wafer 500 as an example, the formed groove structure has a curved sidewall S, and the top width W1 of the curved sidewall S is smaller than the middle width W2;

Step 03: growing pad metal in the trench structure, wherein the pad metal closes the top of the trench structure and forms a reserved cavity in the middle of the trench structure;

Specifically, please refer to FIG. 6 , taking the preparation of a silicon wafer 500 as an example, using a copper electroplating process to grow pad metal copper M in the trench structure, because the metal copper electroplating has a copper seed layer grown along the side wall characteristics, and the top width of the trench structure is smaller than the middle width, therefore, the top region of the trench structure will be closed first, so that the subsequent copper plating growth can only be carried out on the surface of the silicon wafer, but not inside the trench structure, thus A pad metal M with a reserved cavity K inside is formed.

Step 04: Grinding the top of the pad metal to the surface of the bonding layer;

Specifically, referring to FIG. 7, taking the preparation of a silicon wafer 500 as an example, a chemical mechanical polishing process is used to grind the top of the pad metal to the surface of the adhesive layer 503, thereby removing the copper metal on the surface of the silicon wafer 500. Due to chemical The mechanical polishing process has a difference in the grinding rate of the metal copper and the bonding layer. The grinding process monitors the grinding end point through the endpoint detection technology and stops on the bonding layer 503; Adhesive layer 503 is allowed to have arrive The thickness of the pad is damaged, while the metal copper of the pad is only reserved in the groove structure;

Step 05: stacking the two silicon wafer substrates completed in step 04, and bonding the two silicon substrates together through an adhesive layer;

Specifically, please refer to FIG. 8 , the stacking and bonding process of the silicon wafer substrate can adopt a conventional process, which will not be repeated here. The above steps 01-04 describe a silicon wafer 500, and here another silicon wafer 600 in FIG. Lamination layer 603 and pad area, there is a pad metal M' in the pad area, and there is a reserved hole K in the pad metal M'; it should be noted that each silicon chip can be prepared at the same time, or one the preparation of one;

Step 06: The heat treatment process is used to bond the pad metal, and the pad metal expands and extends when heated, filling the reserved cavity in the groove structure.

Specifically, please refer to Fig. 9, the welding pad metal copper M and M' are bonded through heat treatment, the pad metal M and M' expand and expand when heated, fill the reserved cavity K, and avoid metal pressure welding Metal voids and defects are formed at the corner positions of the dots; thereby forming a defect-free and void-free bonding pad metal M and M' structure with arc-shaped sidewalls between the two stacked silicon wafers 500 and 600, improving the bonding pad Bonding quality and product reliability.

Although the present invention has been disclosed above with preferred embodiments, the embodiments are only examples for convenience of description, and are not intended to limit the present invention. Those skilled in the art can make For several changes and modifications, the scope of protection claimed by the present invention should be based on the claims.

Claims (10)

1. A method of forming a stacked silicon chip using a pad hybrid bonding process, characterized in that, comprising: Step 01: Provide two silicon wafers with semiconductor devices; wherein, each of the silicon wafers has a semiconductor device structure manufactured by a previous process and an interconnection structure manufactured by a subsequent process; then, a silicon wafer is formed on the entire silicon wafer a top dielectric layer and an adhesive layer; having pad areas in the top dielectric layer and the adhesive layer; Step 02: using an anisotropic etching process to form a groove structure with a middle width greater than a top width in the pad area; Step 03: growing a pad metal in the trench structure, wherein the pad metal closes the top of the trench structure and forms a reserved cavity in the middle of the trench structure; Step 04: Grinding the top of the pad metal to the surface of the adhesive layer; Step 05: stacking the two silicon wafers completed in step 04, and bonding the two silicon substrates together through the adhesive layer; Step 06: Bonding the pad metal by using a heat treatment process, the pad metal expands and extends when heated, and fills the reserved cavity in the trench structure. 2. The method of claim 1, wherein the trench structure has curved sidewalls. 3. The method according to claim 1, wherein the material of the top dielectric layer is silicon dioxide. 4. method according to claim 3, is characterized in that, the thickness of described top dielectric layer is 5. The method according to claim 1, wherein the material of the adhesive layer is a composite structure of one or more of silicon oxynitride, silicon oxide, silicon nitride, and calcium carbide. 6. method according to claim 5, is characterized in that, the thickness of described bonding layer is 7 . The method according to claim 1 , wherein, in the step 03 , a copper electroplating process is used to grow pad metal copper in the groove structure. 7 . 8 . The method according to claim 1 , wherein in the step 04 , a chemical mechanical polishing process is used to grind the top of the pad metal to the surface of the adhesive layer. 9. The method according to claim 8, wherein the grinding process monitors the grinding end point by an end point detection technology and stops on the adhesive layer. 10 . The method according to claim 1 , wherein the semiconductor device structure comprises a pixel unit structure; and the interconnection structure manufactured by the subsequent process comprises a metal layer and a via layer. 11 .