CN105788555A

CN105788555A - Shifting register unit and driving method thereof as well as grid electrode driving circuit and display device

Info

Publication number: CN105788555A
Application number: CN201610339380.0A
Authority: CN
Inventors: 米磊; 王世君; 薛艳娜
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2016-05-19
Filing date: 2016-05-19
Publication date: 2016-07-20
Anticipated expiration: 2036-05-19
Also published as: CN105788555B

Abstract

The invention provides a shifting register unit and a driving method thereof as well as a grid electrode driving circuit and a display device, relating to the technical field of display, and aiming at simplifying the grid electrode driving circuit. The shifting register unit comprises a first control module, an input module, a second control module, a first output module, a second output module, a third output module, a fourth output module, and an output control module, wherein the first control module is used for controlling voltage of a first node; the input module is used for controlling voltage of a second node; the second control module is used for controlling voltage of the first node, the second node, a fourth node and a fifth node; the first output module, the second output module, the third output module and the fourth output module are used for outputting clock signals of a first clock signal end, a second clock signal end, a third clock signal end and a fourth clock signal end respectively; and the output control module is used for controlling the fourth output module to output the voltage of the fourth node. The shifting register unit provided by the embodiment of the invention is used for manufacturing the display device.

Description

Shift register cell and driving method, gate driver circuit, display device

Technical field

The present invention relates to Display Technique field, particularly relate to a kind of shift register cell and driving method, gate driver circuit, display device.

Background technology

Integrated raster data model is (English: GateDriveOnArray, it is called for short: GOA), it is utilize thin film transistor (TFT) (English: thinfilmtransistor, it is called for short: TFT) gate driver circuit is produced on thin-film transistor array base-plate by LCD (Liquid Crystal Display) array (Array) processing procedure, to realize the type of drive of progressive scan.

Gate driver circuit design is all the key problem that those skilled in the art constantly study all the time.Integrated gate driver technology is utilized to be integrated on the array base palte of display floater by gate driver circuit, it is possible to save gate switch Integrated circuit portion, thus reducing product cost from material cost and processing technology two aspect.Existing gate driver circuit is generally made up of multiple shift register cells, the signal output part of arbitrary shift register cell connects a grid line of display floater, for providing gate drive signal to the grid line of its connection, and each shift register cell includes a pre-charge module, a drop-down module, a stable module and an output module, and each module includes again multiple TFT.But, along with improving constantly of display floater resolution, in display floater, the quantity of grid line is also continuously increased, so needing to design more shift register cell formation gate driver circuit to provide gate drive signal for display floater, owing to existing shift register cell structure is complex, and each shift register cell is only capable of and provides gate drive signal to a grid line, so existing gate driver circuit is unfavorable for simplifying the technique of display floater and reducing the generation cost of display floater.Additionally, narrow frame technology has enjoyed consumers since occurring always.Narrow frame technology must premised on the area reducing gate driver circuit, and in prior art, grid electrode drive circuit structure is complicated, it is difficult to the area of reduction gate driver circuit, is therefore also unfavorable for the realization of narrow frame technology.

To sum up, how simplifying gate driver circuit is those skilled in the art's technical problems urgently to be resolved hurrily.

Summary of the invention

Embodiments of the invention provide a kind of shift register cell and driving method, gate driver circuit, display device, are used for simplifying gate driver circuit.

For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that

First aspect, it is provided that a kind of shift register cell, including: first controls module, input module, the second control module, the first output module, the second output module, the 3rd output module, the 4th output module and output control module；

Described first controls module connects the first scanning signal end, the second scanning signal end, the first signal input part, secondary signal input and primary nodal point, for the voltage of described first signal input part being inputted primary nodal point under the control of the scan signal of the first scanning signal end, or under the control of the second the second scanning signal scanning signal end, the voltage of described secondary signal input is inputted primary nodal point；

Described input module connects secondary nodal point, described secondary signal input and described primary nodal point, for the voltage of described secondary signal input being inputted described secondary nodal point under the control of the voltage of described primary nodal point；

Described second controls module connects the first level terminal, second electrical level end, the 3rd node, fourth node, the 5th node, described primary nodal point and described secondary nodal point, for the voltage of described first level terminal inputting described 3rd node under the control of the voltage of described primary nodal point and under the control of the voltage of described 3rd node, the voltage of described second electrical level end being inputted described primary nodal point, secondary nodal point, fourth node and the 5th node；

Described first output module connects the first signal output part, the first clock signal terminal, described first level terminal, described secondary nodal point, described 3rd node, described fourth node and described 5th node, for the first clock signal of described first clock signal terminal being exported at described first signal output part under the control of the voltage of described secondary nodal point, or under the control of the voltage of described 3rd node, the voltage of described fourth node is exported at described first signal output part；

Described second output module connects secondary signal outfan, second clock signal end, described first level terminal, described secondary nodal point, described 3rd node, described fourth node and described 5th node, for the second clock signal of described second clock signal end being exported at described secondary signal outfan under the control of the voltage of described secondary nodal point, or under the control of the voltage of described 3rd node, the voltage of described fourth node is exported at described secondary signal outfan；

Described 3rd output module connects the 3rd signal output part, the 3rd clock signal terminal, described first level terminal, described secondary nodal point, described 3rd node, described fourth node and described 5th node, for the 3rd clock signal of described 3rd clock signal terminal being exported at described 3rd signal output part under the control of the voltage of described secondary nodal point, or under the control of the voltage of described 3rd node, the voltage of described fourth node is exported at described 3rd signal output part；

Described 4th output module connects the 4th signal output part, the 4th clock signal terminal, described first level terminal, described secondary nodal point, described 3rd node, described fourth node and described 5th node, for the 4th clock signal of described 4th clock signal terminal being exported at described 4th signal output part under the control of the voltage of described secondary nodal point, or under the control of the voltage of described 3rd node, the voltage of described fourth node is exported at described 4th signal output part；

Described output control module connects described first scanning signal end, described 4th signal output part and described second electrical level end, for being exported at described 4th signal output part by the voltage of described second electrical level end under the control of the scan signal of described first scanning signal end.

Optionally, described first control module includes: the first transistor and transistor seconds；

First pole of described the first transistor connects described first signal input part, and the second pole of described the first transistor connects described primary nodal point；The grid of described the first transistor connects described first scanning signal end；

First pole of described transistor seconds connects described secondary signal input, and the second pole of described transistor seconds connects described primary nodal point；The grid of described transistor seconds connects described second scanning signal end.

Optionally, described input module includes: third transistor；

First pole of described third transistor connects described secondary signal input, and the second pole of described third transistor connects described secondary nodal point, and the grid of described third transistor connects described primary nodal point.

Optionally, described second control module includes: the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor and the 9th transistor；

First pole of described 4th transistor connects described first level terminal, and the second pole of described 4th transistor connects described 3rd node, and the grid of described 4th transistor connects described first level terminal；

First pole of described 5th transistor connects described 3rd node, and the second pole of described 5th transistor connects described second electrical level end, and the grid of described 5th transistor connects described primary nodal point；

First pole of described 6th transistor connects described primary nodal point, and the second pole of described 6th transistor connects described second electrical level end, and the grid of described 6th transistor connects described 3rd node；

First pole of described 7th transistor connects described secondary nodal point, and the second pole of described 7th transistor connects described second electrical level end, and the grid of described 7th transistor connects described 3rd node；

First pole of described 8th transistor connects described second electrical level end, and the second pole of described 8th transistor connects described 5th node, and the grid of described 8th transistor connects described 3rd node；

First pole of described 9th transistor connects described second electrical level end, and the second pole of described 9th transistor connects described fourth node, and the grid of described 9th transistor connects described 3rd node.

Optionally, described first output module includes: the tenth transistor, the 11st transistor, the tenth two-transistor, the 13rd transistor and the first electric capacity；

First pole of described tenth transistor connects described secondary nodal point, and the second pole of described tenth transistor connects the first pole of described first electric capacity, and the grid of described tenth transistor connects described first level terminal；

First pole of described 11st transistor connects described first clock signal terminal, and the second pole of described 11st transistor connects described first signal output part, and the grid of described 11st transistor connects the first pole of described first electric capacity；

First pole of described tenth two-transistor connects the first pole of described first electric capacity, and the second pole of described tenth two-transistor connects described 5th node, and the grid of described tenth two-transistor connects described three nodes；

First pole of described 13rd transistor connects described first signal output part, and the second pole of described 13rd transistor connects described fourth node, and the grid of described 13rd transistor connects described three nodes；

Second pole of described first electric capacity connects described first signal output part.

Optionally, described second output module includes: the 14th transistor, the 15th transistor, the 16th transistor, the 17th transistor and the second electric capacity；

First pole of described 14th transistor connects described secondary nodal point, and the second pole of described 14th transistor connects the first pole of described second electric capacity, and the grid of described 14th transistor connects described first level terminal；

First pole of described 15th transistor connects described second clock signal end, and the second pole of described 15th transistor connects described secondary signal outfan, and the grid of described 15th transistor connects the first pole of described second electric capacity；

First pole of described 16th transistor connects the first pole of described second electric capacity, and the second pole of described 16th transistor connects described 5th node, and the grid of described 16th transistor connects described three nodes；

First pole of described 17th transistor connects described secondary signal outfan, and the second pole of described 17th transistor connects described fourth node, and the grid of described 17th transistor connects described three nodes；

Second pole of described second electric capacity connects described secondary signal outfan.

Optionally, described 3rd output module includes: the 18th transistor, the 19th transistor, the 20th transistor, the 21st transistor and the 3rd electric capacity；

First pole of described 18th transistor connects described secondary nodal point, and the second pole of described 18th transistor connects the first pole of described 3rd electric capacity, and the grid of described 18th transistor connects described first level terminal；

First pole of described 19th transistor connects described 3rd clock signal terminal, and the second pole of described 19th transistor connects described 3rd signal output part, and the grid of described 19th transistor connects the first pole of described 3rd electric capacity；

First pole of described 20th transistor connects the first pole of described 3rd electric capacity, and the second pole of described 20th transistor connects described 5th node, and the grid of described 20th transistor connects described three nodes；

First pole of described 21st transistor connects described 3rd signal output part, and the second pole of described 21st transistor connects described 5th node, and the grid of described 21st transistor connects described four nodes；

Second pole of described 3rd electric capacity connects described 3rd signal output part.

Optionally, described 4th output module includes: the 20th two-transistor, the 23rd transistor, the 24th transistor, the 25th transistor and the 4th electric capacity；

First pole of described 20th two-transistor connects described secondary nodal point, and the second pole of described 20th two-transistor connects the first pole of described 4th electric capacity, and the grid of described 20th two-transistor connects described first level terminal；

First pole of described 23rd transistor connects described 4th clock signal terminal, and the second pole of described 23rd transistor connects described 4th signal output part, and the grid of described 23rd transistor connects the first pole of described 4th electric capacity；

First pole of described 24th transistor connects the first pole of described 4th electric capacity, and the second pole of described 24th transistor connects described 5th node, and the grid of described 24th transistor connects described three nodes；

First pole of described 25th transistor connects described 4th signal output part, and the second pole of described 25th transistor connects described fourth node, and the grid of described 25th transistor connects described three nodes；

Second pole of described 4th electric capacity connects described 4th signal output part.

Optionally, described output control module includes: the 26th transistor；

First pole of described 26th transistor connects described 4th signal output part, and the second pole of described 26th transistor connects described second electrical level end, and the grid of described 26th transistor connects described first scanning signal end.

Optionally, first clock signal of described first clock signal terminal, the second clock signal of described second clock signal end, described 3rd clock signal of the 3rd clock signal terminal and the 4th clock signal of described 4th clock signal terminal differ 1/4 clock cycle successively, and the dutycycle of the 4th clock signal of the 3rd clock signal of the second clock signal of the first clock signal of described first clock signal terminal, described second clock signal end, described 3rd clock signal terminal and described 4th clock signal terminal is 25%.

Optionally, it is characterised in that each transistor is N-type transistor；Or each transistor is P-type transistor.

Second aspect, it is provided that the driving method of a kind of shift register cell, for driving the shift register cell described in any one of first aspect；Described method includes:

First stage, first controls module inputs primary nodal point by the voltage of the first signal input part under the control of the first scan signal scanning signal end；The voltage of secondary signal input is inputted secondary nodal point by input module under the control of the voltage of primary nodal point；The voltage of second electrical level end is exported at signal output part by output control module under the control of the first scan signal scanning signal end；

Second stage, first controls module inputs primary nodal point by the voltage of secondary signal input under the control of the second the second scanning signal scanning signal end；The voltage of secondary signal input is inputted secondary nodal point by input module under the control of the voltage of primary nodal point；First clock signal of the first clock signal terminal is exported at the first signal output part by the first output module under the control of the voltage of secondary nodal point；

Phase III, first controls module inputs primary nodal point by the voltage of secondary signal input under the control of the second the second scanning signal scanning signal end；The voltage of secondary signal input is inputted secondary nodal point by input module under the control of the voltage of primary nodal point；The second clock signal of second clock signal end is exported at secondary signal outfan by the second output module under the control of the voltage of secondary nodal point；

Fourth stage, first controls module inputs primary nodal point by the voltage of secondary signal input under the control of the second the second scanning signal scanning signal end；The voltage of secondary signal input is inputted secondary nodal point by input module under the control of the voltage of primary nodal point；3rd clock signal of the 3rd clock signal terminal is exported at the 3rd signal output part by the 3rd output module under the control of the voltage of secondary nodal point；

In 5th stage, first controls module inputs primary nodal point by the voltage of secondary signal input under the control of the second the second scanning signal scanning signal end；The voltage of secondary signal input is inputted secondary nodal point by input module under the control of the voltage of primary nodal point；4th clock signal of described 4th clock signal terminal is exported at described 4th signal output part by the 4th output module under the control of the voltage of secondary nodal point；

In 6th stage, second controls module inputs the voltage of the first level terminal the 3rd node under the second control scanning signal and under the control of the voltage of the 3rd node, the voltage of second electrical level end is inputted primary nodal point, secondary nodal point, fourth node and the 5th node；First output module, the second output module, the 3rd output module and described 4th output module export the voltage of fourth node respectively under the control of the voltage of described 3rd node at the first signal output part, secondary signal outfan, the 3rd signal output part and the 4th signal output part；

In 7th stage, control module and under the control of primary nodal point, the voltage of the first level terminal is inputted the 3rd node and under the control of the voltage of the 3rd node, the voltage of second electrical level end is inputted primary nodal point, secondary nodal point, fourth node and the 5th node.

The third aspect, it is provided that a kind of gate driver circuit, including the shift register cell described at least one any one of first aspect.

Fourth aspect, it is provided that a kind of display device, including the gate driver circuit described in the third aspect.

nullThe shift register cell that the embodiment of the present invention provides includes: first controls module、Input module、Second controls module、First output module、Second output module、3rd output module、4th output module and output control module，Wherein the voltage of secondary signal input can be inputted primary nodal point by the first control module，The voltage of secondary signal input can be inputted secondary nodal point by input module，Second controls module can voltage input the 3rd node of the first level terminal and the voltage of second electrical level end is inputted primary nodal point、Secondary nodal point、Fourth node and the 5th node，First clock signal of the first clock signal terminal can be exported by the first output module at the first signal output part，Or the voltage of fourth node is exported at the first signal output part，The second clock signal of second clock signal end can be exported by the second output module at secondary signal outfan，Or the voltage of fourth node is exported at secondary signal outfan，3rd clock signal of the 3rd clock signal terminal can be exported by the 3rd output module at the 3rd signal output part，Or the voltage of fourth node is exported at the 3rd signal output part，4th clock signal of the 4th clock signal terminal can be exported by the 4th output module at the 4th signal output part，Or the voltage of fourth node is exported at the 4th signal output part，The voltage of second electrical level end can be exported by output control module at the 4th signal output part，Namely the embodiment of the present invention shares the first control module by four signal output module、Input module and second controls module，Thus gate drive signal can be provided to a grid line respectively，Compared in prior art between each shift register cell without common part and only provide gate drive signal to grid line，The shift register cell that the embodiment of the present invention provides shares the first control module by four signal output module、Input module and second controls module，Thus gate drive signal can be provided to a grid line respectively，Be equivalent to public for the partial function in level Four shift register cell，So the embodiment of the present invention can reduce the device in shift register cell，And then simplification gate driver circuit.

Accompanying drawing explanation

In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.

The schematic diagram of the shift register cell that Fig. 1 provides for embodiments of the invention；

The circuit diagram of the shift register cell that Fig. 2 provides for embodiments of the invention；

The flow chart of steps of the driving method of the shift register cell that Fig. 3 provides for embodiments of the invention；

The sequential chart of each signal in the shift register cell that Fig. 4 provides for embodiments of the invention；

The schematic diagram of the gate driver circuit that Fig. 5 provides for embodiments of the invention.

Detailed description of the invention

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.

The transistor adopted in all embodiments of the invention can be all the device that thin film transistor (TFT) or field effect transistor or other characteristics are identical, is mainly switch transistors pipe according to the transistor that effect embodiments of the invention in circuit adopt.The source electrode of the switch transistors pipe owing to adopting here, drain electrode are symmetrical, so its source electrode, drain electrode can be exchanged.In embodiments of the present invention, for distinguishing transistor the two poles of the earth except grid, being wherein called the first pole by source electrode, drain electrode is called the second pole.The intermediate ends of transistor is specified to be grid, signal input part is that source electrode, signal output part are drain electrode by the form in accompanying drawing.In addition the switch transistors pipe that the embodiment of the present invention adopts includes P type switch transistors pipe and N-type switch transistors pipe two kinds, wherein, P type switch transistors pipe turns on when grid is low level, end when grid is high level, N-type switch transistors pipe, for turning on when grid is high level, ends when grid is low level.

It should be noted that, " first " in the application, printed words such as " second " are only used to function is made a distinction with the essentially identical identical entry of effect or similar item, " first ", printed words such as " second " are not that quantity and execution order are being defined, same embodiment such as, be likely to occur " the first transistor ", " transistor seconds ", " the 4th transistor " is without " third transistor " occur, then " first ", " second ", " the 4th " only can be understood as the differentiation to different crystal pipe, and it is not intended that this embodiment also includes " third transistor ".

The embodiment of the present invention provides a kind of shift register cell, with reference to shown in Fig. 1, this shift register cell includes: first controls module 11, input module the 12, second control module the 13, first output module the 14, second output module the 15, the 3rd output module the 16, the 4th output module 17 and output control module 18.

Wherein, first controls module 11 connects the first scanning signal end S1, the second scanning signal end S2, the first signal input part Input1, secondary signal input Input2 and primary nodal point a, for the voltage of the first signal input part Input1 being inputted primary nodal point a under the control of the scan signal of the first scanning signal end S1, or under the control of the second the second scanning signal scanning signal end S2, the voltage of secondary signal input Input2 is inputted primary nodal point a.

Input module 12 connects secondary nodal point b, secondary signal input Input2 and primary nodal point a, for the voltage of secondary signal input Input2 being inputted secondary nodal point b under the control of the voltage of primary nodal point a.

Second controls module 13 connects the first level terminal V1, second electrical level end V2, the 3rd node c, fourth node d, the 5th node e, primary nodal point a and secondary nodal point b, for the voltage of the first level terminal V1 inputting the 3rd node c under the control of the voltage of primary nodal point a and under the control of the voltage of the 3rd node c, the voltage of second electrical level end V2 being inputted primary nodal point a, secondary nodal point b, fourth node d and the 5th node e.

First output module 14 connects the first signal output part Output1, the first clock signal terminal CLK1, the first level terminal V1, secondary nodal point b, the 3rd node c, fourth node d and the 5th node e, for first clock signal of the first clock signal terminal CLK1 being exported at the first signal output part Output1 under the control of the voltage of secondary nodal point b, or by the output at the first signal output part Output1 of the voltage of fourth node d under the control of the voltage of the 3rd node c.

Second output module 15 connects secondary signal outfan Output2, second clock signal end CLK2, the first level terminal V1, secondary nodal point b, the 3rd node c, fourth node d and the 5th node e, for the second clock signal of second clock signal end CLK2 being exported at secondary signal outfan Output2 under the control of the voltage of secondary nodal point b, or under the control of the voltage of the 3rd node c, the voltage of fourth node d is exported at secondary signal outfan Output2.

3rd output module 16 connects the 3rd signal output part Output3, the 3rd clock signal terminal CLK3, the first level terminal V1, secondary nodal point b, the 3rd node c, fourth node d and the 5th node e, for the 3rd clock signal of the 3rd clock signal terminal CLK3 being exported at the 3rd signal output part Output3 under the control of the voltage of secondary nodal point b, or under the control of the voltage of the 3rd node c, the voltage of fourth node d is exported at the 3rd signal output part Output3.

4th output module 17 connects the 4th signal output part Output4, the 4th clock signal terminal CLK4, the first level terminal V1, secondary nodal point b, the 3rd node c, fourth node d and the 5th node e, for the 4th clock signal of the 4th clock signal terminal CLK4 being exported at the 4th signal output part Output4 under the control of the voltage of secondary nodal point b, or under the control of the voltage of the 3rd node c, the voltage of fourth node d is exported at the 4th signal output part Output4.

Described output control module 18 connects described first scanning signal end S1, described 4th signal output part Output4 and described second electrical level end V2, for being exported at the 4th signal output part Output4 by the voltage of second electrical level end V2 under the control of the scan signal of described first scanning signal end S1.

Further, with reference to shown in Fig. 2, first controls module 11 includes: the first transistor T1 and transistor seconds T2；

First pole of the first transistor T1 connects second pole of the first signal input part Input1, the first transistor T1 and connects primary nodal point a；The grid of the first transistor T1 connects the first scanning signal end S1；

First pole of transistor seconds T2 connects second pole of secondary signal input Input2, transistor seconds T2 and connects primary nodal point a；The grid of transistor seconds T2 connects the second scanning signal end S2.

Input module 12 includes: third transistor T3；

The grid of the second pole connection secondary nodal point b, third transistor T3 that first pole of third transistor T3 connects secondary signal input Input2, third transistor T3 connects primary nodal point a.

Second controls module 13 includes: the 4th transistor T4, the 5th transistor T5, the 6th transistor T6, the 7th transistor T7, the 8th transistor T8 and the 9th transistor T9；

First pole of the 4th transistor T4 connects the first level terminal V1, and second pole of the 4th transistor T4 connects the 3rd node c, and the grid of the 4th transistor T4 connects the first level terminal V1；

The grid of the second pole connection second electrical level end V2, the 5th transistor T5 that first pole of the 5th transistor T5 connects the 3rd node c, the 5th transistor T5 connects primary nodal point a；

First pole of the 6th transistor T6 connects second pole of primary nodal point a, the 6th transistor T6 and connects second electrical level end V2, and the grid of the 6th transistor connects the 3rd node c；

The grid of the second pole connection second electrical level end V2, the 7th transistor T7 that first pole of the 7th transistor T7 connects secondary nodal point b, the 7th transistor T7 connects the 3rd node c；

The grid of the second pole connection the 5th node e, the 8th transistor T8 that first pole of the 8th transistor T8 connects second electrical level end V2, the 8th transistor T8 connects the 3rd node c；

The grid of the second pole connection fourth node d, the 9th transistor T9 that first pole of the 9th transistor T9 connects second electrical level end V2, the 9th transistor T9 connects the 3rd node c.

First output module 14 includes: the tenth transistor T10, the 11st transistor T11, the tenth two-transistor T12, the 13rd transistor T13 and the first electric capacity C1；

First pole of the tenth transistor T10 connects secondary nodal point b, and second pole of the tenth transistor T10 connects first pole of the first electric capacity C1, and the grid of the tenth transistor T10 connects the first level terminal V1；

First pole of the 11st transistor T11 connects the first clock signal terminal CLK1, and second pole of the 11st transistor T11 connects the first signal output part Output1, and the grid of the 11st transistor T11 connects first pole of the first electric capacity C1；

First pole of the tenth two-transistor T12 connects first pole of the first electric capacity C1, and second pole of the tenth two-transistor T12 connects the 5th node e, and the grid of the tenth two-transistor T12 connects three node c；

First pole of the 13rd transistor T13 connects the first signal output part Output1, and second pole of the 13rd transistor T13 connects fourth node d, and the grid of the 13rd transistor T13 connects three node c；

Second pole of the first electric capacity C1 connects the first signal output part Output1.

Second output module 15 includes: the 14th transistor T14, the 15th transistor T15, the 16th transistor T16, the 17th transistor T17 and the second electric capacity C2；

First pole of the 14th transistor T14 connects secondary nodal point b, and second pole of the 14th transistor T14 connects first pole of the second electric capacity C2, and the grid of the 14th transistor T14 connects the first level terminal V1；

First pole of the 15th transistor T15 connects second pole of second clock signal end CLK2, the 15th transistor T15 and connects secondary signal outfan Output2, and the grid of the 15th transistor T15 connects first pole of the second electric capacity C2；

First pole of the 16th transistor T16 connects first pole of the second electric capacity C2, and second pole of the 16th transistor T16 connects the 5th node e, and the grid of the 16th transistor T16 connects three node c；

First pole of the 17th transistor T17 connects second pole of secondary signal outfan Output2, the 17th transistor T17 and connects fourth node d, and the grid of the 17th transistor T17 connects three node c；

Second pole of the second electric capacity C2 connects secondary signal outfan Output2.

3rd output module includes: the 18th transistor T18, the 19th transistor T19, the 20th transistor T20, the 21st transistor T21 and the 3rd electric capacity C3；

First pole of the 18th transistor T18 connects first pole of second pole connection the 3rd electric capacity C3 of secondary nodal point b, the 18th transistor T18, and the grid of the 18th transistor T18 connects the first level terminal V1；

First pole of the 19th transistor T19 connects first pole of grid connection the 3rd electric capacity C3 of second pole connection the 3rd signal output part Output3, the 19th transistor T19 of the 3rd clock signal terminal CLK3, the 19th transistor T19；

First pole of the 20th transistor T20 connects first pole of the 3rd electric capacity C3, and second pole of the 20th transistor T20 connects the 5th node e, and the grid of the 20th transistor T20 connects three node c；

First pole of the 21st transistor T21 connects second pole of the 3rd signal output part Output3, the 21st transistor T21 and connects fourth node d, and the grid of the 21st transistor T21 connects three node c；

Second pole of the 3rd electric capacity C3 connects the 3rd signal output part Output3.

4th output module 17 includes: the 20th two-transistor T22, the 23rd transistor T23, the 24th transistor T24, the 25th transistor T25 and the 4th electric capacity C4；

First pole of the 20th two-transistor T22 connects first pole of second pole connection the 4th electric capacity C4 of secondary nodal point b, the 20th two-transistor T22, and the grid of the 20th two-transistor T22 connects the first level terminal V1；

First pole of the 23rd transistor T23 connects first pole of grid connection the 4th electric capacity C4 of second pole connection the 4th signal output part Output4, the 23rd transistor T23 of the 4th clock signal terminal CLK4, the 23rd transistor T23；

First pole of the 24th transistor T24 connects first pole of the 4th electric capacity C4, and second pole of the 24th transistor T24 connects the 5th node e, and the grid of the 24th transistor T24 connects three node c；

First pole of the 25th transistor T25 connects second pole of the 4th signal output part Output4, the 25th transistor T25 and connects fourth node d, and the grid of the 25th transistor T25 connects three node c；

Second pole of the 4th electric capacity C4 connects the 4th signal output part Output4.

Described output control module 18 includes: the 26th transistor T26；

First pole of described 26th transistor T26 connects described 4th signal output part Output4, second pole of described 26th transistor T26 connects the grid of described second electrical level end V2, described 26th transistor T26 and connects described first scanning signal end S1.

Yet another embodiment of the invention provides the driving method of a kind of shift register cell, the shift register cell that this driving method provides for driving any of the above-described embodiment.Concrete, with reference to shown in Fig. 3, the volume driving method of this shift register cell comprises the steps:

S31, first stage, first controls module inputs primary nodal point by the voltage of the first signal input part under the control of the first scan signal scanning signal end；The voltage of secondary signal input is inputted secondary nodal point by input module under the control of the voltage of primary nodal point；The voltage of second electrical level end is exported at signal output part by output control module under the control of the first scan signal scanning signal end.

S32, second stage, first controls module inputs primary nodal point by the voltage of secondary signal input under the control of the second the second scanning signal scanning signal end；The voltage of secondary signal input is inputted secondary nodal point by input module under the control of the voltage of primary nodal point；First clock signal of the first clock signal terminal is exported at the first signal output part by the first output module under the control of the voltage of secondary nodal point.

S33, phase III, first controls module inputs primary nodal point by the voltage of secondary signal input under the control of the second the second scanning signal scanning signal end；The voltage of secondary signal input is inputted secondary nodal point by input module under the control of the voltage of primary nodal point；The second clock signal of second clock signal end is exported at secondary signal outfan by the second output module under the control of the voltage of secondary nodal point.

S34, fourth stage, first controls module inputs primary nodal point by the voltage of secondary signal input under the control of the second the second scanning signal scanning signal end；The voltage of secondary signal input is inputted secondary nodal point by input module under the control of the voltage of primary nodal point；3rd clock signal of the 3rd clock signal terminal is exported at the 3rd signal output part by the 3rd output module under the control of the voltage of secondary nodal point.

S35, the 5th stage, first controls module inputs primary nodal point by the voltage of secondary signal input under the control of the second the second scanning signal scanning signal end；The voltage of secondary signal input is inputted secondary nodal point by input module under the control of the voltage of primary nodal point；4th clock signal of the 4th clock signal terminal is exported at the 4th signal output part by the 4th output module under the control of the voltage of secondary nodal point.

S36, the 6th stage, second controls module inputs the voltage of the first level terminal the 3rd node under the second control scanning signal and under the control of the voltage of the 3rd node, the voltage of second electrical level end is inputted primary nodal point, secondary nodal point, fourth node and the 5th node；First output module, the second output module, the 3rd output module and the 4th output module export the voltage of fourth node respectively under the control of the voltage of the 3rd node at the first signal output part, secondary signal outfan, the 3rd signal output part and the 4th signal output part.

S37, the 7th stage, control module and under the control of primary nodal point, the voltage of the first level terminal is inputted the 3rd node and under the control of the voltage of the 3rd node, the voltage of second electrical level end is inputted primary nodal point, secondary nodal point, fourth node and the 5th node.

nullThe voltage of the first signal input part is inputted primary nodal point in the first stage by the shift register cell driving method that the embodiment of the present invention provides、The voltage of secondary signal input is inputted secondary nodal point and the voltage of second electrical level end is exported at the 4th signal output part，Second stage to the 5th stage is divided the first clock signal of the first clock signal terminal、The second clock signal of second clock signal end、3rd clock signal of the 3rd clock signal terminal and the 4th clock signal of the 4th clock signal terminal are at the first signal output part、Secondary signal outfan、3rd signal output part and the output of the 4th signal output part，In the 6th stage, the voltage of second electrical level end is exported primary nodal point、Secondary nodal point、Fourth node and the 5th node and at the first signal output part、Secondary signal outfan、The voltage of the 3rd signal output part and the 4th signal output part output fourth node，So the shift register cell driving method that the embodiment of the present invention provides can drive the gate driver circuit output gate drive signal in above-described embodiment，And the embodiment of the present invention shares the first control module by four signal output module、Input module and second controls module，Thus gate drive signal can be provided to a grid line respectively，Compared in prior art between each shift register cell without common part and only provide gate drive signal to grid line，The shift register cell that the embodiment of the present invention provides shares the first control module by four signal output module、Input module and second controls module，Thus gate drive signal can be provided to a grid line respectively，Be equivalent to public for the partial function in level Four shift register cell，So the embodiment of the present invention can reduce the device in shift register cell，And then simplification gate driver circuit.

Below, with reference to the time sequence status schematic diagram shown in Fig. 4, the operation principle of the shift register cell shown in Fig. 2 and the driving method of shift register cell shown in Fig. 3 is illustrated, wherein, high level VGH is provided with the first level terminal V1, second electrical level end V2 provides low level VGL, and in shift register cell shown in Fig. 2, during all transistors equal grid high level, the N-type transistor of conducting is that example illustrates.Exemplary, second electrical level end V2 can be earth terminal.It can further be stated that, during the N-type transistor turned on when the equal grid high level of transistors all in shift register cell shown in Fig. 2,4th transistor T4, the tenth transistor T10, the 14th transistor T14, the 18th transistor T18 and the 20th two-transistor T22 grid are connected with the first level terminal V1 providing high level all the time, so the tenth transistor T10, the 14th transistor T14, the 18th transistor T18 and the 20th two-transistor T22 are normally on transistors.

Fig. 4 having illustrated, first clock signal of the first clock signal terminal CLK1, the second clock signal of second clock signal end CLK2, the 3rd clock signal of the 3rd clock signal terminal CLK3, the 4th clock signal of the 4th clock signal terminal CLK4, the input signal of the first signal input part Input1, the input signal of secondary signal input Input2, the scan signal of the first scanning signal end S1 and the second of the second scanning signal end scan the sequential chart of signal.Wherein the cycle of the first clock signal, second clock signal, the 3rd clock signal and the 4th clock signal is 4T, and dutycycle is 25%.The cycle of the input signal of the first signal input part Input1 and the input signal of secondary signal input Input2 is 8T, dutycycle is 5/8, the initial time of the input signal output high level that the initial time of the input signal high level of the first signal input part Input1 shifts to an earlier date 5T, secondary signal input Input2 than the initial time of CLK1 output high level shifts to an earlier date T than the CLK1 initial time exporting high level.Scan signal and the second scanning signal illustrate that the time of high level is 5T, and the initial time of scan signal output high level shifts to an earlier date 5T than the CLK1 initial time exporting high level, the initial time of the second scanning signal output high level is identical with the initial time that CLK1 exports high level, wherein the cycle of scan signal and the second scanning signal can be determined according to the rate of scanning of the display surface gate driver circuit including this shift register cell, exemplary, rate of scanning is 60HZ, then the cycle of scan signal and the second scanning signal is 16.67ms.As shown in Figure 4, it is provided that the time sequence status in seven stages, wherein, the first stage is t1；Second stage is t2；Phase III is t3；Fourth stage is t4；5th stage was t5；6th stage was t6；7th stage was t7.

The t1 stage, Input1 high level, the first transistor T1, the 26th transistor T26 conducting, and because S1 high level, therefore primary nodal point a level is driven high, grid turns on the primary nodal point a third transistor T3 being connected and the 5th transistor T5.Because T5 turns on, so the 3rd node c connects second electrical level end V2, the 3rd node c low level by T5.Because T3 conducting and Input2 high level, so Input2 is charged to the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3 and the 4th electric capacity C4 by third transistor T3 simultaneously, T11, T15, T19, T23 turn on, but because CLK1, CLK2, CLK3 are low level in this stage, so the first output module, the second output module and the 3rd output module all export low voltage level in this stage.Again because T26 turns on, so Output output point point is put down.This stage is that the first electric capacity C1, the second electric capacity C2, the 3rd electric capacity C3 and the 4th electric capacity C4 are charged, and therefore the t1 stage is called pre-charging stage.

In the t2 stage, in this stage, Input1 and S1 is low level, and T1 ends, Input2 and S2 is high level, therefore T2 conducting, and Input2 draws high the voltage of primary nodal point a by T2, T3, T5 turn on, and Input2 draws high the voltage of secondary nodal point b by T3, and T11 still turns on.Again because this node CLK1 starts to export high level, so the t2 stage, Output1 exports high level.Additionally, the high level of Output1 output acts on second pole of the first electric capacity C1, so bootstrap effect, the voltage of lifting the first electric capacity C1 the first pole occur the first electric capacity C1, and then make T11 conducting output signal more abundant, Output1 more stable.CLK2, CLK3, CLK4 are low level, so the equal output low level of Output2, Output3, Output4.This rank first output module 14 exports, and therefore the t2 stage was called for the first output stage.

In the t3 stage, in this stage, each signal condition is similar with the t2 stage, is different in that CLK1 is become low level from the high level in t2 stage, and CLK2 is become high level from the low level in t2 stage, and therefore Output2 exports high level.Equally, the high level of Output2 output acts on second pole of the second electric capacity C2, so bootstrap effect, the voltage of lifting the second electric capacity C2 the first pole occur the second electric capacity C2, and then makes T15 conducting output signal more abundant, Output2 more stable.CLK1, CLK3, CLK4 are low level, so the equal output low level of Output1, Output3, Output4.This stage second output module 15 exports, and therefore the t3 stage was called for the second output stage.

In the t4 stage, in this stage, each signal condition is similar with the t3 stage, is different in that CLK2 is become low level from the high level in t3 stage, and CLK3 is become high level from the low level in t3 stage, and therefore Output3 exports high level.Equally, the high level of Output3 output acts on second pole of the 3rd electric capacity C3, so bootstrap effect, the voltage of lifting the 3rd electric capacity C3 the first pole occur the 3rd electric capacity C3, and then makes T19 conducting output signal more abundant, Output3 more stable.CLK1, CLK2, CLK4 are low level, so the equal output low level of Output1, Output2, Output4.This stage the 3rd output module 16 exports, and therefore the t4 stage was called for the 3rd output stage.

In the t5 stage, in this stage, each signal condition is similar with the t4 stage, is different in that CLK3 is become low level from the high level in t4 stage, and CLK4 is become high level from the low level in t4 stage, and therefore Output4 exports high level.Equally, the high level of Output4 output acts on second pole of the 4th electric capacity C4, so bootstrap effect, the voltage of lifting the 4th electric capacity C4 the first pole occur the 4th electric capacity C4, and then makes T23 conducting output signal more abundant, Output4 more stable.CLK1, CLK2, CLK3 are low level, so the equal output low level of Output1, Output2, Output3.This stage the 4th output module 16 exports, and therefore the t5 stage was called for the 4th output stage.

In the t6 stage, this stage S2 high level, so T2 conducting, Input2 low level, primary nodal point a is drawn as low level, T3, T5 cut-off by Input2 by T2.Because T5 ends, so the 3rd node c is drawn as high level, T6, T7, T8, T9, T12, T13, T16, T17, T20, T21, T24 and T25 conducting by V1 by T4.V2 connects the 5th node e, the 5th node e low level by T8, and V2 connects fourth node d, fourth node d low level by T9.First pole of the first electric capacity C1 connects the 5th node e by T12, and the first electric capacity C1 is discharged, and Output1 connects fourth node d, Ouput1 by T13 and is discharged output low level.In like manner, first pole of C2 connects the 5th node e, C2 by T16 and is discharged, and Output2 connects fourth node d, Ouput2 by T13 and is discharged, output low level；First pole of C3 connects the 5th node e, C3 by T20 and is discharged, and Output3 connects fourth node d, Ouput3 by T21 and is discharged, output low level；First pole of C4 connects the 5th node e, C4 by T24 and is discharged, and Output4 connects fourth node d, Ouput4 by T25 and is discharged, output low level.Each outfan is discharged by this stage, and therefore the t6 stage is called discharge regime.

The t7 stage, S1, S2 are level, therefore V1 draws high the voltage of the 3rd node c by T4, and C1, C2, C3, C4, Output1, Output2, Output3, Output4 continue electric discharge, the equal output low level of Output1, Output2, Output3, Output4.Each outfan is still discharged by this stage, and therefore the t7 stage is called the stabilization sub stage.

It should be noted that, above-mentioned shift register cell potentially includes some stages after the t7 stage, this is to be determined by the cycle of scan signal and the second scanning signal, but at S1 before secondary output high level, the 3rd node c in shift register cell keeps the equal output low level of high level Output1, Output2, Output3, Output4

Further, in shift register cell in above-described embodiment, all transistors can also be the P-type transistor of low level conducting, if all transistors are P-type transistor, then have only to readjust the time sequence status of each input signal of shift register cell, such as: adjust the first level terminal V1 and low level is provided, adjusting t1-t5 stage Input2 in Fig. 4 and be adjusted to low level, adjusting t6-t7 stage Input2 is high level, and other signals are also adjusted to the clock signal of opposite in phase.

Further, above-mentioned shift register cell can also adopt N-type transistor and P-type transistor simultaneously, now need to ensure shift register cell needs to adopt identical type by same clock signal or voltage-controlled transistor, certainly this is all the reasonable work-around solution that those skilled in the art can make according to embodiments of the invention, therefore all should be protection scope of the present invention, but consider the making technology of transistor, owing to the active layer dopant material of different types of transistor differs, therefore shift register cell adopt the transistor of uniform type to be more beneficial for the making technology of shift register cell.

One embodiment of the invention provides a kind of gate driver circuit, including the shift register cell at least one above-described embodiment.

Concrete, with reference to shown in Fig. 5, this gate driver circuit includes the shift register cell of several cascades, wherein, first signal output part Output1 of the 1st grade of shift register cell connects grid line G1, the secondary signal outfan Output2 of the 1st grade of shift register cell connects grid line G2, and the 3rd signal output part Output3 of the 1st grade of shift register cell connects grid line G3, and the 4th signal output part Output4 of the 1st grade of shift register cell connects grid line G4；First signal output part Output1 of the 2nd grade of shift register cell connects grid line G5, the secondary signal outfan Output2 of the 2nd grade of shift register cell connects grid line G6,3rd signal output part Output3 of the 2nd grade of shift register cell connects grid line G7, and the 4th signal output part Output4 of the 2nd grade of shift register cell connects grid line G8；First signal output part Output1 of n-th grade of shift register cell connects grid line G4n-3, the secondary signal outfan Output2 of n-th grade of shift register cell connects grid line G4n-2,3rd signal output part Output3 of n-th grade of shift register cell connects grid line G4n-1, and the 4th signal output part Output4 of n-th grade of shift register cell connects grid line G4n.

Additionally, each shift register cell has a first clock signal terminal CLK1, second clock signal end CLK2, a 3rd clock signal terminal CLK3, a 4th clock signal terminal CLK4 and two signal input parts；With reference to shown in Fig. 5, four clock signal terminals connected to each shift register cell by the clock signal clock1 of four systems, clock2, clock3 and clock4 provide clock signal, the CLK1 of each of which level shift register cell inputs clock1, CLK2 inputs clock2, CLK3 inputs clock3, CLK4 and inputs clock4.Input signal INPUT1 and INPUT2 by two and provide input signal to the first signal input part Input1 and Input2 that each shift register cell connects；Wherein, the first signal input part Input1 of the 1st grade of shift register cell inputs INPUT1, the secondary signal input Input2 of the 1st grade of shift register cell inputs INPUT2；First signal input part Input1 of the 2nd grade of shift register cell inputs INPUT2, the secondary signal input Input2 of the 2nd grade of shift register cell inputs INPUT1；For n-th grade of shift register cell, when n is odd number, each signal input part of n-th grade of shift register cell inputs the input signal identical with each signal input part input of the 1st grade of shift register cell；When n is even number, each signal input part of n-th grade of shift register cell inputs the clock signal identical with each signal input part input of the 2nd grade of shift register cell；Fig. 5 illustrates for n for odd number.

Wherein, the time sequence status of system clock is with reference to the 4th clock signal of first clock signal of the first clock signal terminal CLK1, the second clock signal of second clock signal end CLK2, the 3rd clock signal of the 3rd clock signal terminal CLK3, the 4th clock signal terminal CLK4 in Fig. 4；Wherein, clock1, clock2, clock3, clock4 phase place differs 1/4 clock cycle successively, and clock1, clock2, clock3, clock4 are the clock signal that dutycycle is 25%.

Further, every one-level shift register cell also includes two level terminal and two scanning signal ends, wherein, first level terminal of each shift register cell can pass through same level terminal provides voltage, an independent level terminal can also be used respectively, the second electrical level end of each shift register cell same can pass through same level terminal provides voltage, it is also possible to use an independent level terminal respectively, does not share scanning signal end between each shift register cell.

Yet another embodiment of the invention provides a kind of display device, including any one gate driver circuit in above-described embodiment.

It addition, display device can be: any product with display function or parts such as Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, DPF, navigators.

The above; being only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, any those familiar with the art is in the technical scope that the invention discloses; the change that can readily occur in or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with scope of the claims.

Claims

1. a shift register cell, it is characterised in that including: first controls module, input module, the second control module, the first output module, the second output module, the 3rd output module, the 4th output module and output control module；

2. shift register cell according to claim 1, it is characterised in that described first controls module includes: the first transistor and transistor seconds；

3. shift register cell according to claim 1, it is characterised in that described input module includes: third transistor；

4. shift register cell according to claim 1, it is characterised in that described second controls module includes: the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor, the 8th transistor and the 9th transistor；

5. shift register cell according to claim 1, it is characterised in that described first output module includes: the tenth transistor, the 11st transistor, the tenth two-transistor, the 13rd transistor and the first electric capacity；

6. shift register cell according to claim 1, it is characterised in that described second output module includes: the 14th transistor, the 15th transistor, the 16th transistor, the 17th transistor and the second electric capacity；

7. shift register cell according to claim 1, it is characterised in that described 3rd output module includes: the 18th transistor, the 19th transistor, the 20th transistor, the 21st transistor and the 3rd electric capacity；

8. shift register cell according to claim 1, it is characterised in that described 4th output module includes: the 20th two-transistor, the 23rd transistor, the 24th transistor, the 25th transistor and the 4th electric capacity；

9. shift register cell according to claim 1, it is characterised in that described output control module includes: the 26th transistor；

10. the shift register cell according to any one of claim 1-9, it is characterized in that, first clock signal of described first clock signal terminal, the second clock signal of described second clock signal end, described 3rd clock signal of the 3rd clock signal terminal and the 4th clock signal of described 4th clock signal terminal differ 1/4 clock cycle successively, and the first clock signal of described first clock signal terminal, the second clock signal of described second clock signal end, the dutycycle of the 3rd clock signal of described 3rd clock signal terminal and the 4th clock signal of described 4th clock signal terminal is 25%.

11. according to the shift register cell described in any one of claim 2-9, it is characterised in that each transistor is N-type transistor；Or each transistor is P-type transistor.

12. the driving method of a shift register cell, it is characterised in that for driving the shift register cell described in any one of claim 1-11；Described method includes:

In 5th stage, first controls module inputs primary nodal point by the voltage of secondary signal input under the control of the second the second scanning signal scanning signal end；The voltage of secondary signal input is inputted secondary nodal point by input module under the control of the voltage of primary nodal point；4th clock signal of the 4th clock signal terminal is exported at the 4th signal output part by the 4th output module under the control of the voltage of secondary nodal point；

In 6th stage, second controls module inputs the voltage of the first level terminal the 3rd node under the second control scanning signal and under the control of the voltage of the 3rd node, the voltage of second electrical level end is inputted primary nodal point, secondary nodal point, fourth node and the 5th node；First output module, the second output module, the 3rd output module and the 4th output module export the voltage of fourth node respectively under the control of the voltage of the 3rd node at the first signal output part, secondary signal outfan, the 3rd signal output part and the 4th signal output part；

13. a gate driver circuit, it is characterised in that include at least one shift register cell described in any one of claim 1-11.

14. a display device, it is characterised in that include the gate driver circuit described in claim 13.