CN105787164A - Debugging method and system for programmable logic device - Google Patents
Debugging method and system for programmable logic device Download PDFInfo
- Publication number
- CN105787164A CN105787164A CN201610095331.7A CN201610095331A CN105787164A CN 105787164 A CN105787164 A CN 105787164A CN 201610095331 A CN201610095331 A CN 201610095331A CN 105787164 A CN105787164 A CN 105787164A
- Authority
- CN
- China
- Prior art keywords
- core
- pld
- logic analyser
- enhanced logic
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000013461 design Methods 0.000 claims abstract description 75
- 230000008569 process Effects 0.000 claims abstract description 17
- 238000001514 detection method Methods 0.000 claims description 6
- 238000012360 testing method Methods 0.000 abstract description 8
- 238000005070 sampling Methods 0.000 abstract description 7
- 108090000553 Phospholipase D Proteins 0.000 description 45
- 230000006870 function Effects 0.000 description 10
- 239000000203 mixture Substances 0.000 description 7
- 238000011161 development Methods 0.000 description 5
- 102100032967 Phospholipase D1 Human genes 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 108010002266 phospholipase D1 Proteins 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000013481 data capture Methods 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a debugging method and system for a programmable logic device.The method comprises the steps that a client side sets working parameters of an enhanced type logic analyzer core, and compiles the working parameters and design to be detected to comprehensively generate a bitstream file to be sent to a service side; the service side downloads the bitstream file to the programmable logic device; the programmable logic device executes the design to be tested, and the enhanced type logic analyzer core collects and stores data according to the working parameters and sends the data to the service side.The service side stores and processes the data and then sends the data to the client side.By means of the debugging method and system, enhanced type logic analyzer core is embedded into the programmable logic device, data sampling output is carried out on the design to be tested through the enhanced type logic analyzer core, no external logic analyzer or oscilloscope needs to be adopted in the process, testing points do not need to be planned on a circuit board, and pin resources are not occupied.
Description
Technical field
The present invention relates to IC design field, particularly relate to a kind of adjustment method for PLD and system.
Background technology
In FPGA (FieldProgrammableGateArray, field programmable gate array) design process, more than half time can spend in debugging and misarrangement, and the equipment such as logic analyser and oscillograph is most important debugging acid.
In the prior art, when using logic analyser and oscillograph to debug, it is necessary to coupled together by measured signal on probe and circuit board, then resetting logic analyser, the signal that capturing needs carries out observation analysis debugging.This adjustment method, when design and checking VHD FPGA, is difficult to be connected on the circuit board that thin space technique makes, and I/O pin is difficult to draw, it could even be possible to change the state that signal is original, it is difficult to ensure the correctness of signal；Meanwhile, it requires to plan on circuit boards at the very start test point, adds built-in testing pad, socket or adapter etc., it is necessary to is relatively used for the FPGA pin of debugging, had both occupied resource, and inconvenience uses again；Namely existing adjustment method can not meet the debugging demand that FPGA technology development is adjoint.
Therefore, those skilled in the art urgently provide a kind of adjustment method, to solve the problem that existing adjustment method can not meet the adjoint debugging demand of FPGA technology development.
Summary of the invention
The invention provides a kind of adjustment method for PLD and system, to solve the problem that existing adjustment method can not meet the adjoint debugging demand of FPGA technology development.
The invention provides a kind of adjustment method for PLD, it is for the debugging system of PLD, debugging system includes PLD, service end, client and embeds the enhanced logic analyser core of PLD, and adjustment method includes:
Client arranges the running parameter of enhanced logic analyser core, running parameter and design and compilation to be measured is comprehensively generated bit stream file and sends to service end；
Bit stream file is downloaded to PLD by service end；
PLD performs design to be measured, and enhanced logic analyser core is according to running parameter collection and stores data, sends to service end；
After data are carried out storage process by service end, transmission to client is shown.
Further, bit stream file is downloaded to before PLD by service end, also includes: judge that whether PLD is performing other designs, if so, then cache bit stream file, if it is not, then download bit stream file to be downloaded to PLD.
Further, also include: by waveform, client executing shows that at least one mode that sampled signal, list are shown in sampled point, contrast display different bus signal, data exporting processes data.
Further, running parameter includes gathering power-up initializing data, enhanced logic analyser core is according to running parameter collection and stores data and includes: first clock after PLD powers on effectively along time, enhanced logic analyser core starts to capture the power-up initializing instantaneous signal of design to be measured.
Further, debugging system includes at least two and embeds the enhanced logic analyser core of PLD, client generates bit stream file and includes: resolve design to be measured, one or more enhanced logic analyser cores are selected according to detection demand, different identification is distributed for one or more enhanced logic analyser cores, connect the port of design to be measured, the enhanced logic analyser core that gauze is corresponding with designated identification with pin, linking objective clock is to the clock port of enhanced logic analyser core corresponding to designated identification, according to the trigger condition in running parameter, trigger element, sampled point and storage condition carry out inserting core, generate the design netlist including one or more enhanced logic analyser core, design netlist is converted to bit stream file.
Further, enhanced logic analyser core is according to running parameter collection and stores data and includes: according to Samples selecting signal to be sampled, when target clock arrives, trigger element is carried out conditional judgment, if meeting trigger condition, starting to capture data, if meeting storage condition, the data of crawl being stored.
The invention provides a kind of debugging system for PLD, it includes PLD, service end, client and embeds the enhanced logic analyser core of PLD, wherein:
Running parameter and design and compilation to be measured, for arranging the running parameter of enhanced logic analyser core, are comprehensively generated bit stream file and send to service end by client；
Service end is for being downloaded to PLD by bit stream file；
PLD is used for performing design to be measured, and enhanced logic analyser core is according to running parameter collection and stores data, sends to service end；
Service end is for after carrying out storage process to data, and transmission to client is shown.
Further, bit stream file is downloaded to before PLD by service end, is additionally operable to: judge that whether PLD is performing other designs, if so, then cache bit stream file, if it is not, then download bit stream file to be downloaded to PLD.
Further, client is additionally operable to perform to show that at least one mode that sampled signal, list are shown in sampled point, contrast display different bus signal, data exporting processes data by waveform.
Further, running parameter include gather power-up initializing data, enhanced logic analyser core for after PLD powers on first clock effectively along time, enhanced logic analyser core starts to capture the power-up initializing instantaneous signal of design to be measured.
Further, debugging system includes at least two and embeds the enhanced logic analyser core of PLD, client is used for resolving design to be measured, one or more enhanced logic analyser cores are selected according to detection demand, different identification is distributed for one or more enhanced logic analyser cores, connect the port of design to be measured, the enhanced logic analyser core that gauze is corresponding with designated identification with pin, linking objective clock is to the clock port of enhanced logic analyser core corresponding to designated identification, according to the trigger condition in running parameter, trigger element, sampled point and storage condition carry out inserting core, generate the design netlist including one or more enhanced logic analyser core, design netlist is converted to bit stream file.
Further, enhanced logic analyser core is for according to Samples selecting signal to be sampled, when target clock arrives, trigger element being carried out conditional judgment, if meeting trigger condition, starting to capture data, if meeting storage condition, the data of crawl are stored.
Beneficial effects of the present invention:
The invention provides a kind of adjustment method, enhanced logic analyser core is embedded at PLD, check design to be measured by enhanced logic analyser and carry out data sampling output, in this process, by pin etc., external logic analyser and oscillographic pointer need not be connected with the circuit of PLD as existing adjustment method, and then also the operation of PLD would not be impacted, do not require to plan test point on circuit boards yet, testing weld pad, socket or adapter etc., it is not take up pin resource, solve the problem that existing adjustment method can not meet the adjoint debugging demand of FPGA technology development.Further, the running parameter that enhanced logic analyser core can be differently configured, support that multiple enhanced logic analyser core, power-up initializing capture signal, trigger condition configuration is more abundant, it is simple to use.
Accompanying drawing explanation
The structural representation of the debugging system that Fig. 1 provides for first embodiment of the invention；
The flow chart of the adjustment method that Fig. 2 provides for second embodiment of the invention；
Fig. 3 is the structure chart of enhanced logic analyser core in third embodiment of the invention；
Fig. 4 is the fundamental diagram of enhanced logic analyser core in third embodiment of the invention.
Detailed description of the invention
Now in conjunction with the mode of accompanying drawing the present invention exported by detailed description of the invention and further annotate explanation.
First embodiment:
The structural representation of the debugging system that Fig. 1 provides for first embodiment of the invention, as shown in Figure 1, in the present embodiment, debugging system provided by the invention includes: the enhanced logic analyser core DebugCore4 of PLD 1, service end 2, client 3 and embedding PLD 1, wherein:
Running parameter and design and compilation to be measured, for arranging the running parameter of enhanced logic analyser core, are comprehensively generated bit stream file and send to service end 2 by client 3；
Service end 2 for being downloaded to PLD 1 by bit stream file；
PLD 1 is used for performing design to be measured, and enhanced logic analyser core 4 is according to running parameter collection and stores data, sends to service end 2；
Service end 2 is for after carrying out storage process to data, and transmission to client 3 is shown.
In certain embodiments, the service end 2 in above-described embodiment is additionally operable to before bit stream file is downloaded to PLD: judge whether PLD is performing other designs, if, then cache bit stream file, if it is not, then download bit stream file to be downloaded to PLD.
In certain embodiments, the client 3 in above-described embodiment is additionally operable to perform to show that at least one mode that sampled signal, list are shown in sampled point, contrast display different bus signal, data exporting processes data by waveform.
In certain embodiments, running parameter in above-described embodiment includes gathering power-up initializing data, enhanced logic analyser core 4 for first clock after PLD powers on effectively along time, enhanced logic analyser core starts to capture the power-up initializing instantaneous signal of design to be measured.
In certain embodiments, debugging system in above-described embodiment includes at least two and embeds the enhanced logic analyser core 4 of PLD, client 3 is used for resolving design to be measured, one or more enhanced logic analyser cores are selected according to detection demand, different identification is distributed for one or more enhanced logic analyser cores, connect the port of design to be measured, the enhanced logic analyser core that gauze is corresponding with designated identification with pin, linking objective clock is to the clock port of enhanced logic analyser core corresponding to designated identification, according to the trigger condition in running parameter, trigger element, sampled point and storage condition carry out inserting core, generate the design netlist including one or more enhanced logic analyser core, design netlist is converted to bit stream file.In actual applications, multiple enhanced logic analyser cores 4 can be evenly distributed in PLD, it is also possible to debugging demand according to reality, concentrated setting is in subregion.
In certain embodiments, enhanced logic analyser core 4 in above-described embodiment is for according to Samples selecting signal to be sampled, when target clock arrives, trigger element is carried out conditional judgment, if meeting trigger condition, starting to capture data, if meeting storage condition, the data of crawl being stored.
Second embodiment:
The flow chart of the adjustment method that Fig. 2 provides for second embodiment of the invention, as shown in Figure 2, in the present embodiment, adjustment method provided by the invention includes:
S201: client arranges the running parameter of enhanced logic analyser core, comprehensively generates bit stream file by running parameter and design and compilation to be measured and sends to service end；
S202: bit stream file is downloaded to PLD by service end；
S203: PLD performs design to be measured, and enhanced logic analyser core is according to running parameter collection and stores data, sends to service end；
S204: after data are carried out storage process by service end, transmission to client is shown.
In certain embodiments, the method in above-described embodiment, before bit stream file is downloaded to PLD by service end, also includes: judge whether PLD is performing other designs, if, then cache bit stream file, if it is not, then download bit stream file to be downloaded to PLD.
In certain embodiments, the method in above-described embodiment also includes: by waveform, client executing shows that at least one mode that sampled signal, list are shown in sampled point, contrast display different bus signal, data exporting processes data.
In certain embodiments, running parameter in above-described embodiment includes gathering power-up initializing data, enhanced logic analyser core is according to running parameter collection and stores data and includes: first clock after PLD powers on effectively along time, enhanced logic analyser core starts to capture the power-up initializing instantaneous signal of design to be measured.
In certain embodiments, debugging system in above-described embodiment includes at least two and embeds the enhanced logic analyser core of PLD, client generates bit stream file and includes: resolve design to be measured, one or more enhanced logic analyser cores are selected according to detection demand, different identification is distributed for one or more enhanced logic analyser cores, connect the port of design to be measured, the enhanced logic analyser core that gauze is corresponding with designated identification with pin, linking objective clock is to the clock port of enhanced logic analyser core corresponding to designated identification, according to the trigger condition in running parameter, trigger element, sampled point and storage condition carry out inserting core, generate the design netlist including one or more enhanced logic analyser core, design netlist is converted to bit stream file.
In certain embodiments, enhanced logic analyser core in above-described embodiment is according to running parameter collection and stores data and includes: according to Samples selecting signal to be sampled, when target clock arrives, trigger element is carried out conditional judgment, if meeting trigger condition, starting to capture data, if meeting storage condition, the data of crawl being stored.
In conjunction with concrete application scenarios the present invention done and further annotate explanation.
3rd embodiment:
Present embodiments provide a kind of based on PLD (programmablelogicdevice, PLD) the embedded logic analyser of enhancement mode, by inserting one or more logic analyser core in FPGA design, user can easily access the internal all signals of FPGA device and node (including port, gauze and pin)；By arranging trigger condition, the signal that needs are observed triggers, data acquisition, storage, and shows observation in client；In order to solve in prior art the problem to VHD FPGA inconvenient debugging, this embedded enhanced logic analyser possesses support multiple DebugCore (enhanced logic analyser core) Simultaneous Sampling Data, capture signal during power-up initializing, the configuration of trigger condition is more enriched, is used the features such as simple, and has powerful data analysis by client and represent function.
In actual use, embedded logic analyzer uses the one or more DebugCore being embedded in FPGA design, designer arranges trigger condition in client, by JTAG (JointTestActionGroup, joint test working group) the interface accessing FPGA that service end is connected with FPGA.Once the soft core of logic analyser captures data, information being returned by jtag interface, then these data are observed by designer, it is possible to observe hundreds and thousands of signals easily.
As shown in Figure 1, client 3 (can be Debugger visual logic analyser) initiates request to service end 2 (can be distance host JTAGServer), after service end 2 receives the request of client 3, judge whether FPGA1 is processing the request of other clients or other requests of this client, if FPGA1 is currently without processing any request, then request is issued in FPGA1 hardware, otherwise waits for.The data that FPGA hardware to capture correspondence according to request are sent to service end 2, and service end 2 carries out locally stored, and after process, data are transmitted to client 3, and data are shown by client 3.
Utilize client 3 to complete user's design netlist and specific DebugCore to insert core, after generating bit stream file, bit stream file is downloaded in fpga chip and run.FPGA will need the data caught to be stored in RAM (randomaccessmemory random access memory), and according to specific format, storage data are sent to service end.
DebugCore captures signal demand clock, may want to be captured by different clock frequencies for different signals.Therefore, need to support multiple DebugCore, slotting core module in client completes multiple independent DebugCore and is inserted in user's design, and distribute different ID according to insertion sequence to DebugCore, then bit stream is generated, and distinguish different DebugCore by ID in FPGA, thus realize the function of multinuclear debugging.
In FPGA design, after just powering on, the data of user's design would be likely to occur time very short labile state, and this state affects very big in practice, therefore, it is possible to obtain just power on after user's design critically important in the service data of FPGA.The present invention inserts DebugCore in user designs, and can enable the crawl of power-up initializing data and the setting of condition, it is achieved observe user's design service data in FPGA after just powering on.
Concrete, the debugging system that the present embodiment provides is broadly divided into hardware components and software section: hardware components is made up of design to be measured (DUT), the DebugCore being embedded in FPGA, ram memory cell and jtag interface；Software section is made up of user's design software and the on-line debugging software ELA (enhanced logic analyser) being integrated in, and the operation principle of ELA is: arrange parameters such as needing the signal of monitoring, Trigger Logic, sampling depth and clock signal in ELA on-line debugging software；Download in FPGA together with after comprehensive to the ELA file set and user's design and compilation；Running ELA, if meeting trigger condition, measured signal is just sampled by ELA at the rising edge of clock, and is stored in ram memory cell；When data of having sampled, can upload the data in PC by jtag interface and carry out on-line debugging.
nullDebugCore designs structured flowchart as shown in Figure 3，Inside core, each triggering port is connected to corresponding TriggerUnit (trigger element) 31，Each Clock clock signal arrives，Each TriggerUnit31 carries out conditional judgment，Again the result of different TriggerUnit31 is carried out boolean combination or sequential combination，If meeting TriggerCondition (trigger condition) 32，Then start to capture data by DataCaptureControl (data capture controller) 33，If meeting StorageCondition (storage condition) 34，Then carry out data storage by DataCaptureMemory (data storage controller) 35.
The basic functional principle of DebugCore, as shown in Figure 4, the basic comprising modules of DebugCore has DataRegister36, TriggerPort37 and TriggerCondition32.DataRegister36 is the combination that user selects for the some signalling channels observed, and at most has 4096 signals.TriggerPort37 is the combination of the input signal of one group of identity function, and it comprises several TriggerUnit31 for arranging trigger condition, needs according to user and determines.TriggerUnit31 selects some bars from same TriggerPort37, is combined into trigger element, is used for arranging certain specific trigger condition.And TriggerCondition32 is Boolean expression or the sequence of one or more TriggerUnit composition, it is used for instructing the seizure of DebugCore data.
When debugging, user needs TriggerUnit31 is configured, and the configuration of TriggerUnit31 arranges trigger condition exactly.In each TriggerUnit31 being input in this TriggerPort36 that data on node that the channel C hannels of TriggerPort36 can connect are real-time, check whether the value of this group node meets the trigger condition arranged in TriggerUnit31；By with or, the logical relation of non-logical relation or sequence trigger switch, multiple TriggerUnit31 can be combined into a TriggerCondition32, only when the TriggerCondition32 trigger condition arranged is satisfied, just can trigger data catch, data capture action by the digital independent on the Channels of the DataRegister36 node connected to DataRegister36, can then pass through Software on Drawing and become waveform to show user.
Slotting core step involved by the present embodiment includes: user selects design netlist file user.vm at slotting core display module, by resolving user.vm, port (Port), gauze (Net) and pin (Pin) is displayed.User can select Port, Net and Pin to be seen, and configuration parameter (trigger condition, trigger element, sampled point, storage condition etc.) carrys out the DebugCore that instantiation is specified on display module, and generate core.v, use the comprehensive core.v of SynplifyPro to generate intermediate file core.vm.Finally use user.vm as top layer module, call core.vm and generate a user_ic.vm, complete to insert kernel function.
The adjustment method that the present embodiment provides possesses advantages below:
A, supporting the function of many ELA core, namely by inserting core module, be inserted simultaneously into multiple DebugCore, this function includes:
First, by inserting core module, user design is resolved in Debugger client, and generate multiple DebugCore as required, these DebugCore are independent of one another, by application assigned difference ID, from integer 1, are incremented by gradually, maximum support 16.
Second, connect the net to the DebugCore specified in user design, and linking objective clock is to the clock port of DebugCore, then configuration parameter (trigger condition, trigger element, sampled point, storage condition etc.) carries out inserting core, ultimately produces the design netlist comprising multinuclear.
3rd, design netlist is generated bit stream file, then downloads in FPGA.In the control system of FPGA, it is connected with multiple DebugCore by Hub (a kind of bridge), by the ID of DebugCore, it is achieved the operation to the DebugCore specified.
4th, DebugCore captures signal according to the trigger condition set, and is stored in RAM, and is sent to service end, and service end is sent signal to by TCPSocket and shows in client.
B, power-up initializing data sampling, after namely FPGA powers on, first time meets the data of crawl during initial trigger condition, and this function includes:
First, when inserting core, configurable enable captures power-up initializing data, and the trigger condition of user is configured in the netlist after slotting core.
Second, after using slotting core, netlist generates bit stream, download in FPGA, when a clock is effectively along arriving after powering on, user's design brings into operation, and DebugCore starts to capture the signal in user's design simultaneously, when user configured trigger condition meets, FPGA starts to capture data according to sampling depth, is stored in RAM.
3rd, user can pass through the acquisition power-up initializing function on interface, collection data is transferred to the display observation of PC end, understands form and the stability of power-up initializing twinkling signal.
C, configuration trigger condition, it is provided that configurable trigger condition abundanter, trigger condition be one or more trigger element composition Boolean expression or sequence trigger switch sequence, be used for instruct debugging Nuclear Data seizure.Trigger condition can be the AOI logical combination of multiple trigger element, and sequence trigger switch sequence is, after the order all conditions according to configuration meets successively, just to enable triggering.As shown in Figure 4, each Triggerport can configure multiple TriggerUnit, TriggerUnit can capture the value (0 arranging each Channel corresponding in TriggerPort, 1, arbitrary value, rising edge, trailing edge), each TriggerPort can configure 16 TriggerUnit.The Boolean expression of one or more TriggerUnit composition or sequence, so one TriggerCondition of composition, be used for instructing the seizure of DebugCore data.The Boolean expression of one or more TriggerUnit composition or sequence, so one StorageCondition of composition, be used for instructing the storage of DebugCore data.
D, client data show and preserve, compared with existing oscillographic data display mode, interface function is more powerful, it is possible to display channel and bus signals intuitively；Providing a patterned interface in order to configure DebugCore, it can configure DebugCore in real time without recompiling design, easy to use.Including: waveform shows, for waveshape signal display interface, it is possible to signal is stretched, pulls and combination in any, simple and clear；Table data shows, and can be illustrated on interface by sampled point by list, represents single Channel and bus signals with data value form；Bus data shows, it is possible to contrasted by different bus intuitively, observes bus signals over time, and the multi-form combination in any of point, line presents in a different view；Data exporting function, the information such as the information revised such as signal name, bus composition can be preserved by user, in order to imports next time and uses.
In summary, by the enforcement of the present invention, at least there is following beneficial effect:
The invention provides a kind of adjustment method, enhanced logic analyser core is embedded at PLD, check design to be measured by enhanced logic analyser and carry out data sampling output, in this process, by pin etc., external logic analyser and oscillographic pointer need not be connected with the circuit of PLD as existing adjustment method, and then also the operation of PLD would not be impacted, do not require to plan test point on circuit boards yet, testing weld pad, socket or adapter etc., it is not take up pin resource, solve the problem that existing adjustment method can not meet the adjoint debugging demand of FPGA technology development.
Further, the running parameter that enhanced logic analyser core can be differently configured, support that multiple enhanced logic analyser core, power-up initializing capture signal, trigger condition configuration is more abundant, it is simple to use.
Below it is only the specific embodiment of the present invention; not the present invention is done any pro forma restriction; every any simple modification, equivalent variations, combination or modification embodiment of above done according to the technical spirit of the present invention, all still falls within the protection domain of technical solution of the present invention.
Claims (12)
1. the adjustment method for PLD, it is characterized in that, debugging system for PLD, described debugging system includes PLD, service end, client and embeds the enhanced logic analyser core of described PLD, and described adjustment method includes:
Described client arranges the running parameter of described enhanced logic analyser core, described running parameter and design and compilation to be measured is comprehensively generated bit stream file and sends to described service end；
Described bit stream file is downloaded to described PLD by described service end；
Described PLD performs described design to be measured, and described enhanced logic analyser core according to described running parameter collection and stores data, sends to described service end；
After described data are carried out storage process by described service end, send extremely described client and be shown.
2. adjustment method as claimed in claim 1, it is characterized in that, described bit stream file is downloaded to before described PLD by described service end, also include: judge whether described PLD is performing other designs, if, then bit stream file described in buffer memory, if it is not, then download described bit stream file to be downloaded to described PLD.
3. adjustment method as claimed in claim 1, it is characterised in that also include: by waveform, described client executing shows that at least one mode that sampled signal, list are shown in sampled point, contrast display different bus signal, data exporting processes data.
4. adjustment method as claimed in claim 1, it is characterized in that, described running parameter includes gathering power-up initializing data, described enhanced logic analyser core is according to described running parameter collection and stores data and includes: first clock after described PLD powers on effectively along time, described enhanced logic analyser core starts to capture the power-up initializing instantaneous signal of described design to be measured.
null5. the adjustment method as described in any one of Claims 1-4，It is characterized in that，Described debugging system includes at least two and embeds the enhanced logic analyser core of described PLD，Described client generates bit stream file and includes: resolve design to be measured，One or more enhanced logic analyser cores are selected according to detection demand，Different identification is distributed for the one or more enhanced logic analyser core，Connect the port of design to be measured、The enhanced logic analyser core that gauze is corresponding with designated identification with pin，Linking objective clock is to the clock port of enhanced logic analyser core corresponding to designated identification，According to the trigger condition in described running parameter、Trigger element、Sampled point and storage condition carry out inserting core，Generate the design netlist including one or more enhanced logic analyser core，Described design netlist is converted to described bit stream file.
6. adjustment method as claimed in claim 5, it is characterized in that, described enhanced logic analyser core is according to described running parameter collection and stores data and includes: according to described Samples selecting signal to be sampled, when described target clock arrives, described trigger element being carried out conditional judgment, if meeting described trigger condition, starting to capture data, if meeting described storage condition, the data of crawl are stored.
7. the debugging system for PLD, it is characterised in that include PLD, service end, client and embed the enhanced logic analyser core of described PLD, wherein:
Described running parameter and design and compilation to be measured, for arranging the running parameter of described enhanced logic analyser core, are comprehensively generated bit stream file and send to described service end by described client；
Described service end is for being downloaded to described PLD by described bit stream file；
Described PLD is used for performing described design to be measured, and described enhanced logic analyser core according to described running parameter collection and stores data, sends to described service end；
Described service end is for, after described data are carried out storage process, sending extremely described client and be shown.
8. debug system as claimed in claim 7, it is characterized in that, described bit stream file is downloaded to before described PLD by described service end, it is additionally operable to: judge whether described PLD is performing other designs, if, then bit stream file described in buffer memory, if it is not, then download described bit stream file to be downloaded to described PLD.
9. debug system as claimed in claim 7, it is characterised in that described client is additionally operable to perform to show that at least one mode that sampled signal, list are shown in sampled point, contrast display different bus signal, data exporting processes data by waveform.
10. debug system as claimed in claim 7, it is characterized in that, described running parameter includes gathering power-up initializing data, described enhanced logic analyser core for after described PLD powers on first clock effectively along time, described enhanced logic analyser core starts to capture the power-up initializing instantaneous signal of described design to be measured.
null11. the debugging system as described in any one of claim 7 to 10，It is characterized in that，Described debugging system includes at least two and embeds the enhanced logic analyser core of described PLD，Described client is used for resolving design to be measured，One or more enhanced logic analyser cores are selected according to detection demand，Different identification is distributed for the one or more enhanced logic analyser core，Connect the port of design to be measured、The enhanced logic analyser core that gauze is corresponding with designated identification with pin，Linking objective clock is to the clock port of enhanced logic analyser core corresponding to designated identification，According to the trigger condition in described running parameter、Trigger element、Sampled point and storage condition carry out inserting core，Generate the design netlist including one or more enhanced logic analyser core，Described design netlist is converted to described bit stream file.
12. debug system as claimed in claim 11, it is characterized in that, described enhanced logic analyser core is for according to described Samples selecting signal to be sampled, when described target clock arrives, described trigger element being carried out conditional judgment, if meeting described trigger condition, starting to capture data, if meeting described storage condition, the data of crawl are stored.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610095331.7A CN105787164A (en) | 2016-02-19 | 2016-02-19 | Debugging method and system for programmable logic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610095331.7A CN105787164A (en) | 2016-02-19 | 2016-02-19 | Debugging method and system for programmable logic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105787164A true CN105787164A (en) | 2016-07-20 |
Family
ID=56403419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610095331.7A Pending CN105787164A (en) | 2016-02-19 | 2016-02-19 | Debugging method and system for programmable logic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105787164A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109739705A (en) * | 2018-12-29 | 2019-05-10 | 西安智多晶微电子有限公司 | A kind of real-time debugging system of FPGA on piece and method |
| CN109791518A (en) * | 2016-09-28 | 2019-05-21 | 亚马逊科技公司 | Debugging message is extracted from the FPGA in multi-tenant environment |
| CN110597678A (en) * | 2019-09-09 | 2019-12-20 | 腾讯科技（深圳）有限公司 | A debugging method and a debugging unit |
| CN111366841A (en) * | 2020-04-07 | 2020-07-03 | 华北水利水电大学 | A kind of FPGA programmable logic unit testing equipment and using method |
| CN111522330A (en) * | 2020-05-13 | 2020-08-11 | 航天科工防御技术研究试验中心 | FPGA device testing method and system and electronic equipment |
| CN112255534A (en) * | 2020-10-14 | 2021-01-22 | 天津津航计算技术研究所 | IP core module debugging system based on FPGA |
| CN112541313A (en) * | 2020-12-24 | 2021-03-23 | 山东高云半导体科技有限公司 | Method and device for configuring trigger expression for logic analysis state |
| CN112634801A (en) * | 2021-01-08 | 2021-04-09 | 北京集睿致远科技有限公司 | On-chip logic analyzer and chip debugging method |
| CN113341907A (en) * | 2021-04-20 | 2021-09-03 | 深圳市创智成科技股份有限公司 | System and debugging method for universal Debug card |
| CN113407389A (en) * | 2021-05-19 | 2021-09-17 | 无锡中微亿芯有限公司 | FPGA (field programmable Gate array) online debugging method for realizing continuous sampling |
| CN113850042A (en) * | 2021-08-23 | 2021-12-28 | 深圳市紫光同创电子有限公司 | Concurrent debugging method and system based on programmable logic device |
| CN116306429A (en) * | 2023-01-18 | 2023-06-23 | 广东高云半导体科技股份有限公司 | Method, device, computer storage medium and terminal for realizing state data capture |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6510405B1 (en) * | 1998-12-22 | 2003-01-21 | Unisys Corporation | Method and apparatus for selectively displaying signal values generated by a logic simulator |
| CN104536867A (en) * | 2015-01-22 | 2015-04-22 | 浪潮(北京)电子信息产业有限公司 | System and method for debugging multiple field-programmable gate arrays |
| CN105024884A (en) * | 2015-07-28 | 2015-11-04 | 深圳市同创国芯电子有限公司 | System and method for debugging programmable logic device PLD |
-
2016
- 2016-02-19 CN CN201610095331.7A patent/CN105787164A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6510405B1 (en) * | 1998-12-22 | 2003-01-21 | Unisys Corporation | Method and apparatus for selectively displaying signal values generated by a logic simulator |
| CN104536867A (en) * | 2015-01-22 | 2015-04-22 | 浪潮(北京)电子信息产业有限公司 | System and method for debugging multiple field-programmable gate arrays |
| CN105024884A (en) * | 2015-07-28 | 2015-11-04 | 深圳市同创国芯电子有限公司 | System and method for debugging programmable logic device PLD |
Non-Patent Citations (2)
| Title |
|---|
| 宋存杰: "ChipScope Pro实例教程", 《新浪爱问共享资料：CHIPSCOPE PRO实例教程》 * |
| 曾波: "在系统逻辑分析仪的电路设计与实现", 《在系统逻辑分析仪的电路设计与实现》 * |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109791518A (en) * | 2016-09-28 | 2019-05-21 | 亚马逊科技公司 | Debugging message is extracted from the FPGA in multi-tenant environment |
| CN109791518B (en) * | 2016-09-28 | 2022-06-14 | 亚马逊科技公司 | System and method for server computer including configurable logic platform |
| CN109739705A (en) * | 2018-12-29 | 2019-05-10 | 西安智多晶微电子有限公司 | A kind of real-time debugging system of FPGA on piece and method |
| CN110597678B (en) * | 2019-09-09 | 2022-05-31 | 腾讯科技（深圳）有限公司 | A debugging method and debugging unit |
| CN110597678A (en) * | 2019-09-09 | 2019-12-20 | 腾讯科技（深圳）有限公司 | A debugging method and a debugging unit |
| CN111366841A (en) * | 2020-04-07 | 2020-07-03 | 华北水利水电大学 | A kind of FPGA programmable logic unit testing equipment and using method |
| CN111522330A (en) * | 2020-05-13 | 2020-08-11 | 航天科工防御技术研究试验中心 | FPGA device testing method and system and electronic equipment |
| CN112255534A (en) * | 2020-10-14 | 2021-01-22 | 天津津航计算技术研究所 | IP core module debugging system based on FPGA |
| CN112541313B (en) * | 2020-12-24 | 2022-03-11 | 山东高云半导体科技有限公司 | Method and device for configuring trigger expression for logic analysis state |
| CN112541313A (en) * | 2020-12-24 | 2021-03-23 | 山东高云半导体科技有限公司 | Method and device for configuring trigger expression for logic analysis state |
| CN112634801A (en) * | 2021-01-08 | 2021-04-09 | 北京集睿致远科技有限公司 | On-chip logic analyzer and chip debugging method |
| CN112634801B (en) * | 2021-01-08 | 2022-06-10 | 北京集睿致远科技有限公司 | On-chip logic analyzer and chip debugging method |
| CN113341907A (en) * | 2021-04-20 | 2021-09-03 | 深圳市创智成科技股份有限公司 | System and debugging method for universal Debug card |
| CN113341907B (en) * | 2021-04-20 | 2024-04-12 | 深圳市创智成科技股份有限公司 | System and debugging method of general Debug card |
| CN113407389A (en) * | 2021-05-19 | 2021-09-17 | 无锡中微亿芯有限公司 | FPGA (field programmable Gate array) online debugging method for realizing continuous sampling |
| CN113850042A (en) * | 2021-08-23 | 2021-12-28 | 深圳市紫光同创电子有限公司 | Concurrent debugging method and system based on programmable logic device |
| CN113850042B (en) * | 2021-08-23 | 2024-04-30 | 深圳市紫光同创电子有限公司 | Concurrent debugging method and system based on programmable logic device |
| CN116306429A (en) * | 2023-01-18 | 2023-06-23 | 广东高云半导体科技股份有限公司 | Method, device, computer storage medium and terminal for realizing state data capture |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105787164A (en) | Debugging method and system for programmable logic device | |
| CN102541707B (en) | FPGA on-chip logic analyzer system and method for multiplexing JTAG interface | |
| US8214694B1 (en) | Lightweight probe and data collection within an integrated circuit | |
| Anis et al. | Low cost debug architecture using lossy compression for silicon debug | |
| US9495492B1 (en) | Implementing synchronous triggers for waveform capture in an FPGA prototyping system | |
| US8607174B2 (en) | Verification module apparatus to serve as a prototype for functionally debugging an electronic design that exceeds the capacity of a single FPGA | |
| US8997034B2 (en) | Emulation-based functional qualification | |
| US6760898B1 (en) | Method and system for inserting probe points in FPGA-based system-on-chip (SoC) | |
| US8281280B2 (en) | Method and apparatus for versatile controllability and observability in prototype system | |
| Huang et al. | SoC HW/SW verification and validation | |
| CN100425999C (en) | Circuit board fault self-positioning device and method based on programmable logic device | |
| KR102596638B1 (en) | Methods and circuits for debugging circuit designs | |
| CN103870627A (en) | Design and simulation system, device and method | |
| US8214701B1 (en) | Hardware and software debugging | |
| US7373619B2 (en) | Post-silicon test coverage verification | |
| CN115454751A (en) | FPGA chip testing method and device and computer readable storage medium | |
| CN105486998A (en) | Processor board card parameter lossless automatic test method and monitoring host device | |
| CN105093001A (en) | Automatic analysis test system for characteristics of high-speed PLL and clock chip | |
| Xu et al. | On signal tracing in post-silicon validation | |
| US9946624B1 (en) | Systems and methods to capture data signals from a dynamic circuit | |
| Mathaikutty et al. | Model-driven test generation for system level validation | |
| KR20200033881A (en) | Logic analyzer for integrated circuits | |
| KR101192556B1 (en) | Method for design verification system of digital circuits and the verification system thereof | |
| CN108848001A (en) | A kind of network-on-chip test encapsulation based on one-way transmission path | |
| CN117709251A (en) | ARINC429 interface automatic verification system and method based on SV |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| CB02 | Change of applicant information |
Address after: 518057 Guangdong city of Shenzhen province Nanshan District high tech Industrial Park Road eight South South technology Howare Technology Building 16 Applicant after: Shenzhen Pango Microsystems Co., Ltd. Address before: 518057 Guangdong city of Shenzhen province Nanshan District high tech Industrial Park Road eight South South technology Howare Technology Building 16 Applicant before: SHENZHEN PANGO MICROSYSTEMS CO., LTD. |
|
| COR | Change of bibliographic data | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160720 |
|
| RJ01 | Rejection of invention patent application after publication |