CN105762177A - Anti-latch IGBT device - Google Patents

Abstract

The present invention relates to an anti-latch-up IGBT device, in which a plurality of regularly arranged and parallel to each other active cells are arranged in a base region of a first conductivity type of a semiconductor substrate, and the active cells include The base region of the second conductivity type in the upper part of the base region and the source region of the first conductivity type located in the base region of the second conductivity type, the base region of the second conductivity type, the source region of the first conductivity type and the semiconductor substrate The source metal ohmic contact on the first main surface; a first conductivity type barrier ring is also provided in the second conductivity type base region, and the first conductivity type barrier ring is located outside the first conductivity type source region Circle, outside the barrier ring of the first conductivity type and between the barrier ring of the first conductivity type and the source of the first conductivity type is the base region of the second conductivity type, and one end of the barrier ring of the first conductivity type passes through the first main surface of the semiconductor substrate The insulating dielectric layer is isolated from the source metal, and the other end is in contact with the side wall of the channel. The invention has a compact structure, can effectively reduce the risk of latching, provides a basis for reducing the conduction voltage drop, is compatible with the existing technology, and is safe and reliable.

Description

A kind of anti-latch-up IGBT device

technical field

The invention relates to a semiconductor device, in particular to an anti-latch IGBT device, belonging to the technical field of IGBT devices.

Background technique

There are parasitic thyristors in the IGBT device, that is, the NPNP structure. During normal operation of the device, it is undesirable to turn on the parasitic thyristor. If the parasitic thyristor is turned on, the gate of the IGBT device will lose control of the current. However, during the operation of the IGBT, if the hole current flowing under the source is too large, the PN junction between the source and the base region will be forward biased, that is, the source starts to inject electrons into the base region, and the base region begins to inject electrons into the source region. At this time, the parasitic thyristor is turned on, that is, the IGBT device is in a latched state.

Now that the current density pursued by IGBT is getting higher and higher, there is a risk of latch-up in the device when the device is working at a high current. In order to reduce the risk of latch-up of IGBT devices during operation, on the one hand, the doping concentration of the base region under the source is increased to reduce the resistance of this part of the region, but this can easily affect the threshold voltage of the device, thus affecting the design of the device. and increase the difficulty of manufacturing; on the other hand, it is to reduce the doping concentration of the back collector of the device, thereby reducing the component of the hole current in the conduction current, but this will increase the conduction voltage drop of the device, especially for those with a wide N-type base region For high-voltage IGBT devices, the conduction voltage drop will be very large. Moreover, when the backside doping of the device is too low, the short-circuit robustness of the device will be reduced.

As shown in Figure 1, it is the structure of an existing trench type IGBT device. Taking an N-type IGBT device as an example, the IGBT device includes an N-type base region 7, and a P-type base region is arranged on the upper part of the N-type base region 7. Region 6, a cell trench 13 is provided in the P-type base region 6, the bottom of the cell trench 13 is located in the N-type base region 7, and an N+ source region 4 is provided above the outer wall side of the cell trench 13 , the sidewall and bottom wall of the cell trench 13 are covered with an insulating gate oxide layer 14 , and the cell trench 13 is filled with conductive polysilicon 3 . The source metal 1 is provided on the front of the N-type base region 7, and the source metal 1 is insulated and isolated from the conductive polysilicon 3 through the insulating dielectric layer 2 on the N-type base region 7, and the source metal 1 and the N+ source region 4 And the P-type heavily doped region 5 in the P-type base region 6, the P-type heavily doped region 5 also extends to the bottom of the N+ source region 4 in the P-type base region 6, but the P-type heavily doped region 5 is not in contact with the outer wall of the cell groove 13 . A collector structure is provided on the back of the N-type base region 7 , and the collector structure includes a P-type collector region 9 and a collector metal 10 in ohmic contact with the P-type collector region 9 .

During specific work, the region part of the P-type heavily doped region 5 located under the N+ source region 4 can form an anti-latch-up structure 11. In order to make the device have high anti-latch-up performance, a P-type anti-latch-up structure 11 is formed. The doping concentration must be very high, and at the same time, the high doping must be as close as possible to the sidewall of the cell trench 13, and since the P-type doping of the sidewall of the cell trench 13 directly affects the threshold voltage of the IGBT device, so the The above-mentioned anti-latch-up structure 11 brings great difficulty to the design and process of the IGBT device.

On the other hand, in order to prevent the IGBT device from latch-up during use, the doping concentration of the P-type collector region 9 is generally relatively low, and its junction depth is generally relatively shallow, which makes the holes injected by the N-type base region 7 If it is relatively small, the conductance modulation effect is not significant, which will lead to a relatively large turn-on voltage drop of the IGBT device.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art and provide an anti-latch-up IGBT device, which has a compact structure, can effectively reduce the risk of latch-up, and provides a basis for reducing the conduction voltage drop. Compatible, safe and reliable.

According to the technical solution provided by the present invention, the anti-latch-up IGBT device includes a semiconductor substrate having two opposite main surfaces, and the two opposite main surfaces of the semiconductor substrate include a first main surface and a second main surface corresponding to the first main surface. The main surface; the first main surface and the second main surface of the semiconductor substrate include a base region of the first conductivity type; a number of active cells arranged regularly and parallel to each other are arranged in the base region of the first conductivity type of the semiconductor substrate, The active cell includes a base region of the second conductivity type located in the upper part of the base region of the first conductivity type and a source region of the first conductivity type located in the base region of the second conductivity type, and the base region of the second conductivity type The region, the source region of the first conductivity type are in ohmic contact with the source metal on the first main surface of the semiconductor substrate;

A barrier ring of the first conductivity type is also provided in the base region of the second conductivity type. The barrier ring of the first conductivity type is located on the outer circle of the source region of the first conductivity type. The type source region is separated by the second conductivity type base region, one end of the first conductivity type barrier ring is isolated from the source metal by the insulating medium layer on the first main surface of the semiconductor substrate, and the other end is connected to the conductive channel of the active cell sidewall contact.

A collector structure is provided on the second main surface of the semiconductor substrate. The collector structure includes a collector metal and a collector layer in ohmic contact with the collector metal. Between the two main surfaces, the collector layer includes a collector region of the second conductivity type.

A buffer layer of the first conductivity type is also provided between the collector layer and the second main surface of the semiconductor substrate.

The collector layer further includes several collector regions of the first conductivity type located in the collector region of the second conductivity type, and the collector regions of the first conductivity type are in ohmic contact with the collector metal.

The active cells are planar or grooved.

When the active cell adopts a planar structure, the planar active cell includes two adjacent base regions of the second conductivity type and a source region of the first conductivity type located in the base region of the second conductivity type, The adjacent base regions of the second conductivity type are separated by the base regions of the first conductivity type, and a conductive polysilicon and an insulating dielectric layer are provided directly above the first base regions of the adjacent second conductivity type. The conductive polysilicon The insulating dielectric layer is isolated from the first main surface of the semiconductor substrate and the source metal, and the two ends of the conductive polysilicon overlap with the underlying first conductivity type source region, and are set in each second conductivity type base region The barrier ring of the first conductivity type, the barrier ring of the first conductivity type is located on the outer circle of the source region of the first conductivity type, and the conductive polysilicon is in ohmic contact with the gate metal.

When the active cell adopts a groove-like structure, the active cell includes a cell groove located in the second conductivity type base region, and the bottom of the cell groove is located in the second conductivity type base region In the base region of the first conductivity type below, the inner wall and bottom wall of the cell trench are covered with an insulating gate oxide layer, and the cell trench covered with the insulating gate oxide layer is filled with conductive polysilicon. The notch is covered by an insulating dielectric layer on the first main surface of the semiconductor substrate, and the conductive polysilicon in the cell trench is isolated from the source metal by the insulating dielectric layer; the source region of the first conductivity type is located above the outer wall of the cell trench , the source region of the first conductivity type and the barrier ring of the first conductivity type are in contact with the outer wall of the cell trench, and the conductive polysilicon in the cell trench is in ohmic contact with the gate metal.

The material of the semiconductor substrate includes silicon.

The shape of the active cells is strip, square or circle.

A second conductivity type heavily doped region for forming an anti-latch-up structure is provided inside the first conductivity type barrier ring, and the second conductivity type heavily doped region is located outside and below the first conductivity type source region, The heavily doped region of the second conductivity type is in contact with the source region of the first conductivity type, and the length of the heavily doped region of the second conductivity type below the source region of the first conductivity type is smaller than the length of the source region of the first conductivity type.

Among the "first conductivity type" and "second conductivity type", for N-type IGBT devices, the first conductivity type refers to N-type, and the second conductivity type is P-type; for P-type IGBT devices, the first conductivity type The type referred to by the type and the second conductivity type is just opposite to that of the N-type IGBT device.

Advantages of the present invention: a barrier ring of the first conductivity type is provided in the base region of the second conductivity type, and the lower part of the source region of the first conductivity type is surrounded by the barrier ring of the first conductivity type, so as to effectively separate electron current and holes The current is separated, which can significantly reduce or even prevent the hole current from flowing under the source region of the first conductivity type, and only allow the electron current to flow to the source region of the first conductivity type through the channel, which can improve the anti-latch-up ability of the IGBT device , providing a basis for reducing the conduction voltage drop, compatible with existing processes, and safe and reliable.

Description of drawings

FIG. 1 is a cross-sectional view of a conventional trench type IGBT device.

Fig. 2 is a cross-sectional view of the trench PT type IGBT device of the present invention.

Fig. 3 is a cross-sectional view of a planar PT-type IGBT device of the present invention.

Fig. 4 is a cross-sectional view of a trench NPT type IGBT device of the present invention.

Fig. 5 is a cross-sectional view of the trench PT type RCIGBT device of the present invention.

Fig. 6 is a cross-sectional view of a trenched NPT type RCIGBT device according to the present invention.

Fig. 7 is a cross-sectional view of a planar NTP type IGBT device of the present invention.

Fig. 8 is a cross-sectional view of a planar PT-type RCIGBT device of the present invention.

Fig. 9 is a cross-sectional view of a planar NPT type RCIGBT device of the present invention.

Fig. 10 is a schematic diagram of the structure of the active cell of the present invention in a strip shape.

Fig. 11 is a schematic diagram of the square structure of the active cell of the present invention.

Fig. 12 is a schematic diagram of the circular structure of the active cell of the present invention.

Description of reference signs: 1-source metal, 2-insulating dielectric layer, 3-conductive polysilicon, 4-N+ source region, 5-P-type heavily doped region, 6-P-type base region, 7-N-type base region region, 8-N-type buffer layer, 9-P-type collector region, 10-collector metal, 11-anti-latch-up structure, 12-N-type barrier ring, 13-cell trench, 14-insulated gate oxide layer , 15-N-type collector and 16-active cells.

detailed description

The present invention will be further described below in conjunction with specific drawings and embodiments.

In order to effectively reduce the risk of latch-up and provide a basis for reducing the conduction voltage drop, taking an N-type IGBT device as an example, the present invention includes a semiconductor substrate with two opposite main surfaces, and the two opposite main surfaces of the semiconductor substrate include the first A main surface and a second main surface corresponding to the first main surface; an N-type base region 7 is included between the first main surface and the second main surface of the semiconductor substrate; several regular rows are arranged in the N-type base region 7 of the semiconductor substrate The active cells 16 distributed parallel to each other, the active cells 16 include the P-type base region 6 located in the upper part of the N-type base region 7 and the N+ source region 4 located in the P-type base region 6 , the P-type base region 6 and the N+ source region 4 are in ohmic contact with the source metal 1 on the first main surface of the semiconductor substrate;

An N-type barrier ring 12 is also provided in the P-type base region 6. The N-type barrier ring 12 is located on the outer ring of the N+ source region 4, and the N-type barrier ring 12 and the N+ source region 4 pass through a P-type The base region 6 is spaced apart. One end of the barrier ring of the first conductivity type is insulated from the source metal through the insulating medium layer on the first main surface of the semiconductor substrate, and the other end is in contact with the conductive channel sidewall of the active cell 16 .

Specifically, the material of the semiconductor substrate includes silicon. Of course, other commonly used semiconductor materials can also be used for the semiconductor substrate. For N-type IGBT devices, the conductivity type of the semiconductor substrate is N-type. Generally, the front side of the semiconductor substrate forms the first main surface , the back surface of the semiconductor substrate forms a second main surface, and the first main surface corresponds to the second main surface. The P-type base region 6 is located in the upper part of the N-type base region 7 , the N+ source region 4 is located in the P-type base region 6 , and the P-type base region 6 is in ohmic contact with the source metal 1 .

The N-type barrier ring 12 is located in the P-type base region 6, the N-type barrier ring 12 is on the outer ring of the N+ source region 4, and the outside of the N-type barrier ring 12 and between the N-type barrier ring and the N+ source 4 are P-type The base region 6, that is, the N+ source region 4 is located in the surrounding ring formed by the N-type barrier ring 12, the N+ source region 4 is located in the upper part of the P-type base region 6, and the upper part of the N+ source region 4 is connected to the first main body of the semiconductor substrate. The source metal 1 on the surface is in direct ohmic contact. An N-type barrier ring 12 is used to form a surrounding ring surrounding the lower part of the N+ source region 4. One end of the N-type barrier ring 12 is insulated from the source metal 1 through an insulating dielectric layer 2, and the other end of the N-type barrier ring 12 is connected to the active The sidewalls of the conductive channels of the cells 16 are in contact, and the position of the other end of the N-type barrier ring 12 is related to the specific form of the active cells 16, which are well known to those skilled in the art and will not be described in detail here. The N-type barrier ring 12 in the P-type base region 6 is equivalent to a hole barrier, therefore, it can effectively separate the electron current and the hole current, and can significantly reduce or even prevent the hole current from passing through the N+ source. Under the region 4, only electron current is allowed to flow to the N+ source region 4 through the channel, so that the anti-latch-up capability of the IGBT device can be improved.

During specific implementation, the N-type barrier ring 12 can be formed through existing doping and thermal diffusion processes, and the specific preparation process is well known to those skilled in the art, and will not be repeated here. The shape of the active cells 16 is strip, square or circle, as shown in FIG. 10 , FIG. 11 and FIG. 12 respectively.

In a specific implementation, the active cells 16 are planar or groove-shaped, which can be determined according to requirements. The planar and groove-like forms of the active cells 16 will be described below.

When the active cell 16 adopts a planar structure, the planar active cell includes two adjacent P-type base regions 6 and an N+ source region 4 located in the P-type base region 6, and the adjacent The P-type base regions 6 are spaced apart by the N-type base regions 7, and a conductive polysilicon 3 and an insulating dielectric layer 2 are arranged directly above the N-type base regions 7 adjacent to the P-type base regions 6, and the conductive polysilicon 3 passes through the insulating dielectric layer. 2 is insulated and isolated from the first main surface of the semiconductor substrate and the source metal 1, and both ends of the conductive polysilicon 3 overlap the N+ source region 4 below, and the conductive polysilicon 3 is in ohmic contact with the gate metal.

In the embodiment of the present invention, when the active cells 16 are planar, the P-type base regions 6 are discontinuously distributed in the N-type base regions 7, and the adjacent P-type base regions 6 are connected to each other through the N-type base regions 7. Interval: For one active cell 16, there are N+ source regions 4 in its two adjacent P-type base regions 6, and the doping concentration of the N+ source region 4 is greater than that of the N-type base region 7. An N-type barrier ring 12 is arranged in each P-type base region 6, and the N-type barrier ring 12 is located on the outer ring of the N+ source region 4. One end of the N-type barrier ring is isolated from the source metal 1 by an insulating medium 2, and the other end is isolated from the source metal 1 by an insulating medium 2. One end is in contact with the gate insulating dielectric 2 at the side wall of the channel, the conductive polysilicon 3 is surrounded by the cell insulating dielectric layer 2, the two ends of the conductive polysilicon 3 partly overlap with the N+ source region 4, the conductive polysilicon 3 and the N+ source The overlapping parts of the regions 4 are separated by the cell insulating dielectric layer 2 , and the rest of the N+ source region 4 is in ohmic contact with the source metal 1 . In order to form the gate of the IGBT device, all the conductive polysilicon 3 is drawn out to make ohmic contact with the gate metal, and the specific form of drawing the conductive polysilicon 3 to be in ohmic contact with the gate metal can be a form commonly used in this technical field. It is well known to those in the technical field, and will not be repeated here.

When the active cell 16 is a planar active cell, the collector structure on the back of the planar active cell is different to obtain a PT-type IGBT or an NPT-type IGBT. Figure 3 shows a planar PT-type IGBT device, and Figure 7 shows a planar NPT-type device. IGBT devices. For a planar NPT type IGBT device, the collector structure includes a collector metal 10 and a P-type collector region 9 in ohmic contact with the collector metal 10, and the P-type collector region 9 is located between the collector metal 10 and the semiconductor substrate. The second main room. For a planar PT-type IGBT device, an N-type buffer layer 8 is also provided between the P-type collector region 9 and the second main surface of the semiconductor substrate, and the N-type buffer layer 8 is adjacent to the N-type base region 7 and the P-type collector region. Electric Zone 9.

In addition, depending on the collector layer, an RCIGBT (Reverseconductinginsulatedgatebipolartransistor) device can also be formed. Figure 8 shows a planar PT-type RCIGBT device. There are also several N-type collector regions 15 in the P-type collector region 9. The electrical region 9 and the N-type collector region 15 form a collector layer to obtain a planar PT-type RCIGBT device. In FIG. 9 , several N-type collector regions 15 are also provided in the P-type collector region 9 , and a planar NPT type RCIGBT device is obtained through cooperation of the P-type collector region 9 and the N-type collector region 15 . The working process of the IGBT devices formed by different collector structures is well known to those skilled in the art, and will not be repeated here.

When the active cell 16 adopts a trench-like structure, the active cell of the trench includes a cell trench 13 located in the P-type base region 6, and the bottom of the cell trench 13 is located in the P-type In the N-type base region 7 below the base region 6, the inner wall and bottom wall of the cell trench 13 are covered with an insulating gate oxide layer 14, and the cell trench 13 covered with the insulating gate oxide layer 14 is filled with conductive polysilicon 3. The notch 13 of the cell trench is covered by the insulating dielectric layer 2 on the first main surface of the semiconductor substrate, and the conductive polysilicon 3 in the cell trench 13 is insulated and isolated from the source metal 1 by the insulating dielectric layer 2; the N+ source The pole region 4 is located above the outer wall of the cell trench 13, one end of the N+ source region 4 and the N-type barrier ring 12 is in contact with the outer wall of the cell trench 13, and the other end of the N-type barrier ring 12 passes through the source metal 1 The insulating medium 2 is used for isolation, and the conductive polysilicon 3 in the cell trench 13 is in ohmic contact with the gate metal.

During specific implementation, the notch of the cell trench 13 is located on the first main surface of the semiconductor substrate, and extends vertically downward from the first main surface of the semiconductor substrate, the cell trench 13 passes through the P-type base region 6, and the unit The bottom of the cell trench 13 is located in the N-type base region 7 below the P-type base region 6 . Through processes such as thermal oxidation, an insulating gate oxide layer 14 is grown on the side wall and bottom wall of the cell trench 13. The insulating gate oxide layer 14 can be a silicon dioxide layer. In the cell trench with the insulating gate oxide layer 14 grown The groove 13 is filled with conductive polysilicon 3, and the conductive polysilicon 3 fills the cell trench 13, and the insulating dielectric layer 2 at the notch of the cell trench 13 blocks the cell conductive polysilicon 3, so that the conductive polysilicon 3 is isolated from the source metal 1 . The doping concentration of the N+ source region 4 is greater than the doping concentration of the N-type base region 7, the depth of the N+ source region 4 is smaller than the depth of the P-type base region 5, and the outer sidewall of the N+ source region 4 and the cell trench 13 and in ohmic contact with the source metal 1, so that the desired source terminal of the IGBT device can be formed.

On the cross section of the IGBT device, N-type barrier rings 12 are distributed on both sides of the cell trench 13, and the N-type barrier rings 12 surround the N+ source regions 4 on both sides of the outer wall of the cell trench 13. One end of the ring 12 is isolated from the source metal 1 through the insulating medium 2, and the other end of the N-type barrier ring 12 is in contact with the outer wall of the lower part of the cell trench 13, thereby effectively surrounding the N+ source region 4 and realizing The effective separation of the electron current and the hole current significantly reduces or even prevents the hole current from flowing under the N+ source region 4 . The connection and cooperation between the conductive polysilicon 3 and the gate metal in the cell trench 13 is well known to those skilled in the art, and will not be repeated here.

When the active cell 16 is a trench active cell, the structure of the collector on the back of the trench active cell is different to obtain a PT-type IGBT or an NPT-type IGBT. Figure 2 is a trench PT-type IGBT device, and Figure 4 is Trench NPT type IGBT device. For a trench NPT type IGBT device, the collector structure includes a collector metal 10 and a P-type collector region 9 in ohmic contact with the collector metal 10, and the P-type collector region 9 is located between the collector metal 10 and the semiconductor substrate. The second main face room. For trench PT-type IGBT devices, an N-type buffer layer 8 is also provided between the P-type collector region 9 and the second main surface of the semiconductor substrate, and the N-type buffer layer 8 is adjacent to the N-type base region 7 and the P-type Collector area9.

In addition, depending on the collector layer, RCIGBT (Reverseconductinginsulatedgatebipolartransistor) devices can also be formed. Figure 5 shows a trench PT-type RCIGBT device. There are also several N-type collector regions 15 in the P-type collector region 9. The collector region 9 and the N-type collector region 15 form a collector layer to obtain a trench PT-type RCIGBT device. In FIG. 6 , several N-type collector regions 15 are also provided in the P-type collector region 9 , and a grooved NPT type RCIGBT device is obtained through cooperation of the P-type collector region 9 and the N-type collector region 15 . The working process of the IGBT devices formed by different collector structures is well known to those skilled in the art, and will not be repeated here.

Further, the N-type barrier ring 12 is provided with a P-type heavily doped region 5 for forming the anti-latch-up structure 11, and the P-type heavily doped region 5 is located outside and below the N+ source region 4, P The P-type heavily doped region 5 is in contact with the N+ source region 4, and the length of the P-type heavily doped region 5 below the N+ source region 4 is less than the length of the N+ source region.

In the embodiment of the present invention, whether the active cell 16 adopts a planar active cell or a groove active cell, an existing anti-latch structure 11 can be arranged in the active cell 16; the anti-latch The structure 11 includes a P-type heavily doped region 5 coordinated with the N+ source region 4 , and the doping concentration of the P-type heavily doped region 5 is greater than that of the P-type base region 6 . The P-type heavily doped region 5 is located in the P-type base region 6, and the length of the P-type heavily doped region 5 located below the N+ source region 4 is less than the length of the N+ source region 4, that is, when the active cell 16 is a trench When the cell is active, the P-type heavily doped region 5 is not in contact with the outer wall of the cell trench 13 . The specific form of the cooperation between the P-type heavily doped region 5 and the N+ source region 4 to form the anti-latch-up structure 11 is the same as the prior art, and will not be repeated here.

In the present invention, an N-type barrier ring 12 is set in the P-type base region 6, and the lower part of the N+ source region 4 is surrounded by the N-type barrier ring 12, that is, the outside of the N-type barrier ring 12 and the N-type barrier ring and the N+ source 4 is a P-type base region 6, one end of the N-type barrier ring 12 is insulated from the source metal 1 through the insulating dielectric layer 2, and the other end is in contact with the side wall of the conductive channel of the active cell 16, so as to effectively The electron current and the hole current are separated to significantly reduce or even prevent the hole current from flowing under the N+ source region 4, and only allow the electron current to flow to the N+ source region 4 through the channel, which can improve the latch-up resistance of the IGBT device Ability to provide a basis for reducing the conduction voltage drop, compatible with existing processes, safe and reliable.

Claims (10)

1. An anti-latch-up IGBT device, comprising a semiconductor substrate with two relative main surfaces, the two relative main surfaces of the semiconductor substrate comprising a first main surface and a second main surface corresponding to the first main surface; the semiconductor substrate A base region of the first conductivity type is included between the first main surface and the second main surface; a number of active cells arranged regularly and parallel to each other are arranged in the base region of the first conductivity type of the semiconductor substrate, the active cells It includes a base region of the second conductivity type located in the upper part of the base region of the first conductivity type and a source region of the first conductivity type located in the base region of the second conductivity type, the base region of the second conductivity type, the base region of the first conductivity type The source region is in ohmic contact with the source metal on the first main surface of the semiconductor substrate; it is characterized by: A barrier ring of the first conductivity type is also provided in the base region of the second conductivity type. The barrier ring of the first conductivity type is located on the outer circle of the source region of the first conductivity type. The type source region is separated by the second conductivity type base region, one end of the first conductivity type barrier ring is isolated from the source metal by the insulating medium layer on the first main surface of the semiconductor substrate, and the other end is connected to the conductive channel of the active cell sidewall contact. 2. The anti-latch-up IGBT device according to claim 1, characterized in that: a collector structure is provided on the second main surface of the semiconductor substrate, and the collector structure includes a collector metal and a A collector layer in ohmic contact, the collector layer is located between the collector metal and the second main surface of the semiconductor substrate, and the collector layer includes a second conductivity type collector region. 3. The anti-latch-up IGBT device according to claim 2, characterized in that: a buffer layer of the first conductivity type is further provided between the collector layer and the second main surface of the semiconductor substrate. 4. The anti-latch-up IGBT device according to claim 2, characterized in that: the collector layer further comprises a plurality of collector regions of the first conductivity type located in the collector region of the second conductivity type, the collector regions of the first conductivity type The electrical region is in ohmic contact with the collector metal. 5. The anti-latch-up IGBT device according to claim 1, characterized in that: the active cells are planar or groove-shaped. 6. The anti-latch-up IGBT device according to claim 5, characterized in that: when the active cell adopts a planar structure, the planar active cell includes two adjacent base regions of the second conductivity type and The first conductivity type source region located in the second conductivity type base region, the adjacent second conductivity type base regions are separated by the first conductivity type base region, and the second conductivity type base region adjacent to the second conductivity type base region is separated Conductive polysilicon and an insulating dielectric layer are provided directly above the base region of a conductivity type. The conductive polysilicon is isolated from the first main surface of the semiconductor substrate and the source metal through the insulating dielectric layer, and the two ends of the conductive polysilicon are connected to the first conductive layer below. The source regions of the first conductivity type are overlapped, and a barrier ring of the first conductivity type is provided in each base region of the second conductivity type. The barrier ring of the first conductivity type is located at the outer circle of the source region of the first conductivity type. pole metal ohmic contact. 7. The anti-latch-up IGBT device according to claim 5, characterized in that: when the active cells adopt a groove-like structure, the active cells include cells located in the second conductivity type base region trench, the bottom of the cell trench is located in the base region of the first conductivity type below the base region of the second conductivity type, the inner wall and bottom wall of the cell trench are covered with an insulating gate oxide layer, and are covered with an insulating gate oxide layer. The cell trench of the gate oxide layer is filled with conductive polysilicon, the notch of the cell trench is covered by the insulating dielectric layer on the first main surface of the semiconductor substrate, and the conductive polysilicon in the cell trench passes through the insulating dielectric layer and the source Metal insulation isolation; the source region of the first conductivity type is located above the outer wall of the cell trench, the source region of the first conductivity type and the barrier ring of the first conductivity type are in contact with the outer wall of the cell trench, and the conduction in the cell trench The polysilicon is in ohmic contact with the gate metal. 8. The anti-latch-up IGBT device according to claim 1, wherein the material of the semiconductor substrate comprises silicon. 9. The anti-latch-up IGBT device according to claim 1, characterized in that: the shape of the active cells is strip, square or circle. 10. The anti-latch-up IGBT device according to claim 1, characterized in that: a heavily doped region of the second conductivity type for forming an anti-latch-up structure is provided in the barrier ring of the first conductivity type, and the second The heavily doped region of the conductivity type is located outside and below the source region of the first conductivity type, the heavily doped region of the second conductivity type is in contact with the source region of the first conductivity type, and the heavily doped region of the second conductivity type is in the first conductivity type The length below the source region of the first conductivity type is less than the length of the source region of the first conductivity type.