CN105742421A - Normal LED (light emitting diode) and manufacturing process therefor - Google Patents

Abstract

A formal LED light-emitting diode and a manufacturing process thereof relate to the technical field of LED light-emitting diodes. On the epitaxial layer, the P?GaN layer and part of the quantum well layer of each cell are etched and removed in a patterned manner until the N?GaN layer is exposed; on the surface of the epitaxial wafer, a transparent conductive material is evaporated by sputtering, and through photolithography Process, using chemical etching method, only retain the transparent conductive material on the P?GaN layer of each cell; make a P electrode on the transparent conductive layer of one of the two adjacent cells, and make a P electrode on the transparent conductive layer of the other cell The transparent conductive layer, the P?GaN layer and the quantum well layer are wrapped to make an N electrode, and the lower end of the N electrode is connected to the N?GaN layer. The present invention retains part of the P?GaN and the quantum well layer under the N electrode. The process of the present invention is simple, and a part of the P?GaN and MQW that originally need to be etched away is reserved, which reduces the black spot phenomenon after the ICP is etched. Occurrence and yield improvement.

Description

A formal LED light-emitting diode and its manufacturing process

technical field

The invention relates to the technical field of production of LED light-emitting diodes.

Background technique

Most of the current chips are positive-mounted structures, and the P electrode is directly formed on the P-GaN layer through the time-transmitting conductive layer. In order to directly connect the N electrode and the N-GaN layer, only the P-GaN layer under the P electrode is retained during etching. , quantum well layer, and the rest of the P-GaN layer and quantum well layer are all etched away, directly and completely exposing the N-GaN layer. A large number of N-GaN layers of this structure are directly exposed on the surface of the LED light-emitting diode, and are easily affected by epitaxial surface factors when performing ICP etching for N steps. After the electrodes are evaporated, ICP black spots and LED light-emitting diodes are prone to appear. The disadvantage of low yield.

Contents of the invention

The object of the present invention is to provide an LED light-emitting diode that can effectively reduce the occurrence of ICP black spots and improve the yield of the LED light-emitting diode.

The present invention includes an N-GaN layer, a quantum well layer, a P-GaN layer and a transparent conductive layer arranged in sequence on the same side of the substrate, a P electrode is arranged on the transparent conductive layer, and an N electrode is connected on the N-GaN layer, which It is characterized in that a transparent conductive layer, a P-GaN layer and a quantum well layer are wrapped between the N electrode and the N-GaN layer.

The invention retains part of the P-GaN and quantum well layers under the N electrode, which can reduce the area of the N-GaN layer directly exposed to the surface of the LED light-emitting diode, thereby reducing the occurrence of black spots after ICP etching, and improving the product quality. The yield rate, and the invention is beneficial to increase the lateral expansion capability of the current and improve the uniformity of the current distribution.

Another object of the present invention is to propose a manufacturing process of the above formal LED light-emitting diode.

The present invention comprises the following steps:

1) The N-GaN layer, the quantum well layer and the P-GaN layer are formed by sequential epitaxial growth on the same side of the substrate;

2) Etching and removing part of the P-GaN layer and quantum well layer of each cell in a patterned manner until the N-GaN layer is exposed;

3) Evaporate transparent conductive material on the epitaxial wafer surface by sputtering method, and use chemical etching method through photolithography process to keep only the transparent conductive material on the P-GaN layer of each cell;

4) Make a P electrode on the transparent conductive layer of one of the two adjacent cells, and make an N electrode on the transparent conductive layer, P-GaN layer and quantum well layer of the other cell. The lower ends of the electrodes are connected to the N-GaN layer.

The manufacturing process of the present invention is simple and effective. Under the condition of the same chip size and area, a part of the P-GaN and MQW that should be completely etched away is reserved, thereby reducing the occurrence of black spots after ICP etching and improving the yield rate. .

Description of drawings

Figures 1 to 2 are process diagrams of the manufacturing process of the present invention.

Fig. 3 is a schematic structural view of the present invention.

detailed description

1. The manufacturing process of the front-loading chip is as follows:

1. The N-GaN layer 2 , the quantum well layer 3 and the P-GaN layer 4 are formed by epitaxial growth sequentially on the conventional substrate 1 .

2. In the yellow light lithography process, use inductive couple and plasma (ICP) to adjust the ratio of etching gases BCl3 and Cl2 to etch and remove part of the P-GaN layer and quantum well layer of each cell in a patterned manner until the N -GaN layer, the etching depth is about 10000 Å～16000 Å.

The shape of the semi-finished product is shown in Figure 1.

3. Evaporate an indium tin oxide (ITO) transparent conductive layer 5 on the surface of the epitaxial wafer by sputtering. Through the photolithography process and chemical etching method, only the ITO on the P-GaN layer is retained, so that the current flows in the P-GaN layer. The uniformity of surface distribution is better. as shown in picture 2.

4. Fabricate and form a P electrode with a thickness of about 10000 Å-12000 Å on the transparent conductive layer of one of the two adjacent cells.

The transparent conductive layer, P-GaN layer and quantum well layer of the other two adjacent cells are wrapped to form an N electrode with a thickness of about 10000 Å to 12000 Å, and the lower end of the N electrode is connected to on the N-GaN layer.

2. The structural characteristics of the finished product:

As shown in Figure 3, on the same side of substrate 1, comprise N-GaN layer 2, quantum well layer 3, P-GaN layer 4 and transparent conductive layer 5 that are arranged in sequence, P electrode is set on transparent conductive layer 5, in A transparent conductive layer 5 , a P-GaN layer 4 and a quantum well layer 3 are arranged between the N electrode 7 and the N-GaN layer 2 in a wrapping manner.

Claims (2)

1. A positively mounted LED light-emitting diode comprises an N-GaN layer, a quantum well layer, a P-GaN layer and a transparent conductive layer arranged in sequence on the same side of the substrate, a P electrode is set on the transparent conductive layer, and the N-GaN The N electrode is connected on the layer, and the feature is that a transparent conductive layer, a P-GaN layer and a quantum well layer are arranged between the N electrode and the N-GaN layer. 2. The manufacturing process of formally mounted LED light-emitting diodes as claimed in claim 1, comprising the following steps: 1) The N-GaN layer, the quantum well layer and the P-GaN layer are formed by sequential epitaxial growth on the same side of the substrate; 2) Etching and removing part of the P-GaN layer and quantum well layer of each cell in a patterned manner until the N-GaN layer is exposed; 3) Evaporate transparent conductive material on the epitaxial wafer surface by sputtering method, and use chemical etching method through photolithography process to keep only the transparent conductive material on the P-GaN layer of each cell; 4) Make a P electrode on the transparent conductive layer of one of the two adjacent cells; It is characterized in that an N electrode is wrapped around the transparent conductive layer, P-GaN layer and quantum well layer of the other two adjacent cells, and the lower end of the N electrode is connected to the N-GaN layer.