CN105742352A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The invention provides a semiconductor device, comprising: a semiconductor substrate; a gate dielectric layer on the substrate; a gate structure on the gate dielectric layer; source and drain regions on both sides of the gate structure; wherein the gate structure includes a first The gate and the second gate, the first gate is located on the gate dielectric layer inside the source and drain regions, the second gate is located on the gate dielectric layer between the first gate, for NMOS, the first gate The effective work function is smaller than the effective work function of the second gate, and for PMOS, the effective work function of the first gate is greater than the effective work function of the second gate. In the present invention, before the device of the second gate is turned on, a region with more carriers will be induced in the substrate under the first gate, which is equivalent to the source-drain extension region, and the junction of the source-drain extension region The depth is very shallow, which can effectively suppress the short channel effect, reduce the static power consumption of the device, and improve the performance of the device.

Description

Semiconductor device and manufacturing method thereof

technical field

The invention relates to the field of semiconductor devices, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

With the high integration of semiconductor devices, the channel length of MOSFET is continuously shortened, and a series of effects that can be ignored in the MOSFET long channel model become more and more significant, and even become the dominant factor affecting device performance and power consumption. This phenomenon is collectively referred to as for the short channel effect. The short channel effect will deteriorate the electrical characteristics of the device, seriously affecting the performance and power consumption of the device.

In order to control the short channel effect, it is necessary to improve some aspects of the traditional device. In theory, the depth of the source/drain junction can be reduced, the threshold voltage can be reduced as the channel becomes shorter, and the drain electric field can be reduced. channel potential, thereby alleviating the short channel effect.

Contents of the invention

The purpose of the present invention is to solve the above-mentioned technical defects, provide a semiconductor device and its manufacturing method, and suppress the short channel effect.

The invention provides a semiconductor device, comprising:

semiconductor substrate;

a gate dielectric layer on the substrate;

A gate structure on the gate dielectric layer;

Source and drain regions on both sides of the gate structure;

Wherein, the gate structure includes a first gate and a second gate, the first gate is located on the gate dielectric layer inside the source and drain regions, and the second gate is located on the gate dielectric layer between the first gates, For NMOS, the effective work function of the first gate is smaller than that of the second gate, and for PMOS, the effective work function of the first gate is greater than that of the second gate.

Optionally, each of the gate lengths of the first gates is in a range of 2-40 nm.

Optionally, the first gate is a first work function adjustment layer, and the second gate includes a second work function adjustment layer and a third metal layer thereon.

Optionally, for NMOS devices, the effective work function of the first work function adjustment layer is less than 4.6eV, and for PMOS devices, the effective work function of the first work function adjustment layer is greater than 4.6eV.

Optionally, the second work function adjustment layer is formed on the sidewall of the first work function adjustment layer and on the gate dielectric layer between the first work function adjustment layers.

In addition, the present invention also provides a method for manufacturing a semiconductor device, comprising:

A semiconductor substrate is provided, and a dummy gate region and source and drain regions on both sides of the dummy gate region are formed on the substrate;

removing the dummy gate region to form an opening;

forming a first gate on the sidewall of the opening;

filling the opening to form a second gate in the opening;

Wherein, for NMOS, the effective work function of the first gate is smaller than that of the second gate, and for PMOS, the effective work function of the first gate is greater than that of the second gate.

Optionally, each of the gate lengths of the first gates is in a range of 2-40 nm.

Optionally, the first gate is a first work function adjustment layer.

Optionally, the step of forming the second gate includes: forming a second work function adjusting layer on the inner surface of the opening, and filling the opening with a third metal layer to form the second gate.

Optionally, for NMOS devices, the effective work function of the first work function adjustment layer is less than 4.6eV, and for PMOS devices, the effective work function of the first work function adjustment layer is greater than 4.6eV.

In the semiconductor device and its manufacturing method provided by the embodiments of the present invention, a first gate is formed on the gate dielectric layer inside the source and drain regions, and a second gate is formed on the gate dielectric layer between the first gates, Since the first gate and the second gate have different effective work functions, after the device is powered on, the threshold voltage of the first gate is lower than the threshold voltage of the second gate, and before the device of the second gate is turned on, A region with more carriers will be induced in the substrate under the first gate, which is equivalent to forming a source-drain extension region. The junction depth of the source-drain extension region is very shallow, which can effectively suppress the short channel effect and reduce the The static power consumption of the device improves the performance of the device.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

FIG. 1 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

FIG. 2 shows a schematic structural diagram of a semiconductor device according to an embodiment of the present invention when it is powered on;

FIG. 3 shows a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

4-12 show schematic structural diagrams of various stages of formation of a semiconductor device according to an embodiment of the present invention.

detailed description

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

The present invention aims to provide a semiconductor device to effectively suppress the short channel effect. 1, the device includes: a semiconductor substrate 100; a gate dielectric layer 104 on the substrate 100; a gate structure on the gate dielectric layer 104; source and drain regions 140 on both sides of the gate structure; The structure includes a first gate 120 and a second gate 130, the first gate 120 is located on the gate dielectric layer 104 inside the source and drain regions 140, and the second gate 130 is located on the gate dielectric layer between the first gates 120 Above 104 , for NMOS, the effective work function of the first gate 120 is smaller than that of the second gate 130 , and for PMOS, the effective work function of the first gate 120 is greater than that of the second gate 130 .

In the present invention, the first gate 120 can be a one-layer or multi-layer structure, which is located on the gate dielectric layer 104 of the substrate inside the source-drain region 140, which is equivalent to the region of the source-drain extension region of a common device. , the width (ie gate length) can be 2-40 nanometers. The second gate 130 may be a one-layer or multi-layer structure, which is located on the gate dielectric layer 104 between the first gates 120 , which is equivalent to the channel region of a common device. In a specific embodiment, the first gate can surround the second gate, or be located on both sides of the second gate, sandwiching the second gate, and the width (gate length) of the first gate refers to the second gate. The width d of the first gate 120 on each side of the second gate 130 .

Wherein, the first gate and the second gate have different effective work functions, for NMOS, the effective work function of the first gate is smaller than the effective work function of the second gate, for PMOS, the effective work function of the first gate greater than the effective work function of the second gate.

In a specific embodiment, the effective work function of the first grid and the second grid can be mainly adjusted through the work function adjustment layer. In this embodiment, as shown in FIG. 12 , the first grid 120 is a single-layer The structure is the first work function adjustment layer 120-1, the second grid 130 includes the second work function adjustment layer 130-1 and the third metal layer 130-2 thereon, wherein the first and second work function adjustment The gate electrode material with work function adjustment function is used for the first metal layer, and other gate materials are used for the third metal layer to complete the filling.

In this embodiment, for an NMOS device, the first work function adjustment layer 120-1 can use a metal gate material with an effective work function less than 4.6eV, and the metal gate material with an effective work function less than 4.6eV can be aluminum (Al), titanium aluminum, for example. Alloy (TiAl), titanium-aluminum-carbon alloy (TiAlC), nitride of lanthanide elements, titanium nitride (TiN) doped with phosphorus (P) or lanthanide elements, etc., or their combination; the second work function adjustment layer 130 -1 Use a metal gate material with an effective work function greater than that of the first work function adjustment layer, such as aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum carbon alloy (TiAlC), nitrides of lanthanide elements, doped Phosphorus (P) or titanium nitride (TiN) of lanthanide elements, etc., or a combination thereof.

In this embodiment, for a PMOS device, the first work function adjustment layer 120-1 can use a metal gate material with an effective work function greater than 4.6eV, and the metal gate material with an effective work function greater than 4.6eV can be molybdenum (Mo), nitride Titanium (TiN), nitrides of lanthanides, titanium nitride (TiN) doped with boron (B), indium (In), platinum (Pt), hafnium (Hf) or aluminum (Al), etc., and their In combination, the second work function adjustment layer can use a metal gate material whose effective work function is smaller than that of the first work function adjustment layer, for example, molybdenum (Mo), titanium nitride (TiN), nitrides of lanthanides, doped with Titanium nitride (TiN) of boron (B), indium (In), platinum (Pt), hafnium (Hf) or aluminum (Al), and other combinations.

In a specific embodiment, the dummy gate process is used to form the gate structure. As shown in FIG. 12, the first gate 120 is the first work function adjustment layer 120-1, and the second gate 130 includes the second work function adjustment layer 130-1 and the third metal layer 130-2 filled thereon, the second work function adjustment layer 130-1 is formed on the sidewall of the first work function adjustment layer 120-1 and the first work function adjustment layer 120- On the gate dielectric layer 104 between 1, in this specific embodiment, the first work function adjustment layer may be titanium aluminum alloy (TiAl), and the second work function adjustment layer may be titanium aluminum carbon alloy (TiAlC).

In the present invention, since the first gate and the second gate adopt different effective work functions, the threshold voltage of the first gate is lower than the threshold voltage of the second gate. After the device is powered on, refer to FIG. 2 , since the threshold voltage of the first gate is lower than the threshold voltage of the second gate, before the device of the second gate is turned on, a region with more carriers will be induced in the substrate under the first gate 120 150, which is equivalent to the source-drain extension region. The junction depth of the source-drain extension region is very shallow, which can effectively suppress the short channel effect, reduce the static power consumption of the device, and improve the performance of the device.

The structure of the semiconductor device of the present invention has been described above. In addition, the present invention also provides a method for manufacturing the above-mentioned semiconductor device. Referring to FIG. 3 , the method includes: providing a semiconductor substrate on which dummy gate regions and dummy The source and drain regions on both sides of the gate region; the dummy gate region is removed to form an opening; the first gate is formed on the sidewall of the opening; the opening is filled to form a second gate in the opening; wherein, for NMOS, The effective work function of the first gate is smaller than the effective work function of the second gate. For PMOS, the effective work function of the first gate is greater than the effective work function of the second gate.

In order to better understand the technical solutions and technical effects of the present invention, the manufacturing method of the above-mentioned semiconductor device will be described in detail below in conjunction with specific embodiments and the flowchart of the manufacturing method shown in FIG. 3 .

First, in step S01 , a semiconductor substrate 100 is provided, on which a dummy gate region and source and drain regions 140 on both sides of the dummy gate region are formed, as shown in FIG. 5 .

In the embodiment of the present invention, the semiconductor substrate 100 may be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator, Silicon On Insulator) or GOI (Germanium On Insulator, Germanium On Insulator) and the like. The semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., it can also be a stacked structure, such as Si/SiGe, etc., it can also be other epitaxial structures, such as SGOI ( silicon germanium on insulator), or a three-dimensional silicon structure, such as a silicon fin (Fin) or a nanowire structure. In this embodiment, the semiconductor substrate is a bulk silicon substrate, and the isolation 102 separating the active regions has been formed in the substrate, such as a shallow trench isolation (STI) structure.

In this embodiment, the dummy gate region may be a stacked structure including the dummy gate dielectric layer 103 and the dummy gate 106, and in other embodiments the dummy gate region may also be other single-layer or stacked structures, such as only including The dummy gate, which is a sacrificial layer, should be removed after forming subsequent structures. Specifically, the dummy gate region and the source and drain regions on both sides of the dummy gate region may be formed through the following steps.

First, deposit a stack of dummy gate dielectric layer 103 and dummy gate 106 in sequence. Dummy gate dielectric layer 103 can be a thermal oxide layer or other suitable dielectric material, such as silicon oxide, silicon nitride, etc., and dummy gate 106 can be It is made of amorphous silicon, polycrystalline silicon, or amorphous carbon, etc., and is patterned by etching technology to form a dummy gate region. As shown in Figure 4, unlike conventional devices, the gate length of the dummy gate is The sum of the gate length and the gate length used to induce source-drain extensions. Next, deposit the side wall material, the side wall can have a single-layer or multi-layer structure, and can be made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, boron or phosphorus doped silicon glass, low-k dielectric materials and combinations thereof , and/or other suitable materials, and after anisotropic etching, a sidewall 108 is formed on the sidewall of the dummy gate region, as shown in FIG. 4 . Then, the source and drain regions 140 can be formed by implanting p-type or n-type dopants or impurities into the substrate on both sides of the dummy gate region according to the desired transistor structure, and activating the doping by thermal annealing, as shown in FIG. 5 As shown, different from the conventional device process, in the present invention, the source and drain extension regions are not doped. Certainly, in other embodiments, the source and drain regions may also be formed by epitaxial methods.

Next, in step S02 , the dummy gate region is removed to form an opening 114 , as shown in FIG. 8 .

In this embodiment, after the interlayer dielectric layer is formed, the dummy gate region is removed to form an opening. Specifically, first, as shown in FIG. 6 , a contact etching stop layer material such as silicon nitride or silicon oxynitride can be deposited on the above-mentioned device to form a contact etching stop layer 110 (CESL, ContactEtchingStopLayer); then , the material 112 covering the interlayer dielectric layer, such as undoped silicon oxide (SiO ₂ ), doped silicon oxide (such as borosilicate glass, borophosphosilicate glass, etc.), or other low-k dielectric materials; then, perform Planarization, such as chemical mechanical polishing, until the dummy gate 106 is exposed, thereby forming a contact etch stop layer 110 on the source and drain regions 104 and covering the interlayer dielectric layer 112 thereon, as shown in FIG. 7 .

Next, an etching technique can be used to remove the dummy gate 106 of amorphous silicon. In a specific embodiment, for example, the dummy gate of polysilicon is removed by wet etching using an etching solvent including tetramethylammonium hydroxide (TMAH). , and further remove the dummy gate dielectric layer 103 until the substrate is exposed, thereby forming an opening 114 , as shown in FIG. 8 . Of course, in other embodiments, the dummy gate region may only include a dummy gate, and the underlying gate dielectric layer may not be removed, and a replacement gate may be directly re-formed on the gate dielectric layer.

Then, in step S03 , a first gate 120 having a first work function layer is formed on the sidewall of the opening, as shown in FIG. 10 .

In this embodiment, specifically, firstly, the interface layer 105 is formed by oxidation on the substrate of the opening 114, and the gate dielectric material 104 is deposited. As shown in FIG. 9, the gate dielectric material is, for example, a high-k dielectric material (e.g., a material with a high dielectric constant compared to silicon oxide) or other suitable dielectric materials, such as high-k dielectric materials such as hafnium-based oxides, zirconium-based oxides, aluminum oxide, lanthanide oxides, etc.; then , depositing the first work function adjustment layer 120-1, the first work function adjustment layer may be titanium aluminum alloy (TiAl), and the thickness may be 2-40 nanometers. This thickness determines the gate length of the first gate and the length of the source-drain extension region induced after the device is formed. Then, anisotropic etching, such as RIE, is performed to form the first gate only on the sidewall of the opening. The first gate of the work function adjustment layer 120-1 is shown in FIG. 10 .

Then, in step S04, the opening is filled to form the second gate 130, wherein, for NMOS, the effective work function of the first gate is smaller than the effective work function of the second gate, and for PMOS, the effective work function of the first gate is greater than the effective work function of the second grid, as shown in FIG. 12 .

In this embodiment, specifically, first, as shown in FIG. 11, a second work function adjustment layer 130-1 is deposited. The second work function adjustment layer 130-1 may be titanium aluminum carbon alloy (TiAlC), with a thickness of Can be 1-10 nanometers. Next, fill the third metal layer 130-2, and perform planarization treatment, such as CMP, until the interlayer dielectric layer 112 is exposed, as shown in FIG. The second gate of the three metal layers 130-2.

So far, the semiconductor device of the embodiment of the present invention is formed. Then, other structures of the device, such as source-drain contacts, gate contacts, etc., can be formed as required.

The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it to be equivalent to equivalent changes Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (10)

1. a semiconductor device, it is characterised in that including:

Semiconductor substrate；

Gate dielectric layer on substrate；

Grid structure on gate dielectric layer；

The source-drain area of grid structure both sides；

Wherein, grid structure includes first grid and second grid, first grid is positioned on the gate dielectric layer inside source-drain area, on second grid gate dielectric layer between first grid, for NMOS, the effective work function of first grid is less than the effective work function of second grid, and for PMOS, the effective work function of first grid is more than the effective work function of second grid.

2. semiconductor device according to claim 1, it is characterised in that the long scope of grid of described first grid is respectively 2-40nm.

3. semiconductor device according to claim 1, it is characterised in that described first grid is the first work function regulating course, described second grid includes the second work function regulating course and the 3rd metal level thereon.

4. semiconductor device according to claim 3, it is characterised in that for nmos device, the effective work function of the first work function regulating course is less than 4.6eV, and for PMOS device, the effective work function of the first work function regulating course is more than 4.6eV.

5. semiconductor device according to claim 3, it is characterised in that the second work function regulating course is formed on the gate dielectric layer on the sidewall of the first work function regulating course and between the first work function regulating course.

6. the manufacture method of a semiconductor device, it is characterised in that including:

Semiconductor substrate is provided, substrate is formed pseudo-grid region and the source-drain area of pseudo-both sides, grid region；

Remove pseudo-grid region, to form opening；

The sidewall of described opening is formed first grid；

Fill opening, to form second grid in the opening；

Wherein, for NMOS, the effective work function of first grid is less than the effective work function of second grid, and for PMOS, the effective work function of first grid is more than the effective work function of second grid.

7. manufacture method according to claim 6, it is characterised in that the long scope of grid of described first grid is respectively 2-40nm.

8. manufacture method according to claim 6, it is characterised in that described first grid is the first work function regulating course.

9. manufacture method according to claim 6, it is characterised in that the step forming second grid includes: form the second work function regulating course on the inner surface of opening, and fill opening with the 3rd metal level, to form second grid.

10. manufacture method according to claim 9, it is characterised in that for nmos device, the effective work function of the first work function regulating course is less than 4.6eV, and for PMOS device, the effective work function of the first work function regulating course is more than 4.6eV.