CN105742300B - Chip package and method for fabricating the same - Google Patents

Abstract

A chip package and a method for manufacturing the same, the chip package comprising a packaging substrate, a semiconductor element and a plurality of conductive structures. The semiconductor element has a central region and an edge region surrounding the central region. The conductive structure is located between the packaging substrate and the semiconductor element. The conductive structure has different heights, and the height of the conductive structure gradually increases from the central region of the semiconductor element to the edge region of the semiconductor element, so that the distance between the edge region of the semiconductor element and the packaging substrate is greater than the distance between the central region of the semiconductor element and the packaging substrate. As a result, the front side (i.e., the image sensing surface) of the semiconductor element of the present invention is a concave surface, which can simulate the shape of a retina. When the image sensing surface of the semiconductor element senses an image, light is easily concentrated, which can reduce the possibility of image distortion.

Description

Chip package and manufacturing method thereof

technical field

The invention relates to a chip package and a manufacturing method of the chip package.

Background technique

When manufacturing the chip package of the image sensor, the semiconductor element can be disposed on the circuit board by using soldering technology or surface mount technology (Surface Mount Technology; SMT). In this way, the solder balls located on the back of the semiconductor element can be electrically connected to the circuit board.

Since the size of the solder balls is approximately the same, and the semiconductor element is not specially designed, the existing semiconductor element is parallel to the circuit board, so that the front side of the semiconductor element (ie, the image sensing surface) is a horizontal plane. In this way, when the image sensing surface of the semiconductor element senses an image, light tends to diverge, which easily causes image distortion.

Contents of the invention

A technical aspect of the present invention is a chip package.

According to an embodiment of the present invention, a chip package includes a packaging substrate, a semiconductor element, and a plurality of conductive structures. The semiconductor element has a central area and an edge area surrounding the central area. The conductive structure is located between the packaging substrate and the semiconductor element. The conductive structures have different heights, and the heights of the conductive structures gradually increase from the central area of the semiconductor element to the edge area of the semiconductor element, so that the distance between the edge area of the semiconductor element and the packaging substrate is greater than the distance between the central area of the semiconductor element and the packaging material. distance between substrates.

In one embodiment of the present invention, the top view shape of the conductive structure includes circle, ellipse, polygon or a combination thereof.

In one embodiment of the present invention, the above-mentioned semiconductor element has a semiconductor substrate. The semiconductor substrate has pads and hollow areas. The solder pads are exposed from the hollowed out area. The semiconductor element also includes an insulating layer. The insulating layer is located on the surface of the semiconductor substrate facing the packaging substrate and on the surface of the semiconductor substrate surrounding the hollow area.

In one embodiment of the present invention, the above-mentioned semiconductor device further includes a redistribution layer. The redistribution layer is on the insulating layer and on the pad.

In one embodiment of the present invention, the above-mentioned semiconductor element further includes a protective layer. The protection layer is located on the redistribution layer and the insulation layer, and the protection layer has a plurality of openings, so that the redistribution layer is exposed through the openings.

In an embodiment of the present invention, the above-mentioned conductive structures are respectively located on the redistribution layers in the openings.

In one embodiment of the present invention, the diameter of the above-mentioned opening gradually decreases from the central area of the semiconductor element to the edge area of the semiconductor element.

Another technical aspect of the present invention is a method for manufacturing a chip package.

According to one embodiment of the present invention, a method for manufacturing a chip package includes the following steps: a) forming a plurality of conductive structures with different heights on the semiconductor element, wherein the height of the conductive structures is from the central area of the semiconductor element to the edge of the semiconductor element The area gradually increases; b) Pressing the semiconductor element on the packaging substrate, so that the semiconductor element is supported by the conductive structure and bends.

In one embodiment of the present invention, the above step a) includes adjusting the diameter of the opening of the printing nozzle, so that the conductive colloid is printed onto the semiconductor device from the printing nozzle with different diameters, so as to form conductive structures with different heights.

In one embodiment of the present invention, the manufacturing method of the above-mentioned chip package further includes: forming a protective layer on the redistribution layer of the semiconductor element; The central area gradually decreases towards the edge area of the semiconductor element.

In one embodiment of the present invention, the above step a) includes placing a plurality of conductive structures on the redistribution layer in the opening of the passivation layer.

In the above embodiments of the present invention, since the conductive structures have different heights, and the height of the conductive structures gradually increases from the central area of the semiconductor element to the edge area of the semiconductor element, the distance between the edge area of the semiconductor element and the package substrate The distance is greater than the distance between the central region of the semiconductor device and the package substrate. In this way, the front surface of the semiconductor element (ie, the image sensing surface) is a concave surface, which can be simulated into the shape of a retina. When the image sensing surface of the semiconductor element senses an image, the light is easy to concentrate, which can reduce the possibility of image distortion.

Description of drawings

FIG. 1 shows a side view of a chip package according to an embodiment of the present invention.

FIG. 2 is a side view of the semiconductor device shown in FIG. 1 when it is press-bonded to the packaging substrate.

FIG. 3 is a bottom view of the semiconductor device in FIG. 2 .

FIG. 4 is a cross-sectional view of the semiconductor device of FIG. 3 along line 4 - 4 .

FIG. 5 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention, and the cross-sectional position is the same as that in FIG. 4 .

FIG. 6 is a flowchart of a method for manufacturing a chip package according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view of a semiconductor substrate after forming a hollow region according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view of the semiconductor substrate in FIG. 7 after forming an insulating layer and a redistribution layer.

FIG. 9 is a cross-sectional view of the insulating layer and the redistribution layer of FIG. 8 after forming a protection layer.

FIG. 10 is a cross-sectional view of the redistribution layer of FIG. 9 after forming a conductive structure.

FIG. 11 is a cross-sectional view of the carrier of FIG. 10 when it is removed.

FIG. 12 is a cross-sectional view when the adhesive tape of FIG. 11 is removed.

Among them, a brief description of the symbols in the drawings is as follows:

100: chip package 110: packaging substrate

120: semiconductor element 120a: semiconductor element

1201: Semiconductor substrate 121a: Surface

121b: surface 122: central area

123: pad 124: edge area

125: hollow area 126: insulating layer

127: Redistribution layer 128: Protection layer

129: opening 129a: opening

129b: opening 129c: opening

130: conductive structure 130a: conductive structure

130b: conductive structure 130c: conductive structure

210: carrier 220: adhesive tape

230: tape 240: tape

4-4: Line segment D: Direction

D1: Distance D2: Distance

H1: Height H2: Height

H3: Height S1～S2: Steps.

Detailed ways

A number of embodiments of the present invention will be disclosed in the following figures. For the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some conventional structures and elements will be shown in a simple and schematic manner in the drawings.

FIG. 1 shows a side view of a chip package 100 according to an embodiment of the invention. FIG. 2 shows a side view of the semiconductor device 120 of FIG. 1 when it is pressed and bonded to the packaging substrate 110 . Referring to FIG. 1 and FIG. 2 at the same time, the chip package 100 includes a packaging substrate 110 , a semiconductor device 120 and a plurality of conductive structures 130 a , 130 b , 130 c. The semiconductor device 120 has a central region 122 and an edge region 124 surrounding the central region 122 . The conductive structures 130 a , 130 b , 130 c are located between the packaging substrate 110 and the semiconductor device 120 . The conductive structures 130a, 130b, 130c have different heights, and the heights of the conductive structures 130a, 130b, 130c gradually increase from the central region 122 of the semiconductor element 120 to the edge region 124 of the semiconductor element 120, so that the edge region 124 of the semiconductor element 120 The distance D1 between the packaging substrate 110 and the packaging substrate 110 is greater than the distance D2 between the central region 122 of the semiconductor device 120 and the packaging substrate 110 .

The conductive structure 130a has a height H1, the conductive structure 130b has a height H2, and the conductive structure 130c has a height H3, and the height H1 is smaller than the height H2, and the height H2 is smaller than the height H3. When the semiconductor device 120 has not been bonded to the packaging substrate 110 , the conductive structures 130 a , 130 b , 130 c may be located on the semiconductor device 120 or on the packaging substrate 110 . The semiconductor device 120 can be laminated on the package substrate 110 in the direction D by using surface mount technology (Surface Mount Technology; SMT).

Since the heights H1, H2, and H3 of the conductive structures 130a, 130b, and 130c gradually increase from the central region 122 of the semiconductor element 120 to the edge region 124 of the semiconductor element 120, when the semiconductor element 120 is bonded to the packaging substrate 110, the semiconductor The surface 121a of the element 120 is concave. In this embodiment, the surface 121 a of the semiconductor device 120 is the front side of the semiconductor device 120 , which is an image sensing surface capable of sensing light. The surface 121b of the semiconductor device 120 is the back side of the semiconductor device 120 and can be electrically connected to the package substrate 110 through the conductive structures 130a, 130b, 130c.

When the surface 121a of the semiconductor device 120 is concave, it can simulate the shape of a retina. In this way, when the surface 121a of the semiconductor device 120 (ie, the image sensing surface) senses an image, the light is easily concentrated, which reduces the possibility of image distortion.

In this embodiment, the packaging substrate 110 may be a circuit board. The material of the semiconductor element 120 may include silicon, and may be an image sensing chip, such as a CMOS element, but the present invention is not limited thereto. The conductive structures 130a, 130b, 130c may be solder balls, but the number, shape and material of the conductive structures are not intended to limit the present invention.

FIG. 3 is a bottom view of the semiconductor device 120 of FIG. 2 . FIG. 4 is a cross-sectional view of the semiconductor device 120 in FIG. 3 along line 4 - 4 . Referring to FIG. 3 and FIG. 4 at the same time, the top view shape of the conductive structures 130a, 130b, 130c may include a circle, an ellipse, a polygon or a combination thereof. The semiconductor element 120 has a semiconductor substrate 1201 (for example, a silicon wafer). The semiconductor substrate 1201 has a bonding pad 123 and a hollow area 125 . The pads 123 are exposed from the hollow area 125 . The semiconductor element 120 further includes an insulating layer 126 . The insulating layer 126 is located on the surface 121 b of the semiconductor substrate 1201 facing the packaging substrate 110 (see FIG. 1 ) and on the surface of the semiconductor substrate 1201 surrounding the hollow region 125 .

In addition, the semiconductor device 120 further includes a redistribution layer 127 and a passivation layer 128 . The redistribution layer 127 is located on the insulating layer 126 and on the bonding pad 123 . The passivation layer 128 is located on the redistribution layer 127 and the insulation layer 126 , and the passivation layer 128 has a plurality of openings 129 to expose the redistribution layer 127 from the openings 129 . The conductive structures 130 a , 130 b , and 130 c are respectively located on the redistribution layer 127 in the opening 129 .

In this embodiment, the diameters of the openings 129 of the protective layer 128 are substantially the same, but the volumes of the conductive structures 130a, 130b, and 130c are different. The volume of the conductive structure 130a is smaller than the volume of the conductive structure 130b, and the volume of the conductive structure 130b is smaller than the volume of the conductive structure 130c, so the height H1 of the conductive structure 130a is smaller than the height H2 of the conductive structure 130b, and the height H2 of the conductive structure 130b is smaller than the conductive structure 130c The height H3.

FIG. 5 shows a cross-sectional view of a semiconductor device 120 a according to another embodiment of the present invention, and the cross-sectional position is the same as that in FIG. 4 . The semiconductor device 120 a includes a semiconductor substrate 1201 , an insulating layer 126 , a redistribution layer 127 and a protection layer 128 . The difference from the embodiment in FIG. 4 is that in this embodiment, the openings 129a, 129b, 129c of the protective layer 128 have diameters that gradually decrease from the central region 122 of the semiconductor element 120a to the edge region 124 of the semiconductor element 120a, and are conductive The volumes of the structures 130a, 130b, 130c are approximately the same.

Since the aperture of the opening 129a of the protective layer 128 is larger than the aperture of the opening 129b, and the aperture of the opening 129b is larger than the aperture of the opening 129c, the height H1 of the conductive structure 130a is smaller than the height H2 of the conductive structure 130b, and the height H2 of the conductive structure 130b is smaller than that of the conductive structure. Height H3 of 130c.

FIG. 6 is a flowchart of a method for manufacturing a chip package according to an embodiment of the present invention. The manufacturing method of the chip package includes the following steps. In step S1, a plurality of conductive structures with different heights are formed on the semiconductor element, wherein the height of the conductive structures gradually increases from the central area of the semiconductor element to the edge area of the semiconductor element, as shown in FIG. 2 . Next, in step S2 , the semiconductor element is pressed on the packaging substrate, so that the semiconductor element is supported by the conductive structure and bends, such as the semiconductor element shown in FIG. 1 .

4, in the step of forming conductive structures 130a, 130b, 130c of different heights on the semiconductor element 120, the conductive colloid can be printed onto the semiconductor element 120 from the printing nozzles with different opening diameters by adjusting the opening diameter of the printing nozzles. , so as to form conductive structures 130a, 130b, 130c with different heights. In this embodiment, the apertures of the openings 129 of the protective layer 128 are approximately the same, but the volumes of the conductive colloid printed into the openings 129 are different, so that the conductive structures 130a, 130b, and 130c with different heights can be formed after the conductive colloid is cured. In this embodiment, it is applicable to a solder ball printing (ball printing) process.

Referring to FIG. 5 , in the step of forming conductive structures 130 a , 130 b , 130 c with different heights on the semiconductor device 120 a , a protection layer 128 may be formed on the redistribution layer 127 of the semiconductor device 120 a. Then a plurality of openings 129a, 129b, 129c with different diameters can be formed in the protective layer 128, wherein the diameters of the openings 129a, 129b, 129c gradually decrease from the central region 122 of the semiconductor device 120a to the edge region 124 of the semiconductor device 120a. After that, a plurality of conductive structures 130 a , 130 b , 130 c can be placed on the redistribution layer 127 in the openings 129 a , 129 b , 129 c of the passivation layer 128 . In this embodiment, the conductive structures 130a, 130b, and 130c have the same volume, but the shapes of the conductive structures 130a, 130b, and 130c can be restricted by the openings 129a, 129b, and 129c of the protective layer 128 with different diameters to form different heights. Conductive structures 130a, 130b, 130c. For example, the large opening 129a of the passivation layer 128 can form a short conductive structure 130a, and the small opening 129c of the passivation layer 128 can form a tall conductive structure 130c. In this embodiment, it is applicable to a ball placement process.

It should be understood that the connection relationship, materials, and manufacturing methods of the components that have been described will not be repeated. In the following description, other steps of the manufacturing method of the chip package will be described.

FIG. 7 is a cross-sectional view of a semiconductor substrate 1201 after forming a hollow region 125 according to an embodiment of the present invention. The semiconductor substrate 1201 can be temporarily bonded to the carrier 210 by an adhesive tape 220 (such as double-sided tape). Then, the surface 121b of the semiconductor substrate 1201 can be ground to reduce the thickness of the semiconductor substrate 1201 . After that, the hollow area 125 can be formed in the semiconductor substrate 1201 by etching, so that the bonding pad 123 is exposed from the hollow area 125 .

FIG. 8 is a cross-sectional view of the semiconductor substrate 1201 in FIG. 7 after the insulating layer 126 and the redistribution layer 127 are formed. After the hollow area 125 is formed, an insulating layer 126 can be formed on the surface 121 b of the semiconductor substrate 1201 and the surface surrounding the hollow area 125 . Next, a redistribution layer 127 may be formed in the insulating layer 126 and the hollow area 125 , so that the redistribution layer 127 is electrically connected to the pad 123 .

FIG. 9 shows a cross-sectional view of the insulating layer 126 and the redistribution layer 127 in FIG. 8 after forming a protection layer 128 . Referring to FIG. 8 and FIG. 9 at the same time, after the redistribution layer 127 is formed, an etching or laser process can be used to form a gap in the semiconductor substrate 1201 . Then, the passivation layer 128 can be formed on the insulating layer 126 and the redistribution layer 127 .

FIG. 10 is a cross-sectional view of the redistribution layer 127 of FIG. 9 after the conductive structure 130 is formed. Referring to FIG. 9 and FIG. 10 simultaneously, the passivation layer 128 may be patterned to form openings 129 . After the opening 129 of the passivation layer 128 is formed, the conductive structure 130 can be formed on the redistribution layer 127 in the opening 129 . The number of the conductive structures 130 is not intended to limit the present invention. Wherein, the design of the conductive structure 130 and the opening 129 of the protective layer 128 may be as shown in FIG. 4 , or as shown in FIG. 5 , and will not be repeated here.

FIG. 11 is a cross-sectional view of the carrier 210 in FIG. 10 when removed. Referring to FIG. 10 and FIG. 11 at the same time, after the conductive structure 130 is formed, the protective layer 128 and the adhesive tape 220 above the gap in FIG. 10 can be pre-sawed. Next, the pre-cut structure can be placed on the tape 230 and the carrier 210 can be separated from the tape 220 .

FIG. 12 is a cross-sectional view when the adhesive tape 230 of FIG. 11 is removed. Referring to FIG. 10 and FIG. 11 at the same time, after the carrier 210 is separated, the tape 240 can be attached to the tape 220 on the semiconductor substrate 1201 , and then the tape 230 can be removed from the conductive structure 130 . In subsequent processes, the adhesive tapes 220 and 240 on the semiconductor substrate 1201 of FIG. 12 can be removed to obtain the semiconductor device 120 of FIG. 4 or the semiconductor device 120a of FIG. 5 .

The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person familiar with this technology can make further improvements on this basis without departing from the spirit and scope of the present invention. Improvements and changes, so the protection scope of the present invention should be defined by the claims of the present application.

Claims (11)

1. a kind of wafer encapsulation body, which is characterized in that include：

One encapsulation base material；

Semiconductor element, with a central area and the marginal zone for surrounding the central area；And

Multiple conductive structures, between the encapsulation base material and the semiconductor element, wherein the conductive structure is with different Highly, and the height of the conductive structure from the central area of the semiconductor element toward the marginal zone of the semiconductor element gradually Increase, so that the distance between the marginal zone of the semiconductor element and the encapsulation base material are greater than the center of the semiconductor element The distance between area and the encapsulation base material.

2. wafer encapsulation body according to claim 1, which is characterized in that the plan view shape of the conductive structure includes circle Shape, ellipse, polygon or combinations of the above.

3. wafer encapsulation body according to claim 1, which is characterized in that the semiconductor element has semiconductor substrate, The semiconductor substrate has a weld pad and a vacancy section, and the weld pad is exposed from the vacancy section, which also includes：

One insulating layer, positioned at the semiconductor substrate towards on the surface of the encapsulation base material and the semiconductor substrate surrounds the vacancy section Surface on.

4. wafer encapsulation body according to claim 3, which is characterized in that the semiconductor element also includes：

One reroutes layer, is located on the insulating layer and on the weld pad.

5. wafer encapsulation body according to claim 4, which is characterized in that the semiconductor element also includes：

One protective layer is located on the rewiring layer and on the insulating layer, and the protective layer has multiple openings, makes the rewiring layer It is exposed from the opening.

6. wafer encapsulation body according to claim 5, which is characterized in that the conductive structure is located in the opening The rewiring layer on.

7. wafer encapsulation body according to claim 5, which is characterized in that the bore of the opening is from the semiconductor element The marginal zone of the central area toward the semiconductor element is gradually reduced.

8. a kind of production method of wafer encapsulation body, which is characterized in that include：

A) in the multiple conductive structures for forming different height on semiconductor element, wherein the height of the conductive structure from this half One marginal zone of one central area of conductor element toward the semiconductor element is gradually increased；And

B) in pressing the semiconductor element on an encapsulation base material, so that the semiconductor element is supported and curved by the conductive structure It is bent.

9. the production method of wafer encapsulation body according to claim 8, wherein step a) includes：

The bore for adjusting the opening of a print nozzles prints a conductive rubber to this from the print nozzles of different openings bore On semiconductor element, to form the conductive structure of tool different height.

10. the production method of wafer encapsulation body according to claim 8, which is characterized in that also include：

It is rerouted in the one of the semiconductor element and forms a protective layer on layer；And

Multiple openings of different bores are formed in the protective layer, wherein the bore of the opening is from the center of the semiconductor element The marginal zone of area toward the semiconductor element is gradually reduced.

11. the production method of wafer encapsulation body according to claim 10, which is characterized in that step a) includes：

The conductive structure is placed on the rewiring layer in the opening of the protective layer.