CN105739202A - Array base plate and display device - Google Patents
Array base plate and display device Download PDFInfo
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- CN105739202A CN105739202A CN201610306246.0A CN201610306246A CN105739202A CN 105739202 A CN105739202 A CN 105739202A CN 201610306246 A CN201610306246 A CN 201610306246A CN 105739202 A CN105739202 A CN 105739202A
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- clk
- cabling
- array base
- branch line
- base palte
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses an array base plate and a display device, and belongs to the field of a display. The array base plate comprises a plurality of array base plate line driving GOA (gate drive on array) units, a plurality of CLK (clock) wires and a plurality of middle lead wires, wherein the CLK wires and the middle lead wires are arranged in different layers; each GOA unit in the plurality of GOA units is connected with K CLK wires in the plurality of CLK wires through K middle lead wires in the plurality of middle lead wires; each middle lead wire is only connected with one GOA unit and one CLK wire; the K is an even number being greater than 0; the array base plate also comprises a plurality of CLK branch wires; the two ends of each CLK wire in the plurality of CLK wires are respectively connected with the two ends of at least one CLK branch wire in the plurality of CLK branch wires; each CLK branch wire in the plurality of CLK branch wires is only connected with one CLK wire in the plurality of CLK wires; the plurality of CLK wires are arranged between the plurality of CLK branch wires and the GOA units. The problem of different time delay of clock signal transmission of each CLK wire can be solved. The quality of a displayed image is improved.
Description
Technical field
The present invention relates to field of display, pull and display device particularly to a kind of array base.
Background technology
Array base palte row cutting (GateDriveonArray, it being called for short GOA) technology is a kind of by liquid crystal display (LiquidCrystalDisplay, be called for short LCD) raster data model (GateDriver) integrated circuit (IntegratedCircuit, be called for short IC) be integrated in a kind of technology on array (Array) substrate.
The array base palte adopting this technology generally includes the drive circuit area beyond pixel display area and pixel display area.Wherein, it is connected that pixel display area is provided with multirow pixel cell, each row pixel cell and a grid line.Drive circuit area is generally provided with multiple GOA unit, middle leads and conveying clock (Clock is called for short CLK) the signal CLK cabling to GOA unit.Multiple GOA unit are arranged on the same side of pixel display area and arrange along the direction (abbreviation vertical direction) vertical with grid line.Each GOA unit is connected with the grid line of one-row pixels unit by going between.Many CLK cablings are set in parallel in the outside (i.e. the opposition side of pixel display area) of GOA unit, and every CLK cabling vertically extends, and GOA unit is connected with corresponding CLK cabling by middle leads.
In above-mentioned wire structures, middle leads is when connecting CLK cabling and GOA unit, meeting intersects with the CLK cabling between the CLK cabling being connected and GOA unit, owing to CLK cabling and middle leads are arranged on different layers, therefore parasitic capacitance can be produced at middle leads and CLK cabling infall.
Parasitic capacitance on CLK cabling is distributed along the bearing of trend of CLK cabling, therefore the clock signal transmission on a CLK cabling is to time proximally and distally, due to the difference of the parasitic capacitance quantity on the circuit of process, cause that the delay being transferred to proximally and distally differs greatly；Additionally, the parasitic capacitance quantity on CLK cabling that the quantity of the parasitic capacitance on distance GOA unit CLK cabling farther out is nearer less than distance GOA unit, causing that different CLK cabling is when by clock signal transmission to same distance, transmission delay is also different, largely effects on the quality of display picture.
Summary of the invention
Proximally and distally postpone, to CLK cabling, the problem that difference is very big and between each CLK cabling, signal transmission delay is different in order to solve a CLK cabling transfer clock signal, embodiments provide a kind of array base palte and display device.Described technical scheme is as follows:
nullFirst aspect，Embodiments provide a kind of array base palte，Described array base palte includes multiple array base palte row cutting GOA unit、Many clock CLK cablings and many middle leads，Described CLK cabling is arranged with described middle leads different layers，Each GOA unit in the plurality of GOA unit is connected with the K root CLK cabling in described many CLK cablings by the K root middle leads in described many middle leads，And every described middle leads only connects a described GOA unit and a described CLK cabling，K more than 0 and K be even number，Described array base palte also includes many CLK branch lines，The two ends of every CLK cabling in described many CLK cablings connect the two ends of at least one CLK branch line in described many CLK branch lines respectively，And every CLK branch line in described many CLK branch lines is only connected with a CLK cabling in described many CLK cablings，Described many CLK cablings are arranged between described many CLK branch lines and described GOA unit.
In a kind of implementation of the embodiment of the present invention, described many CLK cablings and described many CLK branch lines all be arranged in parallel.
In the another kind of implementation of the embodiment of the present invention, described many CLK branch lines include the 1-M root CLK branch line being arranged in order according to distance GOA unit order from the near to the remote, described many CLK cablings include according to distance GOA unit by the 1-M root CLK cabling being arranged in order as far as near order, nth root CLK branch line is connected with nth root CLK cabling, M is the integer more than 1, M >=N >=1 and N is integer.
In the another kind of implementation of the embodiment of the present invention, the far-end of described CLK branch line is connected with layer with the far-end of described CLK cabling.
In the another kind of implementation of the embodiment of the present invention, the near-end proximally by via with described CLK cabling of described CLK branch line is connected.
In the another kind of implementation of the embodiment of the present invention, described array base palte also includes branch line lead-in wire, and described branch line lead-in wire connects described CLK branch line and described CLK cabling by via.
In the another kind of implementation of the embodiment of the present invention, described many CLK cablings are connected in the middle part of the CLK branch line of two ends connection and CLK cabling with in described many CLK branch lines.
In the another kind of implementation of the embodiment of the present invention, described CLK branch line and be correspondingly arranged on the corresponding junction point of 1 to 3 junction point, described CLK branch line and described CLK cabling in the middle part of described CLK cabling respectively and be connected.
In the another kind of implementation of the embodiment of the present invention, the plurality of GOA unit and Duo Gen CLK cabling are arranged on both sides, pixel display area.
In the another kind of implementation of the embodiment of the present invention, described each GOA unit is connected with two CLK cablings in described many CLK cablings respectively through two middle leads in described many middle leads.
Second aspect, embodiments provides a kind of display device, and described display device includes the array base palte described in any one of first aspect.
The technical scheme that the embodiment of the present invention provides has the benefit that
The present invention is by arranging many CLK branch lines, many CLK cablings are at least connected with a CLK branch line, owing to CLK branch line is only proximally and distally being connected with CLK cabling, on CLK branch line, parasitic capacitance is few, make the CLK signal that CLK cabling inputs can pass through CLK branch line and quickly arrive CLK cabling far-end, make the clock signal transmission on a CLK cabling only small to delay difference proximally and distally, and owing to the electric capacity on the CLK branch line that is connected with every CLK cabling is all only small, signal transmission delay is suitable, solve the problem that each CLK cabling transfer clock signal time delay differs late, improve display picture quality.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme in the embodiment of the present invention, below the accompanying drawing used required during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural representation of a kind of array base palte that the embodiment of the present invention provides；
Fig. 2 is the structural representation of the another kind of array base palte that the embodiment of the present invention provides.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.
Fig. 1 is the structural representation of a kind of array base palte that the embodiment of the present invention provides, referring to Fig. 1, array base palte includes multiple GOA unit 101, many CLK cablings 102 and many middle leads 103, CLK cabling 102 is arranged with middle leads 103 different layers, each GOA unit 101 in the plurality of GOA unit 101 is connected with the K root CLK cabling 102 in described many CLK cablings 102 by the K root middle leads 103 in described many middle leads 103, and every middle leads 103 connect GOA unit 101 and CLK cabling 102, K more than 0 and K be even number.
Array base palte also includes many CLK branch lines 104, the two ends of every CLK cabling 102 in many CLK cablings 102 connect the two ends of at least one CLK branch line 104 in many CLK branch lines 104 respectively, and every CLK branch line 104 in many CLK branch lines 104 is only connected with a CLK cabling 102 in many CLK cablings 102, many CLK cablings 102 are arranged between many CLK branch lines 104 and GOA unit 101.
The present invention is by arranging many CLK branch lines 104, many CLK cablings 102 are at least connected with a CLK branch line 104, owing to CLK branch line 104 is only proximally and distally being connected with CLK cabling 102, on CLK branch line 104, parasitic capacitance is few, make the CLK signal that CLK cabling 102 inputs can pass through CLK branch line 104 and quickly arrive CLK cabling 102 far-end, make the clock signal transmission on a CLK cabling 102 only small to delay difference proximally and distally, and owing to the electric capacity on the CLK branch line 104 that is connected with every CLK cabling 102 is all only small, signal transmission delay is suitable, solve the problem that each CLK cabling 102 transfer clock signal time delay differs late, improve display picture quality.
As it is shown in figure 1, multiple GOA unit 101 and Duo Gen CLK cabling 102 can be arranged on the both sides, pixel display area of array base palte.This setup is only for example, and multiple GOA unit 101 and Duo Gen CLK cabling 102 can also be arranged on the side of pixel display area.
Array base palte shown in Fig. 1, two CLK cablings 102 are connected with each GOA unit, every CLK cabling 102 connects a CLK branch line 104 for example, and wherein two CLK cabling 102 respectively GOA unit 101 provide a positive CLK signal and an anti-phase CLK signal.Certainly, GOA unit 101 can also connect 4,6,8 even more CLK cablings 102, the CLK cabling of connection 102 two one group, and one group of CLK cabling 102 is used for providing a positive CLK signal and an anti-phase CLK signal.A piece CLK cabling 102 can also connect many CLK branch lines 104, but the quantity of the CLK branch line 104 of every CLK cabling 102 connection is identical, for convenient wiring, it is preferred to use a CLK cabling 102 connects a CLK branch line 104.
Wherein, CLK cabling 102 and middle leads 103 are arranged on different layers, and middle leads 103 connects CLK cabling 102 by via, in Fig. 1 shown in circular stain.
It should be noted that the quantity of the GOA unit 101 in Fig. 1 is only for example, the embodiment of the present invention is without limitation.
As it is shown in figure 1, many CLK cablings 102 be arranged in parallel, every CLK branch line 104 all be arranged in parallel with CLK cabling 102.By CLK branch line 104 and CLK cabling 102 being be arranged in parallel, ensure that CLK branch line 104 does not intersect with CLK cabling 102, on the other hand, facilitates CLK branch line 104 to connect up on the one hand.
Further, each GOA unit 101 is connected with a grid line of pixel display area, and multiple GOA unit 101 of the same side, pixel display area are perpendicular to the direction arrangement of grid line, and above-mentioned CLK cabling 102 bearing of trend is identical with the orientation of multiple GOA unit 101.
In embodiments of the present invention, CLK branch line 104 is arranged with layer with CLK cabling 102, thus facilitating the making of array base palte.
In a kind of implementation of the present invention, many CLK cablings 102 are as follows with the order of connection of many CLK branch lines 104: many CLK branch lines 104 include the 1-M root CLK branch line 104 that the order of according to distance GOA unit 101 (or by as far as near) from the near to the remote is arranged in order, many CLK cablings 102 include the 1-M root CLK cabling 102 being arranged in order according to distance GOA unit 101 by the order as far as nearly (or from the near to the remote), nth root CLK branch line 104 is connected with nth root CLK cabling 102, M is the integer more than 1, M >=N >=1 and N is integer.This connection design can conveniently connect up.
nullAs shown in Figure 1，Array base palte includes the 4 CLK branch line 104:CLK1a (i.e. first CLK branch line) being arranged in order according to distance GOA unit 101 order from the near to the remote、CLK2a (i.e. second CLK branch line)、CLK3a (i.e. the 3rd CLK branch line) and CLK4a (i.e. the 4th CLK branch line)，According to distance GOA unit 101 by the 4 CLK cabling 102:CLK1A (i.e. first CLK cabling) being arranged in order as far as near order、CLK2A (i.e. second CLK cabling)、CLK3A (i.e. the 3rd CLK cabling) and CLK4A (i.e. the 4th CLK cabling)，CLK1a and CLK1A connects，CLK2a and CLK2A connects，CLK3a and CLK3A connects，CLK4a and CLK4A connects.
As it is shown in figure 1, CLK branch line 104 is directly connected to CLK cabling 102 at far-end, namely the far-end of CLK branch line 104 is connected with layer with the far-end of CLK cabling 102.CLK branch line 104 is directly connected with CLK cabling 102 at CLK cabling 102 far-end, it is to avoid offers via, can save making step, can reduce again parasitic capacitance.Wherein, the far-end of CLK cabling 102 is CLK cabling 102 apart from printed circuit board (PrintedCircuitBoard is called for short PCB) one end farther out of LCD, and the far-end of CLK branch line 104 is CLK branch line 104 apart from PCB one end farther out of LCD.
The near-end of CLK cabling 102 is one end nearer for PCB of distance LCD, and CLK cabling 102 is connected with PCB, is used for receiving CLK signal input.Owing to the near-end of CLK cabling 102 needs the printed circuit board (PrintedCircuitBoard with LCD, it is called for short PCB) connect, if therefore adopting the mode connected with layer, the near-end of CLK cabling 102 can cause existing between circuit intersecting, so directly cannot be connected with CLK branch line 104 as far-end.Therefore in the present embodiment, the near-end proximally by via with CLK cabling 102 of CLK branch line 104 is connected.CLK cabling 102 and CLK branch line 104 is connected, it is to avoid cross-cutting issue occurs in circuit by via.
Specifically, array base palte also includes branch line lead-in wire 105, and branch line lead-in wire 105 connects CLK branch line 104 and CLK cabling 102 by via.Realize via by branch line to connect, it is to avoid crossing elimination.
Further, many CLK cablings 102 are connected in the middle part of the CLK branch line 104 of two ends connection and CLK cabling 102 with in Duo Gen CLK branch line 104.CLK branch line 104 is connected with CLK cabling 102 in the middle part of CLK cabling 102, accelerates clock signal transmission to the speed in the middle part of CLK cabling 102, and further equalized clock signal is transferred to the delay of each position of CLK cabling 102.
Wherein, CLK branch line 104 and be correspondingly arranged on 1 to 3 junction point (such as 1 shown in Fig. 1 junction point) in the middle part of CLK cabling 102 respectively, CLK branch line 104 is connected by corresponding junction point with in the middle part of CLK cabling 102.The position connected is up to 3 places, it is to avoid link position is too much, causes the problem that on CLK branch line 104, electric capacity is excessive.When being connected by more than one junction point in the middle part of CLK branch line 104 and CLK cabling 102, junction point uniform intervals is distributed on CLK branch line 104 and CLK cabling 102.
In the another kind of implementation of the present invention, the order of connection of many CLK cablings 102 and Duo Gen CLK branch line 104, it is also possible to the mode not being connected with nth root CLK cabling 102 according to nth root CLK branch line 104 carries out.
As in figure 2 it is shown, CLK1a and CLK2A connects, CLK2a and CLK1A connects, and CLK3a and CLK3A connects, and CLK4a and CLK3A connects.
This mode of Fig. 2 makes CLK cabling 102 and CLK branch line 104 cannot connect with layer at far-end, and therefore in the connected mode of Fig. 2, CLK cabling 102 and CLK branch line 104 are connected by via at far-end.
Secondly, in the connected mode shown in Fig. 2, CLK cabling 102 and CLK branch line 104 do not connect at middle part.
Preferably, CLK branch line 104 can be identical with the material of CLK cabling 102, for instance adopts gate metal to make.Adopt identical material to make CLK cabling 102 and CLK branch line 104, facilitate the making of array base palte.Certainly, the material of CLK branch line 104 and CLK cabling 102 can also differ.
Preferably, CLK branch line 104 can be identical with the thickness of CLK cabling 102.CLK branch line 104 and CLK cabling 102 are designed to same thickness, it is simple to the making of array base palte.Certainly, the thickness of CLK branch line 104 and CLK cabling 102 can also differ.
In embodiments of the present invention, branch line lead-in wire 105 can be arranged with layer with middle leads 103, facilitates the making of array base palte.
Preferably, branch line lead-in wire 105 can be identical with the material of middle leads 103, for instance adopts tin indium oxide (IndiumTinOxide is called for short ITO) to make.Adopt identical material to make branch line lead-in wire 105 and middle leads 103, facilitate the making of array base palte.Certainly, the material of branch line lead-in wire 105 and middle leads 103 can also differ.
Preferably, branch line lead-in wire 105 can be identical with the thickness of middle leads 103.Branch line lead-in wire 105 and middle leads 103 are designed to same thickness, it is simple to the making of array base palte.Certainly, the thickness of branch line lead-in wire 105 and middle leads 103 can also differ.
The embodiment of the present invention additionally provides a kind of display device, and this display device includes Fig. 1 or array base palte illustrated in fig. 2.
In the specific implementation, the display device that the embodiment of the present invention provides can be any product with display function or the parts such as mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
The present invention is by arranging many CLK branch lines, many CLK cablings are at least connected with a CLK branch line, owing to CLK branch line is only proximally and distally being connected with CLK cabling, on CLK branch line, parasitic capacitance is few, make the CLK signal that CLK cabling inputs can pass through CLK branch line and quickly arrive CLK cabling far-end, make the clock signal transmission on a CLK cabling only small to delay difference proximally and distally, and owing to the electric capacity on the CLK branch line that is connected with every CLK cabling is all only small, signal transmission delay is suitable, solve the problem that each CLK cabling transfer clock signal time delay differs late, improve display picture quality.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all within the spirit and principles in the present invention, any amendment of making, equivalent replacement, improvement etc., should be included within protection scope of the present invention.
Claims (11)
- null1. an array base palte，It is characterized in that，Described array base palte includes multiple array base palte row cutting GOA unit、Many clock CLK cablings and many middle leads，Described CLK cabling is arranged with described middle leads different layers，Each GOA unit in the plurality of GOA unit is connected with the K root CLK cabling in described many CLK cablings by the K root middle leads in described many middle leads，And every described middle leads only connects a described GOA unit and a described CLK cabling，K more than 0 and K be even number，It is characterized in that，Described array base palte also includes many CLK branch lines，The two ends of every CLK cabling in described many CLK cablings connect the two ends of at least one CLK branch line in described many CLK branch lines respectively，And every CLK branch line in described many CLK branch lines is only connected with a CLK cabling in described many CLK cablings，Described many CLK cablings are arranged between described many CLK branch lines and described GOA unit.
- 2. array base palte according to claim 1, it is characterised in that described many CLK cablings and described many CLK branch lines all be arranged in parallel.
- 3. array base palte according to claim 2, it is characterized in that, described many CLK branch lines include the 1-M root CLK branch line being arranged in order according to distance GOA unit order from the near to the remote, described many CLK cablings include according to distance GOA unit by the 1-M root CLK cabling being arranged in order as far as near order, nth root CLK branch line is connected with nth root CLK cabling, M is the integer more than 1, M >=N >=1 and N is integer.
- 4. array base palte according to claim 3, it is characterised in that the far-end of described CLK branch line is connected with layer with the far-end of described CLK cabling.
- 5. array base palte according to claim 1, it is characterised in that the near-end proximally by via with described CLK cabling of described CLK branch line is connected.
- 6. array base palte according to claim 5, it is characterised in that described array base palte also includes branch line lead-in wire, and described branch line lead-in wire connects described CLK branch line and described CLK cabling by via.
- 7. array base palte according to claim 1, it is characterised in that described many CLK cablings are connected in the middle part of the CLK branch line of two ends connection and CLK cabling with in described many CLK branch lines.
- 8. array base palte according to claim 7, it is characterised in that described CLK branch line and be correspondingly arranged on the corresponding junction point of 1 to 3 junction point, described CLK branch line and described CLK cabling in the middle part of described CLK cabling respectively and be connected.
- 9. array base palte according to claim 1, it is characterised in that the plurality of GOA unit and Duo Gen CLK cabling are arranged on both sides, pixel display area.
- 10. array base palte according to claim 1, it is characterised in that described each GOA unit is connected with two CLK cablings in described many CLK cablings respectively through two middle leads in described many middle leads.
- 11. a display device, it is characterised in that described display device includes the array base palte described in any one of claim 1-10.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610306246.0A CN105739202A (en) | 2016-05-10 | 2016-05-10 | Array base plate and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610306246.0A CN105739202A (en) | 2016-05-10 | 2016-05-10 | Array base plate and display device |
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| CN105739202A true CN105739202A (en) | 2016-07-06 |
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| CN201610306246.0A Pending CN105739202A (en) | 2016-05-10 | 2016-05-10 | Array base plate and display device |
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| CN111624827A (en) * | 2020-06-28 | 2020-09-04 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
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| US12222612B2 (en) | 2020-06-28 | 2025-02-11 | Hefei Boe Display Technology Co., Ltd. | Array substrate, display panel, and display apparatus |
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Application publication date: 20160706 |