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CN105719701B - Semiconductor memory device and method of operating the same - Google Patents

Semiconductor memory device and method of operating the same Download PDF

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Publication number
CN105719701B
CN105719701B CN201510455742.8A CN201510455742A CN105719701B CN 105719701 B CN105719701 B CN 105719701B CN 201510455742 A CN201510455742 A CN 201510455742A CN 105719701 B CN105719701 B CN 105719701B
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data
semiconductor memory
memory system
program
read
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CN105719701A (en
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李炯珉
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SK Hynix Inc
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SK Hynix Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/024—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction

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  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Computer Hardware Design (AREA)

Abstract

The present invention relates to an operating method of a semiconductor memory system, including: performing first Error Correction Code (ECC) decoding on first data stored in the semiconductor memory system, wherein the first data includes user data, ECC data for the user data, and status data for the user data; and performing a second ECC decoding on the user data by changing the read voltage based on the state data of the first data when the first ECC decoding on the user data fails. The invention also relates to a semiconductor memory system and a controller.

Description

Semiconductor memory device and method of operating the same
Cross Reference to Related Applications
This application claims priority from korean patent application No. 10-2014-.
Technical Field
Various exemplary embodiments of the present invention relate to a semiconductor memory system, and more particularly, to a semiconductor memory system capable of improving reliability of data reading and an operating method thereof.
Background
A nonvolatile semiconductor memory device such as a flash memory device maintains data stored in a memory block despite power failure. The nonvolatile semiconductor memory device is capable of repeatedly storing data in a memory block by repeatedly performing operations of programming and erasing data. The number of program/erase cycles represents the number of repetitions of such program and erase operations. A single program/erase cycle includes a single program operation and a single erase operation. As the program operation and the erase operation are repeatedly performed, the number of program/erase cycles may increase.
The number of program/erase cycles may be divided into a plurality of program/erase cycle groups with reference to a program voltage. In addition, the number of program/erase cycles may be divided into a plurality of read-retry groups with reference to the read voltage.
Fig. 1A is a table illustrating a set of program/erase cycles suitable for data programming in a semiconductor memory device. Fig. 1B is a table illustrating a read-retry group suitable for data reading in a semiconductor memory device.
Referring to fig. 1A, the program/erase cycle groups may include first to fifth program/erase cycle groups PGr1, PGr2, PGr3, PGr4 and PGr 5. For example, the first program/erase cycle group PGr1 may represent a number of program/erase cycles ranging from 0K to 0.2K, the second program/erase cycle group PGr2 may represent a number of program/erase cycles ranging from 0.2K to 0.5K, the third program/erase cycle group PGr3 may represent a number of program/erase cycles ranging from 0.5K to 1K, the fourth program/erase cycle group PGr4 may represent a number of program/erase cycles ranging from 1K to 2K, and the fifth program/erase cycle group PGr5 may represent a number of program/erase cycles ranging from 2K to 3K.
Each of the first to fifth program/erase cycle groups PGr1, PGr2, PGr3, PGr4 and PGr5 includes a plurality of indexes indicating addresses of memory blocks. The plurality of indexes may respectively correspond to the plurality of program voltages PVL. For example, the indexes 0 to n of the first program/erase cycle group PGr1 may correspond to values of program voltages PV10 to PV1n respectively applied to the 0 th to nth memory blocks during data programming. The indexes 0 to n of the second program/erase cycle group PGr2 may correspond to values of program voltages PV20 to PV2n applied during data programming. The indexes 0 to n of the third program/erase cycle group PGr3 may correspond to values of program voltages PV30 to PV3n applied during data programming. The indexes 0 to n of the fourth program/erase cycle group PGr4 may correspond to values of program voltages PV40 to PV4n applied during data programming. The indexes 0 to n of the fifth program/erase cycle group PGr5 may correspond to values of program voltages PV50 to PV5n applied during data programming.
Referring to fig. 1B, the read-retry groups may include first to fifth read-retry groups RGr1, RGr2, RGr3, RGr4, and RGr 5. The first to fifth read-retry groups RGr1, RGr2, RGr3, RGr4, and RGr5 correspond to the first to fifth program/erase cycle groups PGr1, PGr2, PGr3, PGr4, and PGr5, respectively.
For example, first read-retry group RGr1 may represent a number of program/erase cycles ranging from 0 to 0.2K, second read-retry group RGr2 may represent a number of program/erase cycles ranging from 0.2K to 0.5K, third read-retry group RGr3 may represent a number of program/erase cycles ranging from 0.5K to 1K, fourth read-retry group RGr4 may represent a number of program/erase cycles ranging from 1K to 2K, and fifth read-retry group RGr5 may represent a number of program/erase cycles ranging from 2K to 3K.
Each of the first to fifth read-retry groups RGr1, RGr2, RGr3, RGr4, and RGr5 includes an index 0 to an index n, respectively. Each of the indexes 0 to n may correspond to values of a plurality of read voltages respectively applied to the 0 th to nth memory blocks during data read of a multi-level cell (MLC) flash memory device. For example, the 0 th index (index 0) may correspond to 3 values RV10, RV20, and RV30 of read voltages REVL1, REVL2, and REVL3 applied to the 0 th memory block during data read of the MLC. The 1 st index (index 1) may correspond to 3 values RV11, RV21, and RV31 of read voltages REVL1, REVL2, and REVL3 applied to the 1 st memory block during data read of the MLC. The nth index (index n) may correspond to 3 values RV1n, RV2n, and RV3n of read voltages REVL1, REVL2, and REVL3 applied to the nth memory block during data read of the MLC.
A plurality of program/erase cycle groups and a plurality of read-retry groups may be managed in units of memory chips.
A mismatch may occur when data is programmed in the semiconductor memory device using the first to fifth program/erase cycle groups PGr1, PGr2, PGr3, PGr4 and PGr5 and then data is read from the semiconductor memory device using the first to fifth read-retry groups RGr1, RGr2, RGr3, RGr4 and RGr 5.
For example, when the number of program/erase cycles of the memory chip is 499, a data program operation is performed on a first memory block in the memory chip using the second program/erase cycle group PGr 2. Thereafter, when the program/erase cycle number of the memory chip is adapted to be 501 due to a further program operation on the same memory chip, a data program operation is performed on a third memory block of the same memory chip using the third program/erase cycle group PGr 3. That is, the data program operation is performed on the first and third memory blocks of the same memory chip using the second and third program/erase cycle groups PGr2 and PGr3, which are different from each other, according to the program/erase cycle number.
Thereafter, during a data read operation for the first memory block, data is read from the first memory block with reference to the third read-retry group RGr3 when the number of program/erase cycles for the memory chip is below 999.
A read failure of the first memory block may occur because data is programmed to the first memory block using the second program/erase cycle group PGr2 and the programmed data is read from the first memory block with reference to the third read-retry group RGr 3. That is, a read failure of the first memory block may occur due to a difference between a program condition and a read condition.
As described above, a read failure may occur when the program condition and the read condition are different from each other. Therefore, a stable operation of the semiconductor memory device may not be performed, deteriorating characteristics of the semiconductor memory device.
Disclosure of Invention
Various embodiments of the present invention are directed to a semiconductor memory system capable of reliably reading data and an operating method thereof.
According to an embodiment of the present invention, an operating method of a semiconductor memory system may include: performing first Error Correction Code (ECC) decoding on first data stored in the semiconductor memory system, wherein the first data includes user data, ECC data for the user data, and status data for the user data; and performing a second ECC decoding on the user data by changing the read voltage based on the state data of the first data when the first ECC decoding on the user data fails.
The state data may include information of a program voltage used when the first data is stored in the semiconductor memory system.
The information of the program voltage may be an index corresponding to one of a plurality of program voltage groups, each of the plurality of program voltage groups being a group of program voltages for storing data into the semiconductor memory system, and each of the plurality of program voltage groups being indexed.
The second step may perform a second ECC decoding on the user data according to one or more read-retry voltages corresponding to the index and by means of read-retry.
The semiconductor memory system may be a multi-level cell (MLC) memory system.
The state data may be Least Significant Bit (LSB) data.
Most Significant Bit (MSB) data corresponding to the state data may have a "FF" value.
The state data may include information of a plurality of program voltages used when the first data is stored in the semiconductor memory system.
The semiconductor memory system may include a state data storage area.
An index of a data cell for a program operation and state data of the data cell are stored in the state data storage region.
According to an embodiment of the present invention, a semiconductor memory system may include: a semiconductor memory device; and a controller, wherein the controller includes a first device performing a first ECC decoding on user data of first data stored in the semiconductor memory system, wherein the first data includes the user data, ECC data for the user data, and state data for the user data; and a second device performing a second ECC decoding on the user data by changing the read voltage based on the state data of the first data when the first ECC decoding on the user data fails.
The state data may include information of a program voltage used when the first data is stored in the semiconductor memory system.
The information of the program voltage may be an index corresponding to one of a plurality of program voltage groups, each of the plurality of program voltage groups being a group of program voltages for storing data into the semiconductor memory system, and each of the plurality of program voltage groups being indexed.
The second device may perform a second ECC decoding on the user data according to one or more read-retry voltages corresponding to the index and by way of read-retry.
The semiconductor memory system may be a multi-level cell (MLC) memory system.
The state data may be Least Significant Bit (LSB) data.
Most Significant Bit (MSB) data corresponding to the state data may have a "FF" value.
The state data may include information of a plurality of program voltages used when the first data is stored in the semiconductor memory system.
The semiconductor memory system may include a state data storage area.
An index of a data cell for a program operation and state data of the data cell may be stored in the state data storage region.
According to an embodiment of the present invention, the controller may include: a first device performing a first ECC decoding on user data of first data stored in the semiconductor memory system using a first read voltage, and for determining whether the first decoding of the user data is successful, wherein the first data includes the user data, ECC data for the user data, and status data for the user data; a second device which changes the first read voltage to a second read voltage based on state data of the first data when a first ECC decoding of the user data fails; and a third device performing a second ECC decoding on the user data using the second read voltage and determining whether the second decoding of the user data is successful, wherein the third means repeats the performing of the second ECC decoding of the user data by changing the second read voltage a predetermined number of times until the second ECC decoding of the user data is successful.
The state data may include information of a program voltage used when the first data is stored in the semiconductor memory system.
The information of the program voltage may be an index corresponding to one of a plurality of program voltage groups, each of the plurality of program voltage groups being a group of program voltages for storing data into the semiconductor memory system, and each of the plurality of program voltage groups being indexed.
The third device may perform a second ECC decoding on the user data according to one or more read-retry voltages corresponding to the index and by way of read-retry.
The state data may include information of a plurality of repeated program voltages used when the first data is stored in the semiconductor memory system.
According to an embodiment of the present invention, information of a program/erase cycle group including information of a program voltage used during a data program operation on a memory block is additionally stored. When ECC decoding of the programmed data fails, the programmed data may be re-read based on the information of the program/erase cycle group. Therefore, the programmed data can be reliably read.
According to an embodiment of the present invention, information of a program/erase cycle group including information of a program voltage used while user data is programmed into a memory block is additionally stored as state data. When the first ECC decoding of the programmed user data fails, the read operation may be performed again on the programmed user data, and the second ECC decoding may be performed on the re-read user data based on the programmed state data. Therefore, the user data can be reliably read.
Drawings
Fig. 1A is a table illustrating a program/erase cycle set suitable for programming data in a semiconductor memory device.
Fig. 1B is a table illustrating read-retry groups applicable to reading data from a semiconductor memory device.
Fig. 2 is a block diagram schematically illustrating a semiconductor memory system according to an embodiment of the present invention.
Fig. 3 is a circuit diagram schematically illustrating a memory cell array circuit of a memory block included in a semiconductor memory device according to an embodiment of the present invention.
Fig. 4 is a flowchart illustrating an operation of the semiconductor memory device according to an embodiment of the present invention.
Fig. 5 is a diagram illustrating a data format according to an embodiment of the present invention.
Fig. 6A to 6C are diagrams schematically illustrating an operation of storing state data in a memory block according to an embodiment of the present invention.
Fig. 7 to 11 are diagrams schematically illustrating a three-dimensional (3D) nonvolatile memory device according to an embodiment of the present invention.
Fig. 12 to 14 are diagrams schematically illustrating a 3D nonvolatile memory device according to an embodiment of the present invention.
Fig. 15 is a block diagram schematically illustrating an electronic device including a semiconductor memory system according to an embodiment of the present invention.
Fig. 16 is a block diagram schematically illustrating an electronic device including a semiconductor memory system according to an embodiment of the present invention.
Fig. 17 is a block diagram schematically illustrating an electronic device including a semiconductor memory system according to an embodiment of the present invention.
Detailed Description
Various embodiments will be described in more detail below with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The drawings are not necessarily to scale, and in some instances, proportions may have been exaggerated to clearly illustrate features of embodiments. Throughout this disclosure, reference numerals directly correspond to like parts in the various figures and embodiments of the invention. Also note that: in this specification, "connected/coupled" means not only that one element is directly coupled to another element but also that one element is indirectly coupled to another element via intermediate elements. In addition, the singular form may include the plural form as long as it is not specifically mentioned in the sentence. It should be readily understood that: the meaning of "on" and "over" in this disclosure should be interpreted in the broadest manner, such that "on" means not only "directly on", but also "on something with intervening features or layers therebetween", and such that "over" means not only directly on top of, but also on top of, something with intervening features or layers therebetween. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or the substrate but also to the case where a third layer exists between the first layer and the second layer or the substrate.
Fig. 2 is a block diagram schematically illustrating a semiconductor memory system 110 according to an embodiment of the present invention. FIG. 2 is a diagram illustrating data processing system 10 including semiconductor memory system 110, according to an embodiment of the present invention.
Referring to FIG. 2, data processing system 10 may include HOST HOST 100 and semiconductor memory system 110.
The host 100 may be one of the following: portable electronic devices including cellular telephones, MP3 players, laptop computers, and the like, as well as electronic devices such as desktop computers, game consoles, televisions, projectors, and the like.
The semiconductor memory system 110 may operate in response to a request from the host 100 and may store data to be accessed by the host 100. That is, the semiconductor memory system 110 may be used as a primary storage device or a secondary storage device of the host 100. The semiconductor memory system 110 may be implemented as one of various storage devices according to a host interface protocol coupled to the host 100. For example, the semiconductor memory system 110 includes a Solid State Disk (SSD), a multimedia card (MMC), an embedded MMC (emmc), a small-sized multimedia card (RS-MMC), a micro-sized version MMC (mmcmicro), a Secure Digital (SD) card, a mini secure digital (miniSD) card, a micro-amp all digital (microSD) card, a Secure Digital High Capacity (SDHC), a universal memory bus (USB) memory device, a universal flash memory (UFS) device, a Compact Flash (CF) card, a smart media card (SM) card, a memory stick, and the like.
The storage device may be implemented with one or more of volatile memory devices such as DRAM (dynamic random access memory) and SRAM (static RAM), and nonvolatile memory devices such as ROM (read only memory), MROM (mask ROM), PROM (programmable ROM), EPROM (erasable ROM), EEPROM (electrically erasable ROM), FRAM (ferromagnetic ROM), PRAM (phase change RAM), MRAM (magnetic RAM), RRAM (resistive RAM), and flash memory.
The semiconductor memory system 110 may include a semiconductor memory device 200 and a memory controller 120. The semiconductor memory device 200 may store data to be accessed by the host 100. The memory controller 120 may control the storage of data in the semiconductor memory device 200.
The controller 120 and the semiconductor memory device 200 may be integrated into a single semiconductor device. For example, the controller 120 and the semiconductor memory device 200 may be integrated into a single semiconductor device to form an SSD. When the semiconductor memory system 110 is used as an SSD, the operation speed of the host 100 coupled to the semiconductor memory system 110 can be significantly improved.
The controller 120 and the semiconductor memory device 200 may be integrated into a single semiconductor device to configure a memory card. For example, the controller 120 and the semiconductor memory device 200 may be integrated into a single semiconductor device to form a memory card, such as a personal computer memory card international association PC card (PCMCIA), a Compact Flash (CF) card, a smart media card (SM) card, a memory stick, a multimedia card (MMC), a small-sized multimedia card (RS-MMC), and a micro-sized version MMC (mmcmicro), a Secure Digital (SD) card, a mini secure digital (miniSD) card, a micro-security digital (microSD) card, a Secure Digital High Capacity (SDHC), a universal flash memory (UFS), and the like.
As another example, the semiconductor memory system 110 may be provided as one of various elements forming an electronic device, such as a computer, an Ultra Mobile Personal Computer (UMPC), a workstation, a net-book (net-book) computer, a Personal Digital Assistant (PDA), a portable computer, a netbook, a tablet computer, a wireless phone, a mobile phone, a smart phone, an electronic book reader, a Portable Multimedia Player (PMP), a portable game device, a navigation device, a black box, a digital camera, a Digital Multimedia Broadcasting (DMB) player, a 3-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device of a data center, a device capable of receiving and transmitting information in a wireless environment, a computer program, a computer readable medium, and a computer program, One of the electronic devices of the home network, one of the electronic devices of the computer network, one of the electronic devices of the telematics network, a Radio Frequency Identification (RFID) device, or an element and device of the computing system.
The semiconductor memory device 200 of the semiconductor memory system 110 can maintain data stored therein even when power is cut off. The semiconductor memory device 200 may store data provided from the host 100 through a write operation and may provide the stored data to the host 100 through a read operation.
The semiconductor memory device 200 may include a memory block 210, a control circuit 220, a voltage management unit 230, a row decoder 240, a page buffer 250, and a column decoder 260. The semiconductor memory device 200 may be a non-volatile memory device, such as a flash memory device. The semiconductor memory device 200 may have a 3-dimensional (3D) stack structure.
The memory block 210 may include a plurality of pages, each page including a plurality of memory cells coupled to a plurality of word lines WL.
The control circuit 220 may control the overall operations of the semiconductor memory device 200, including program, erase, and read operations.
The voltage management unit 230 may provide a word line voltage (e.g., program, read) and a pass voltage to each of the plurality of word lines according to an operation mode, and may provide a voltage to a bank (e.g., a well region) forming the plurality of memory cells. The voltage management unit 230 may provide a voltage under the control of the control circuit 220. The voltage management unit 230 may provide a plurality of variable read voltages to generate a plurality of read data.
The row decoder 240 may select one of a plurality of memory blocks or sectors of the memory cell array 210, and may select one of a plurality of word lines of the selected memory block under the control of the control circuit 220. The row decoder 240 may supply the word line voltages generated by the voltage management unit 230 to the selected word line and the unselected word lines, respectively, under the control of the control circuit 220.
The page buffer 250 may operate under the control of the control circuit 220. During a program operation, the page buffer 250 may function as a write driver for driving bit lines according to data to be stored in the memory cell array 211. During a program operation, the plurality of page buffers 250 may receive data to be programmed in the memory cell array 211 from a buffer (not shown), and may drive bit lines according to the received data. The plurality of page buffers 250 may correspond to a plurality of columns or bit lines, respectively, or a plurality of column pairs or bit line pairs, respectively. The page buffer 250 may include a plurality of latches.
The memory controller 120 of the semiconductor memory system 110 may control the semiconductor memory device 200 in response to a request from the host 100. For example, the memory controller 120 may provide data read from the semiconductor memory device 200 to the host 100, and may store the data provided from the host 100 in the semiconductor memory device 200. To this end, the memory controller 120 may control program, read, and erase operations of the semiconductor memory device 200.
The memory controller 120 may include a host interface unit (host I/F)130, a processor 140, an ECC unit 160, a Power Management Unit (PMU)170, a NAND Flash Controller (NFC)180, and a memory 190.
The host interface unit 130 may process commands and data provided by the host 100. The host interface unit 130 may communicate with the host 100 through one or more interface protocols, such as Universal Serial Bus (USB), multimedia card (MMC), peripheral component interconnect express (PCI-E), Small Computer System Interface (SCSI), serial attached SCSI (sas), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).
The ECC unit 160 may detect and correct errors included in data read from the semiconductor memory apparatus 200 during a read operation. The ECC unit 160 may perform an ECC decoding operation on data read from the semiconductor memory apparatus 200, determine whether the ECC decoding is successful, provide an instruction signal according to the determination, and correct an error bit included in the read data using a parity bit generated through ECC encoding. An ECC fail signal is generated in accordance with a failure of ECC decoding when the ECC unit 160 may not correct erroneous bits or the number of correction operations performed exceeds a given error correction capability.
The ECC unit 160 may correct errors by a code modulation such as a Low Density Parity Check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-solomon (rs) code, a convolutional code, an RSC (recursive systematic code), a Trellis Coded Modulation (TCM), a Block Coded Modulation (BCM), and the like. ECC unit 160 may include error correction circuitry, an error correction system, and an error correction device.
The PMU 170 may manage power for the memory controller 120 or power for elements included in the memory controller 120.
The NFC 180 may serve as an interface between the memory controller 120 and the semiconductor memory device 200 for the memory controller 120 to control the semiconductor memory device 200 in response to a request from the host 100, and when the semiconductor memory device 200 is a flash memory device (e.g., a NAND flash memory device), the NFC 180 may generate a control signal of the semiconductor memory device 200 and process data under the control of the processor 140.
The memory 190 may serve as a working memory of the semiconductor memory system 110 and the memory controller 120, and may store data for driving the semiconductor memory system 110 and the memory controller 120. The memory controller 120 controls the semiconductor memory device 200 in response to a request from the host 100, for example, the memory controller 120 provides the host 100 with data read from the semiconductor memory device 200 and stores the data provided from the host 100 in the semiconductor memory device 200. To this end, the memory controller 120 controls program, read, and erase operations of the semiconductor memory device 200, and the memory 190 may store data required for such operations between the memory controller 120 and the semiconductor memory device 200.
Memory 190 may be implemented with volatile memory, such as SRAM or DRAM. The memory 190 may store data required for operations between the memory controller 120 and the semiconductor memory device 200, data required for program and read operations, and data to be programmed and read during the program and read operations. To this end, the memory 190 may include a program memory, a data memory, a write buffer, a read buffer, a map buffer, and the like.
The memory 190 may store data required for each operation including data reading between the ECC unit 160 and the processor 140, and data to be stored during the data reading operation. That is, the memory 190 may store data read from the semiconductor memory device 200. The data may include user data, ECC data, and status data. The state data may include information of a program/erase cycle group applied while data is programmed in the memory block 210 of the semiconductor memory device 200.
The processor 140 may perform general control operations of the semiconductor memory system 110, and may control program and read operations of the semiconductor memory device 200 in response to program and read requests from the host 100. The processor 140 may drive firmware called a Flash Translation Layer (FTL) to perform general control operations of the semiconductor memory system 110. The processor 140 may be implemented as a microprocessor or Central Processing Unit (CPU).
During a data programming operation on the memory blocks 210 of the memory chip, the processor 140 may refer the semiconductor memory device 200 and the program data to a program/erase cycle group corresponding to the number of program/erase cycles of the memory chip.
More specifically, the data to be programmed into the memory block 210 may be user data, ECC data, and status data. The ECC data may be used for error detection and error correction of the user data.
Hereinafter, the first and second Error Correction Code (ECC) decoding operations are described in more detail. As described above, the state data may include an index of a program/erase cycle group including a program voltage applied while user data is programmed in the memory block 210 of the semiconductor memory device 200. That is, the state data may include information of a program voltage for programming of user data. The state data may represent a program voltage corresponding to a read voltage to be used for reading of user data programmed in the memory block 210 in order to prevent a mismatch between the program voltage and the read voltage.
The status data may include an index of a program/erase cycle group, which is below 2 bytes in size, and may be stored with the user data and the ECC data.
When the processor 140 receives the signal indicating that ECC decoding of the user data fails from the ECC unit 160, based on the information of the program/erase cycle group stored in the memory 190 described with reference to fig. 1A, the processor 140 may check the program/erase cycle group indicated by the state data corresponding to the user data whose ECC decoding failed, may control the semiconductor memory device 200 to re-read the user data using the read voltage included in the read-retry group corresponding to the program/erase cycle group indicated by the state data corresponding to the user data whose ECC decoding failed, and provide the re-read user data to the ECC unit 160.
Fig. 3 is a circuit diagram schematically illustrating a memory cell array circuit of a memory block 210 included in a semiconductor memory device 200 according to an embodiment of the present invention.
Referring to fig. 3, the memory block 210 may include a plurality of cell strings (cell strings) 221 coupled to bit lines BLO to BLm-1, respectively. The cell strings 221 of each column may include one or more drain select transistors DST and one or more source select transistors SST. A plurality of memory cells or memory cell transistors may be coupled in series between the select transistors DST and SST.
Each of the memory cells MCO to MCn-1 may be formed of a multi-level cell (MLC) storing a plurality of bits of data information in each cell. Strings 221 may be electrically coupled to respective bit lines BLO through BLm-1, respectively.
Fig. 4 is a flowchart illustrating an operation of the semiconductor memory device according to an embodiment of the present invention. Fig. 5 is a diagram illustrating a data format according to an embodiment of the present invention.
Referring to fig. 4, in step S401, the controller 120 may receive data read from the memory block 210 of the semiconductor memory device 200. Data can be read by a read voltage that is one of read-retry groups corresponding to the number of current for program/erase cycles of the memory block 210 of the memory chip. For example, while performing a read operation on data, the controller 120 may check the current number of program/erase cycles of the memory chips including the memory block 210. In an embodiment, data is programmed to the memory block 210 by a program voltage belonging to the first program/erase cycle group PGr 1. When the checked number of program/erase cycles of the memory chips falls within the range of 0.2K to 0.5K, the controller 120 may control the semiconductor memory device 200 to read data using the read voltages REVL1, REVL2, and REVL3 of the second read-retry group RGr2 corresponding to the checked number of program/erase cycles of the memory chips falling within the range of 0.2K to 0.5K. The read data will be described with reference to fig. 5.
Referring to fig. 5, data programmed in memory block 210 may include user data 51, ECC data 53, and status data 55. The ECC data 53 may be used for error detection and error correction of the user data 51. The state data 55 may include an index of a program/erase cycle group including a program voltage applied while the user data 51 is programmed in the memory block 210 of the semiconductor memory device 200. That is, state data 55 may include information of a program voltage for programming of user data 51. The state data 55 may represent a program voltage corresponding to a read voltage to be used for reading of the user data 51 programmed in the memory block 210 to prevent a mismatch between the program voltage and the read voltage.
Status data 55 may include an index of a set of program/erase cycles. The size of the index is below 2 bytes. The status data 55 may be stored with the user data 51 and the ECC data 53.
ECC decoding of data including state data 55 may fail and thus read state data 55 may have errors. Accordingly, since the read state data 55 has an error, the controller 120 may not check the read-retry group corresponding to the program/erase cycle group by the information of the program/erase cycle group and the read-retry group stored in the memory 190 described with reference to fig. 1A and 1B. An operation of storing the state data 55 to prevent an error of the state data 55 during a read operation on the state data 55 will be described with reference to fig. 6A to 6C.
Fig. 6A to 6C are diagrams schematically illustrating an operation of storing state data in a memory block according to an embodiment of the present invention.
Referring to fig. 6A, the state data 55 including the index of the program/erase cycle group may be programmed during the programming of the LSB data in the memory chip.
As illustrated in fig. 6A, a 2-bit multi-level cell (MLC) may have 4 states of 2-bit program data. The state data 55 including the index of the program/erase cycle group may be programmed as LSB data, and the value of "FF" may be programmed as dummy MSB data corresponding to the state data 55. The MLC storing the dummy MSB and the state data 55 as LSB data may have one of the erase state E and the third program state P3 among the first to third program states P1 to P3, and thus noise margin may be secured.
Referring to fig. 6B, the state data 55 included in the data to be programmed into the memory block 210 may repeatedly include an index of the program/erase cycle group. For example, when the state data 55 has a size of 2 bytes or less, 6 copies of the index of the program/erase cycle group having a size of 3 bits may be included in the state data 55. Later, state data 55 including a duplicate copy of the index of the program/erase cycle group may be read, and the primary representation (i.e., the index most frequently found in the state data among multiple read representations of the index of the program/erase cycle group included in state data 55) may be determined as the index of the program/erase cycle group. The status data 55 may be read erroneously. However, when state data 55 includes duplicate copies of the index of the program/erase cycle group, a primary representation of the plurality of representations of the index of the program/erase cycle group included in state data 55 may determine the index of the program/erase cycle group during a read operation on state data 55. That is, during a read operation on state data 55, the primary representation that is repeatedly found in state data 55 among the multiple representations of the index of the program/erase cycle group is most likely the index of the program/erase cycle group.
Referring to fig. 6C, unlike the embodiment described with reference to fig. 6A and 6B, the index of the program/erase cycle group may be stored in a separate state data storage area. For example, when data is programmed into a first memory block using a program voltage belonging to the first program/erase cycle group PGr1, an address of the first memory block and an index of the first program/erase cycle group PGr1 may be stored into a separate state data storage area. In this way, it can be ensured that the status data 55 stored in the separate status data storage area is free from errors. Thus, even when the data programmed into the first memory block has an error, the controller 120 can identify the index of the program/erase cycle group of the state data 55 stored in the individual state data storage area to identify the read-retry group corresponding to the program/erase cycle group represented by the state data 55 to reliably re-read the programmed data using the read-retry group corresponding to the program/erase cycle group represented by the state data 55.
Referring back to fig. 4, in step S403, the controller 120 may perform first ECC decoding on the data read from the memory block 210 in step S401 for error detection and error correction. The controller 120 may perform the first ECC decoding on the user data 51 included in the data read from the memory block 210 at step S401 using the ECC data 53 included in the data read from the memory block 210 at step S401. In step S405, the controller 120 may determine whether the first ECC decoding is successful.
When the first ECC decoding is determined to be successful in step S405, the controller 120 may provide the data on which the first ECC decoding is performed to the host 100.
When the first ECC decoding is determined to be unsuccessful in step S405, the controller 120 may check the index of the program/erase cycle group according to the status data 55 of the data read from the memory block 210 in step S401 in step S407.
At step S409, the controller 120 may identify a read-retry group corresponding to the program/erase cycle group represented by the index included in the state data 55, and may set a read voltage for reliably re-reading the programmed data from the memory block 210 using the read-retry group corresponding to the program/erase cycle group represented by the state data 55.
In step S411, the controller 120 may cause the semiconductor memory device 200 to read the same data again using the read voltage identified in S409. For example, when data is programmed by a program voltage belonging to the first program/erase cycle group PGr1, the controller 120 may identify a first read-retry group RGr1 corresponding to the first program/erase cycle group PGr1 represented by the 0 th index (index 0) included in the state data 55 of the data read from the memory block 210 at step S401, and may set read voltages REVL1, REVL2, and REVL3 for re-reading the same data from the memory block 210, at step S409. In step S411, the controller 120 may cause the semiconductor memory device 200 to read the same data again from the memory blocks using the read voltages REVL1, REVL2, and REVL3 of the first read-retry group RGr1 identified in step S409.
In step S413, the controller 120 may perform second ECC decoding on the data read from the memory block 210 in step S411 for error detection and error correction. The controller 120 may perform the second ECC decoding on the user data 51 included in the data read from the memory block 210 at step S411 using the ECC data 53 included in the data read from the memory block 210 at step S411. In step S415, the controller 120 may determine whether the second ECC decoding is successful.
When the second ECC decoding is determined to be successful at step S415, the controller 120 may provide the data on which the second ECC decoding is performed to the host 100.
When the second ECC decoding is determined to be failed in S415, the controller 120 may change the read voltage of the current index of the read-retry group to the read voltage of the next index of the read-retry group in step S417. For example, when the second ECC decoding using the read voltages REVL1, REVL2, and REVL3 of the 0 th index (index 0) of the first read-retry group RGr1 is determined to have failed at step S415, the controller 120 may change the read voltages from the REVL1, REVL2, and REVL3 of the 0 th index (index 0) of the first read-retry group RGr1 to the read voltages REVL1, REVL2, and REVL3 of the 1 st index (index 1) of the first read-retry group RGr1 at step S417.
Steps S411 to S417 may be repeated until the second ECC decoding of the data read from the memory block 210 at step S411 is successful. During the repetition, the read voltages REVL1, REVL2, and REVL3 may be changed by the index of the read-retry group.
According to an embodiment of the present invention, information of the program/erase cycle group including information of a program voltage used while user data is programmed into the memory block is additionally stored as the state data 55. When the first ECC decoding of the programmed user data fails, the read operation may be performed again on the programmed user data, and the second ECC decoding may be performed on the re-read user data based on the programmed state data. Therefore, the user data can be reliably read.
When the semiconductor memory device 200 of the semiconductor memory system 110 according to an embodiment of the present invention is implemented as a three-dimensional (3D) nonvolatile memory device, the semiconductor memory device 200 will be described in more detail.
Fig. 7 to 14 are diagrams schematically illustrating a three-dimensional (3D) nonvolatile memory device of a semiconductor memory device according to an embodiment of the present invention, the three-dimensional (3D) nonvolatile memory device being, for example, a flash memory device implemented in 3D.
Fig. 7 is a block diagram of a memory cell array of the memory block 210 shown in fig. 2.
Referring to fig. 7, the memory cell array may include a plurality of memory blocks BLK1 through BLKj, where j is an integer. Each of the plurality of memory blocks BLK1 through BLKj may have a 3D structure or a vertical structure. For example, each of the plurality of memory blocks BLK1 through BLKj may include structures extending in first through third directions (e.g., X, Y and Z directions).
Each of the plurality of memory blocks BLK1 through BLKj may include a plurality of NAND strings NS extending in the second direction. A plurality of NAND strings NS may be arranged in the first and third directions. Each of the NAND strings NS may be coupled to a bit line BL, one or more string select lines SSL, one or more ground select lines GSL, a plurality of word lines WL, one or more dummy word lines DWL, and a common source line CSL. That is, each of the plurality of memory blocks BLK1 through BLKj may be coupled to a plurality of bit lines BL, a plurality of string select lines SSL, a plurality of ground select lines GSL, a plurality of word lines WL, a plurality of dummy word lines DWL, and a plurality of common source lines CSL.
Fig. 8 is a perspective view of one BLKj of the plurality of memory blocks BLK1 through BLKj shown in fig. 7. Fig. 9 is a sectional view taken along line I-I' of the memory block BLKj shown in fig. 8.
Referring to fig. 8 and 9, the memory block BLKj may include a structure extending in the first to third directions.
A substrate 1111 may be provided. For example, the substrate 1111 may include a silicon material doped with a first type of impurity. For example, the substrate 1111 may include a silicon material doped with a p-type impurity, or a p-type well such as a pocket well. The substrate 1111 may also include an n-type well surrounding a p-type well. In the specification, it is exemplarily assumed that the substrate 1111 is p-type silicon. However, the substrate 1111 will not be limited to p-type silicon.
A plurality of doping regions 1311 to 1314 extending in a first direction may be disposed on the substrate 1111. For example, the plurality of doped regions 1311 through 1314 may have a second type different from the type of the substrate 1111. For example, the plurality of doped regions 1311 through 1314 may have an n-type. In the specification, it is exemplarily assumed that the first to fourth doping regions 1311 to 1314 have an n-type. However, the first to fourth doping regions 1311 to 1314 will not be limited to n-type.
A plurality of insulating materials 1112 extending in the first direction may be sequentially disposed in the second direction on the substrate 1111 between the first and second doping regions 1311 and 1312. For example, the plurality of insulating materials 1112 and the substrate 1111 may be disposed in the second direction such that they are spaced apart by a predetermined distance. For example, the plurality of insulating materials 1112 may be disposed to be spaced apart from each other in the second direction. For example, insulating material 1112 may include an insulator such as silicon oxide.
A plurality of pillars 1113 may be sequentially disposed on a region of the substrate 1111 between the first and second doping regions 1311 and 1312 in the first direction, and may be formed to penetrate the insulating material 1112 in the second direction. For example, each of the plurality of posts 1113 may penetrate the insulating material 1112 to contact the substrate 1111. For example, each of the plurality of posts 1113 may be constructed of a plurality of materials. For example, the surface layer 1114 of each of the plurality of pillars 1113 may comprise a silicon material having a first type. For example, the surface layer 1114 of each of the plurality of pillars 1113 may comprise a silicon material doped with the same type as the substrate 1111. In the description, it is exemplarily assumed that the surface layer 1114 of each of the plurality of pillars 1113 includes p-type silicon. However, the surface layer 1114 of each of the plurality of pillars 1113 will not be limited to p-type silicon.
The inner layer 1115 of each of the plurality of pillars 1113 may be formed of an insulating material. For example, inner layer 1115 of each of plurality of pillars 1113 may be an insulating material such as silicon oxide.
In the region between first doped region 1311 and second doped region 1312, an insulating layer 1116 may be disposed along exposed surfaces of insulating material 1112, post 1113, and substrate 1111. For example, the thickness of insulating material 1116 may be less than half the distance between insulating materials 1112. That is, insulating layer 1116 can be disposed over a first surface of insulating material 1112. More specifically, an insulating layer 1116 is disposed between two adjacent insulating materials 1112. For example, insulating material 1116 is disposed between a first insulating material of insulating material 1112 and a second insulating material underlying the first insulating material.
Conductor materials 1211 to 1291 may be disposed over the second surface of the insulating layer 1116 in a region between the first doped region 1311 and the second doped region 1312. A second surface of the insulating layer 1116 is opposite to the first surface of the insulating layer 1116.
Conductive materials 1211-1291, 1212-1292, and 1213-1293 extending in the first direction may be disposed between the insulating layers 1116. For example, a plurality of conductor materials 1221 to 1281 extending in a first direction may be disposed between insulating materials 1112. For example, the conductor materials 1211 to 1291 extending in the first direction may be metal materials. In another embodiment, the conductor materials 1211 to 1291 extending in the first direction may be a conductor material such as polysilicon.
The same structure as arranged between the first doped region 1311 and the second doped region 1312 may be provided between the second and third doped regions 1312 and 1313. For example, a plurality of insulating materials 1112 extending in the first direction are sequentially arranged in the first direction. The plurality of posts 1113 penetrate the plurality of insulating materials 1112 in the second direction. An insulating layer 1116 is disposed over the plurality of insulating materials 1112 and the plurality of posts 1113. A plurality of conductor materials 1212 to 1292 extending in the first direction may be disposed over the insulating material 1116.
The same structure as that provided between the first and second doped regions 1311 and 1312 may be provided between the third and fourth doped regions 1313 and 1314. For example, a plurality of insulating materials 1112 extending in the first direction are sequentially arranged in the first direction. The plurality of posts 1113 penetrate the plurality of insulating materials 1112 in the second direction. An insulating layer 1116 is disposed over the plurality of insulating materials 1112 and the plurality of posts 1113. A plurality of conductor materials 1213 to 1293 extending in the first direction may be disposed over the insulating material 1116.
The drain electrodes 1320 may be disposed on the plurality of pillars 1113, respectively. For example, the drain 1320 may be a silicon material doped with a second type of material. For example, the drain 1320 may be a silicon material doped with an n-type material. In an embodiment, the drain 320 is illustratively assumed to be a silicon material doped with an n-type silicon material. However, the drain 320 will not be limited to n-type silicon material. For example, the width of the drain 1320 may be wider than the width of the corresponding plurality of pillars 1113. For example, the drain electrode 1320 may be disposed on a top surface of the plurality of drain electrodes 1113 in a pad shape.
Conductor materials 1331 to 1333 extending in the third direction may be disposed on the drain electrode 1320. The conductor materials 1331-1333 may be sequentially arranged in a first direction. Conductor materials 1331-1333 may be respectively coupled to drains 1320 in corresponding regions. For example, the conductor material 1333 and the drain electrode 1320 extending in the third direction may be respectively coupled to each other through contact plugs. For example, the conductor materials 1331 to 1333 extending in the third direction may be a metal material. For example, the conductor materials 1331-1333 may be a conductor material such as polysilicon.
Referring to fig. 8 and 9, each of the plurality of pillars 1113 may form a string together with the plurality of conductor materials 1211 to 1291, 1212 to 1292, and 1213 to 1293 extending in the first direction and the insulating layer 1116. The NAND string NS may include a plurality of transistor structures TS.
Fig. 10 is a cross-sectional view of the transistor structure TS shown in fig. 9.
Referring to fig. 8 to 10, the insulating layer 1116 may include first to third sub-insulating layers 1117, 1118, and 1119.
The P-type silicon 1114 of each of the plurality of pillars 1113 may serve as a body. The first sub-insulating layer 1117 formed over the plurality of pillars 1113 may function as a tunnel insulating layer. For example, the first sub-insulating layer 1117 formed over each of the plurality of pillars 1113 may include a thermal oxide layer.
The second sub insulating layer 1118 formed over the first sub insulating layer 1117 may serve as a charge storage layer. For example, the second sub insulating layer 1118 may function as a charge trap layer. For example, the second sub insulating layer 1118 may include a nitride layer or a metal oxide layer, such as an aluminum oxide layer, a hafnium oxide layer, or the like.
The third sub-insulating layer 1119 formed between the second sub-insulating layer 1118 and the conductor material 1233 may function as a blocking insulating layer. For example, the third sub insulating layer 1119 extending in the first direction may have a single-layer or multi-layer structure. The third sub insulating layer 1119 may be a high dielectric layer having a higher dielectric constant than the first and second sub insulating layers 1117 and 1118, such as an aluminum oxide layer, a hafnium oxide layer, or the like.
The conductor material 1233 may be used as a gate or control gate. That is, the gate or control gate, the blocking insulating layer 1119, the charge trapping layer 1118, the tunnel insulating layer 1117, and the body 1114 may form a transistor or memory cell transistor structure. For example, the first to third sub-insulating layers 1117 to 1119 may form an oxide-nitride-oxide (ONO) structure. In an embodiment, the p-type silicon 1114 of each of the plurality of pillars 1113 extending in the second direction may be referred to as a body.
Memory block BLKj may include a plurality of pillars 1113. That is, the memory block BLKj may include a plurality of NAND strings NS. More specifically, the memory block BLKj may include a plurality of NAND strings NS extending in the second direction or the direction perpendicular to the substrate.
Each of the NAND strings NS may include a plurality of transistor structures TS stacked in the second direction. One or more of the plurality of transistor structures TS of each NAND string NS may be used as the string selection transistor SST. One or more of the plurality of transistor structures TS of each NAND string may serve as a ground select transistor GST.
The conductor materials 1211 to 1291, 1212 to 1292, and 1213 to 1293 extend in a first direction. Two or more of the conductor materials 1211 to 1291 may be used as selection lines, such as one or more string selection lines SSL and one or more ground selection lines GSL.
Conductor materials 1331-1333, each extending in a third direction, may be coupled to one end of a NAND string NS. For example, the conductor materials 1331-1333 each extending in the third direction may serve as bit lines BL. That is, in one memory block BLKj, a single bit line BL may be coupled to a plurality of NAND strings.
Second-type doped regions 1311 to 1314 each extending in the first direction may be disposed at the other end of the NAND string NS. The second-type doped regions 1311 to 1314 each extending in the first direction may serve as a common source line CSL.
In summary, the memory block BLKj may include a plurality of NAND strings NS each extending in a direction (second direction) perpendicular to the substrate 1111. Each of the NAND strings NS may operate as a NAND flash memory block, such as a charge trap NAND flash memory block.
Referring to fig. 8 to 10, the conductor materials 1211 to 1291, 1221 to 1292, and 1213 to 1293 each extending along the first direction form a 9-layer structure. However, the conductor materials 1211 to 1291, 1212 to 1292, and 1213 to 1293 are not limited to 9 layers. In another embodiment, the conductor material may include 8, 16, or more layers. That is, the NAND string can include 8, 16, or more transistors.
Referring to fig. 8 to 10, 3 NAND strings NS are coupled to a single bit line BL. However, the present invention will not be limited to 3 NAND strings NS coupled to a single bit line BL. For example, in a memory block BLKj, m NAND strings NS may be coupled to a single bit line BL, where m is an integer. Here, the number of conductor materials 1211 to 1291, 1212 to 1292, and 1213 to 1293 each extending in the first direction and the number of common source lines 311 to 314 may also be adjusted so as to correspond to the number of NAND strings NS coupled to a single bit line BL.
Referring to fig. 8-10, 3 NAND strings NS are coupled to a single conductor material extending in a first direction. However, the present invention will not be limited to a structure in which 3 NAND strings NS are coupled to a single conductor material. In another embodiment, n NAND strings NS (n is an integer) may be coupled to a single conductor material. Here, the number of conductor materials 1331-1333 each extending in the third direction may also be adjusted to correspond to the number of NAND strings NS coupled to a single conductor material.
Fig. 11 is an equivalent circuit of the memory block BLKj described with reference to fig. 8 to 10.
Referring to fig. 8 to 11, NAND strings NS11 to NS31 may be disposed between the first bit line BL1 and the common source line CSL. The first bit line BL1 may correspond to the conductor material 1331 extending in the third direction. The NAND strings NS12, NS22, and NS32 may be disposed between the second bit line BL2 and the common source line CSL. The second bit line BL1 may correspond to the conductor material 1332 extending in the third direction. The NAND strings NS13, NS23, and NS33 may be disposed between the third bit line BL3 and the common source line CSL. The third bit line BL3 may correspond to the conductor material 1333 extending in the third direction.
The string select transistor SST of each NAND string NS may be coupled to a corresponding bit line BL. The ground select transistor GST of each NAND string NS may be coupled to the common source line CSL. The memory cell MC may be disposed between the ground selection transistor GST and the string selection transistor SST of each NAND string NS.
The NAND string NS may be defined in units of rows and columns. NAND strings NS commonly coupled to a single bit line may form a single column. For example, the NAND strings NS 11-NS 31 coupled to the first bit line BL1 may correspond to a first column. The NAND strings NS12 through NS32 coupled to the second bit line BL2 may correspond to a second column. The NAND strings NS13 through NS33 coupled to the third bit line BL3 may correspond to the third column. The NAND strings NS coupled to a single string select line SSL may form a single row. For example, the NAND strings NS11 through NS13 coupled to the first string select line SSL1 may form a first row. The NAND strings NS 21-NS 23 coupled to the second string select line SSL2 may form a second row. The NAND strings NS31 through NS33 coupled to the third string select line SSL3 may form a third row.
A height may be defined for each NAND string NS. For example, in each NAND string NS, the height of the ground selection transistor GST may be defined as 1. In each NAND string NS, the closer to the string selection transistor SST, the higher the height of the memory cell. In each NAND string NS, the height of the memory cell MC6 adjacent to the string selection transistor SST may be defined as 6.
The string select lines SSL may be shared by the string select transistors SST of the NAND strings NS of the same row. The string select transistors SST of the NAND strings NS in different rows may be coupled with different string select lines SSL1, SSL2, and SSL3, respectively.
The memory cells MC having the same height in the NAND strings NS of the same row may share the word line WL. At a predetermined height, the word line WL may be shared by the memory cells MC of the NAND strings NS of different rows. At a predetermined height, dummy memory cells DMC of NAND strings NS of the same row may share a dummy word line DWL. At a predetermined height, dummy memory cells DMC of NAND strings NS in different rows may share a dummy word line DWL.
For example, the word lines WL or dummy word lines DWL may be commonly coupled to each other at a level where the conductor materials 1211 to 1291, 1212 to 1292, and 1213 to 1293 extending in the first direction are disposed. For example, the conductor materials 1211 to 1291, 1212 to 1292, and 1213 to 1293 each extending in the first direction may be coupled to an upper layer (not shown) via contacts. The conductor materials 1211 to 1291, 1212 to 1292, and 1213 to 1293 each extending in the first direction may be coupled to each other on an upper layer. The ground selection transistors GST of the NAND strings NS of the same row may share the ground selection line GSL. The ground select lines GSL may be shared by the ground select transistors GST of NAND strings NS of different rows. That is, the NAND strings NS11 through NS13, NS21 through NS23, and NS31 through NS33 may be commonly coupled to the ground select line GSL.
The common source line CSL may be commonly coupled to the NAND string NS. For example, the first to fourth doping regions 1311 to 1314 may be coupled at an active region (active region) of the substrate 1111. For example, the first to fourth doping regions 1311 to 1314 may be coupled to an upper layer via a contact. The first to fourth doping regions 1311 to 1314 may be commonly coupled at an upper layer.
As illustrated in fig. 11, word lines WL located at the same level may be commonly coupled to each other. Accordingly, when a given word line WL at a certain level is selected, all of the NAND strings NS coupled to the selected word line WL may be selected. NAND strings NS of different rows may be coupled to different string select lines SSL. Thus, among the NAND strings NS coupled to the selected word line WL, the NAND strings NS also coupled to the unselected rows may be electrically isolated from the bit lines BL1 to BL3 by selection of the string select lines SSL1 to SSL 3. That is, a particular row of the NAND string NS can be selected by selecting string select lines SSL 1-SSL 3. A particular NAND string NS among the NAND strings NS of the selected row may be further selected by selection of the bit lines BL1 through BL 3.
In each NAND string NS, a dummy memory cell DMC may be set. For example, as shown in fig. 11, the first to third memory cells MC1 to MC3 may be disposed between the dummy memory cell DMC and the ground selection transistor GST.
The fourth to sixth memory cells MC4 to MC6 may be disposed between the dummy memory cell DMC and the string selection transistor SST. In an embodiment, the memory cells MC in each NAND string NS are divided into groups of memory cells by dummy memory cells DMC. A memory cell group (e.g., MC1 through MC3) adjacent to the ground selection transistor GST among the memory cell groups may be referred to as a lower memory cell group. A memory cell group (e.g., MC4 through MC6) adjacent to the string selection transistor SST among the memory cell groups may be referred to as an upper memory cell group.
An operation method of the semiconductor memory system will be described with reference to fig. 7 and 11. The semiconductor memory system may include one or more cell strings. Each cell string is arranged in a direction perpendicular to the substrate and coupled with the memory controller 120. Each cell string includes a memory cell, a string selection transistor, and a ground selection transistor. The semiconductor memory system may be provided with a first read command to perform first and second hard decision read operations using a first hard decision read voltage and a second hard decision read voltage different from the first hard decision read voltage. The semiconductor memory system may form hard decision data, may select a specific one of the first and second hard decision voltages based on an erroneous bit state of the hard decision data, may form soft decision data using a soft read voltage different from the first and second hard decision read voltages, and provide the soft decision data to the memory controller 120.
Fig. 12 to 14 are diagrams schematically illustrating a 3D nonvolatile memory device according to an embodiment of the present invention. Fig. 12 through 14 illustrate a semiconductor memory system, such as a three-dimensional flash memory device, according to an embodiment of the present invention.
Fig. 12 is a perspective view of the memory block BLKj shown in fig. 7. Fig. 13 is a sectional view illustrating a memory block BLKj taken along a line VII-VII' shown in fig. 12.
Referring to fig. 12 and 13, the memory block BLKj may include a structure extending in the first to third directions.
A substrate 6311 may be provided. For example, the substrate 6311 may include a silicon material doped with a first type of impurity. For example, the substrate 6311 may include a silicon material doped with a p-type impurity, or a p-type well such as a pocket p-well. Substrate 6311 may also include an n-type well surrounding a p-type well. In an embodiment, substrate 6311 is p-type silicon. However, substrate 6311 is not limited to p-type silicon.
First to fourth conductor material layers 6321 to 6324 each extending in the X direction and the Y direction may be arranged on the substrate 6311. The first to fourth conductor material layers 6321 to 6324 may be spaced apart from each other in the Z direction.
Fifth to eighth conductor material layers 6325 to 6328 extending in the X direction and the Y direction may be disposed on the substrate 6311. Fifth through eighth layers 6325 through 6328 of conductor material may be spaced apart from each other in the Z-direction. The fifth to eighth conductor material layers 6325 to 6328 may be spaced apart from the first to fourth conductor material layers 6321 to 6324 in the Y direction.
A plurality of lower pillars DP may be formed by the first to fourth conductor material layers 6321 to 6324. Each of the plurality of lower pillars DP may extend in the Z direction. A plurality of upper pillars UP may be formed by the fifth to eighth conductor material layers 6325 to 6328. Each of the plurality of upper columns UP may extend in the Z direction.
Each of the lower pillar DP and the upper pillar UP may include an inner material layer 6361, an intermediate layer 6362, and a surface layer 6363. The interlayer 6362 may serve as a channel of the cell transistor. The surface layer 6363 may include: a blocking insulating layer, a charge storage layer, and a tunnel insulating layer.
The plurality of lower pillars DP and the plurality of upper pillars UP may be coupled by pipe gates PG. The tube gate PG may be formed in the substrate 6311. For example, the pipe grid PG may include substantially the same material as the plurality of lower pillars DP and the plurality of upper pillars UP.
A doping material layer 6312 using the second type impurity may be disposed on the plurality of lower pillars DP. The layer of doped material 6312 may extend in the X-direction and the Y-direction. For example, the doping material layer 6312 using the second type impurity may include an n-type silicon material. The doping material layer 6312 using the second type impurity may serve as the common source line CSL.
The drain electrode 6340 may be formed on each of the plurality of upper pillars UP. For example, the drain 6340 may include an n-type silicon material. A first upper conductor material layer 6351 and a second upper conductor material layer 6352 may be formed on the drain electrode 6340. The first and second upper conductor material layers 6351 and 6352 may extend in the Y direction.
The first and second upper conductor material layers 6351 and 6352 may be spaced apart from each other in the X-direction. For example, the first upper conductor material layer 6351 and the second upper conductor material layer 6352 may be made of metal. For example, the first and second upper conductor material layers 6351 and 6352 may be coupled to the drain 6340 through contact plugs. The first and second upper conductor material layers 6351 and 6352 may serve as the first and second bit lines BL1 and BL2, respectively.
The first conductor material layer 6321 may serve as the source select line SSL, and the second conductor material layer 6322 may serve as the first dummy word line DWL1, and the third and fourth conductor material layers 6323 and 6324 may serve as the first main word line MWL1 and the second main word line MWL2, respectively. The fifth and sixth conductor material layers 6325 and 6326 may serve as the third and fourth main word lines MWL3 and MWL4, respectively, the seventh conductor material layer 6327 may serve as the second dummy word line DWL2, and the eighth conductor material layer 6328 may serve as the drain select line DSL.
Each of the plurality of lower pillars DP and the first to fourth conductor material layers 6321 to 6324 adjacent to the lower pillar DP may form a lower string. Each of the plurality of upper pillars UP and the fifth to eighth layers of conductor material 6325 to 6328 adjacent to the upper pillars UP may form an upper string. The lower and upper strings may be coupled to each other by a pipe grid PG. One end of the lower string may be coupled to the second-type doping material layer 6312 serving as the common source line CSL. One end of the upper string may be coupled to a corresponding bit line through a drain 6340. The lower and upper strings are coupled to each other by a pipe grid PG. The single lower string and the single upper string may be combined to form a single cell string coupled between the layer of second-type doping material 6312 and the corresponding bit line.
That is, the lower string may include the source select transistor SST, the first dummy memory cell DMC1, and the first and second main memory cells MMC1 and MMC 2. The upper string may include third and fourth main memory cells MMC3 and MMC4, a second dummy memory cell DMC2, and a drain select transistor DST.
Referring to fig. 12 and 13, the upper and lower strings may form a NAND string NS having a plurality of transistor structures TS. The structure of the transistor TS may be the same as that described with reference to fig. 10.
Fig. 14 is an equivalent circuit of the memory block BLKj described with reference to fig. 12 and 13. Fig. 14 illustrates first and second strings among the strings included in the memory block BLKj according to an embodiment.
Referring to fig. 14, the memory block BLKj may include a plurality of cell strings, each of which includes a single upper string and a single lower string coupled to each other by the pipe gate PG, as described with reference to fig. 12 and 13.
In the memory block BLKj, memory cells stacked along the first channel layer CH1, one or more source select gates, and one or more drain select gates may form a first string ST 1. The memory cells, the one or more source select gates, and the one or more drain select gates stacked along the second channel layer CH2 may form a second string ST 2.
The first and second strings ST1 and ST2 may be coupled to a single drain select line DSL and a single source select line SSL. The first string ST1 may be coupled to a first bit line BL1, and the second string ST2 may be coupled to a second bit line BL 2.
Fig. 14 shows the first and second strings ST1 and ST2 coupled to a single drain select line DSL via a drain select gate DSG0 and to a single source select line SSL via a source select gate SSG 0. The first and second strings ST1 and ST2 may be coupled to bit lines BL1 and BL2, respectively. In another embodiment, the first string ST1 may be coupled to a first drain select line DSL1, and the second string ST2 may be coupled to a second drain select line DSL 2. In another embodiment, the first and second strings ST1 and ST2 may be commonly coupled to the same drain select line DSL and a single bit line BL. In this case, the first string ST1 may be coupled to the first source selection line SSL1, and the second string ST2 may be coupled to the second source selection line SSL 2.
Fig. 15 is a block diagram schematically illustrating an electronic device 10000 including a memory controller 15000 and a flash memory 16000 according to an embodiment of the present invention.
Referring to fig. 15, an electronic device 10000 such as a cellular phone, a smart phone, or a tablet PC may include a flash memory 16000 implemented by a flash memory device and a memory controller 15000 controlling the flash memory 16000.
The flash memory 16000 may correspond to the semiconductor memory system 110 described above with reference to fig. 12 to 14. The flash memory 16000 may store random data.
The memory controller 15000 may be controlled by the processor 11000 which controls the overall operation of the electronic device 10000.
Data stored at the flash memory 16000 may be displayed through the display 13000 under the control of the memory controller 15000 which is operated under the control of the processor 11000.
The radio transceiver 12000 can exchange radio signals through an antenna ANT. For example, the radio transceiver 12000 may convert a radio signal received from the antenna ANT into a signal to be processed by the processor 11000. Thus, the processor 11000 may process the converted signals from the radio transceiver 12000 and may store the processed signals in the flash memory 16000. Otherwise, the processor 11000 may display the processed signals through the display 13000.
The radio transceiver 12000 may convert a signal from the processor 11000 into a radio signal, and may output the converted radio signal to an external device through an antenna ANT.
The input device 14000 may receive control signals for controlling the operation of the processor 11000 or data to be processed by the processor 11000 and may be implemented by a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.
The processor 11000 may control the display 13000 such that data from the flash memory 16000, radio signals from the radio transceiver 12000, or data from the input device 14000 are displayed by the display 13000.
Fig. 16 is a block diagram schematically illustrating an electronic apparatus 20000 including a memory controller 24000 and a flash memory 25000 according to an embodiment of the present invention.
Referring to fig. 16, the electronic device 20000 may be implemented by a data processing device such as a Personal Computer (PC), a tablet computer, a web-book, an e-reader, a Personal Digital Assistant (PDA), an electric Portable Multimedia Player (PMP), an MP3 player, or an MP4 player, and the electronic device 20000 may include a flash memory device such as a flash memory 25000 and a memory controller 24000 controlling the operation of the flash memory 25000.
The electronic device 20000 may include a processor 21000 that controls the overall operation of the electronic device 20000. The memory controller 24000 may be controlled by the processor 21000.
The processor 21000 can display data stored in the semiconductor memory system through the display 23000 according to an input signal from the input device 22000. For example, the input device 22000 may be implemented by a pointing device such as a touch panel or a computer mouse, a keypad, or a keyboard.
Fig. 17 is a block diagram schematically illustrating an electronic device 30000 including a semiconductor memory system 34000 according to an embodiment of the present invention.
Referring to fig. 17, the electronic device 30000 may include: a card interface 31000, a memory controller 32000, and a semiconductor memory system 34000 such as a flash memory device.
The electronic device 30000 can exchange data with a host through the card interface 31000. The card interface 31000 may be a Secure Digital (SD) card interface or a multimedia card (MMC) interface, but is not limited thereto. The card interface 31000 may connect (interface) the HOST and the memory controller 32000 according to a communication protocol of the HOST capable of communicating with the electronic device 30000.
The memory controller 32000 may control the entire operation of the electronic device 30000, and may control data exchange between the card interface 31000 and the semiconductor memory system 34000. The buffer memory 33000 of the memory controller 32000 may buffer data transferred between the card interface 31000 and the semiconductor memory system 34000.
The memory controller 32000 may be coupled with the card interface 31000 and the semiconductor memory system 34000 through a DATA bus DATA and an ADDRESS bus ADDRESS. According to an embodiment, the memory controller 32000 may receive an ADDRESS of data to be read or written from the card interface 31000 through the ADDRESS bus ADDRESS and may transmit it to the semiconductor memory system 34000.
In addition, the memory controller 32000 may receive or transmit DATA through a DATA bus DATA connected to the card interface 31000 or the semiconductor memory system 34000.
When the electronic device 30000 is connected with a HOST (such as a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, a console, video game hardware, or a digital set-top box), the HOST may exchange data of the semiconductor memory system 34000 with the memory controller 32000 through the card interface 31000.
While the invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
As can be seen from the above embodiments, the present application provides the following technical solutions.
Technical solution 1. an operation method of a semiconductor memory system includes:
performing first Error Correction Code (ECC) decoding on first data stored in the semiconductor memory system, wherein the first data includes user data, ECC data for the user data, and state data for the user data; and
performing a second ECC decoding on the user data by changing a read voltage based on state data of the first data when the first ECC decoding on the user data fails.
The operating method of claim 1, wherein the state data includes information of a program voltage used when the first data is stored into the semiconductor memory system.
The operating method of claim 2, wherein the information of the program voltage is an index corresponding to one of a plurality of program voltage groups, each of the plurality of program voltage groups is a group of program voltages for storing data into the semiconductor memory system, and each of the plurality of program voltage groups is indexed.
The operating method of claim 3, wherein the second step performs the second ECC decoding on the user data by read-retry according to one or more read-retry voltages corresponding to the index.
Technical solution 5. the operation method according to claim 1,
wherein the semiconductor memory system is a multi-level cell (MLC) memory system, and
wherein the state data is Least Significant Bit (LSB) data.
The operating method of claim 5, wherein Most Significant Bit (MSB) data corresponding to the state data has a value of "FF".
The operating method of claim 1, wherein the state data includes information of a plurality of program voltages used when the first data is stored in the semiconductor memory system.
Technical solution 8. the operation method according to claim 1,
wherein the semiconductor memory system includes a state data storage area, an
Wherein an index of a data unit for a program operation and state data of the data unit are stored in the state data storage region.
Technical means 9 a semiconductor memory system comprising:
a semiconductor memory device; and
a controller for controlling the operation of the electronic device,
wherein the controller comprises:
a first device performing a first ECC decoding on user data of first data stored in the semiconductor memory system, wherein the first data includes the user data, ECC data for the user data, and status data for the user data; and
a second device that performs a second ECC decoding on the user data by changing a read voltage based on state data of the first data when the first ECC decoding on the user data fails.
Technical solution 10 the semiconductor memory system according to claim 9, wherein the state data includes information of a program voltage used when the first data is stored into the semiconductor memory system.
The semiconductor memory system according to claim 10, wherein the information of the program voltage is an index corresponding to one of a plurality of program voltage groups, each of the plurality of program voltage groups is a group of program voltages for storing data into the semiconductor memory system, and each of the plurality of program voltage groups is indexed.
Technical solution 12 the semiconductor memory system according to claim 11, wherein the second device performs the second ECC decoding on the user data by read-retry according to one or more read-retry voltages corresponding to the index.
Technical solution 13 the semiconductor memory system according to claim 9,
wherein the semiconductor memory system is a multi-level cell (MLC) memory system,
wherein the state data is Least Significant Bit (LSB) data, an
Wherein Most Significant Bit (MSB) data corresponding to the state data has a 'FF' value.
The semiconductor memory system according to claim 9, wherein the state data includes information of a plurality of program voltages used when the first data is stored in the semiconductor memory system.
Claim 15 the semiconductor memory system according to claim 9,
wherein the semiconductor memory system includes a state data storage area, an
Wherein an index of a data unit for a program operation and state data of the data unit are stored in the state data storage region.
The invention according to claim 16 provides a controller comprising:
a first device performing a first ECC decoding on user data of first data stored in the semiconductor memory system using a first read voltage, and for determining whether the first decoding of the user data is successful, wherein the first data includes the user data, ECC data for the user data, and status data for the user data;
a second apparatus that changes the first read voltage to a second read voltage based on state data of the first data when the first ECC decoding of the user data fails; and
a third device to perform a second ECC decoding on the user data using the second read voltage and to determine whether the second decoding of the user data is successful,
wherein the third device repeats the performing of the second ECC decoding of the user data by changing the second read voltage a predetermined number of times until the second ECC decoding of the user data is successful.
The controller of claim 16, wherein the status data includes information of a program voltage used when the first data is stored in the semiconductor memory system.
The controller of claim 16, wherein the information of the program voltage is an index corresponding to one of a plurality of program voltage groups, each of the plurality of program voltage groups is a group of program voltages for storing data into the semiconductor memory system, and each of the plurality of program voltage groups is indexed.
The controller of claim 18, wherein the third device performs the second ECC decoding on the user data by read-retry according to one or more read-retry voltages corresponding to the index.
The controller of claim 16, wherein the status data includes information of a plurality of repeated programming voltages used when the first data is stored in the semiconductor memory system.

Claims (17)

1.一种半导体存储器系统的操作方法，包括：1. A method of operating a semiconductor memory system, comprising: 对存储在所述半导体存储器系统中的第一数据执行第一错误校正码解码，其中，所述第一数据包括用户数据、针对所述用户数据的错误校正码数据以及针对所述用户数据的状态数据；以及performing first error correction code decoding on first data stored in the semiconductor memory system, wherein the first data includes user data, error correction code data for the user data, and a state for the user data data; and 在对所述用户数据的所述第一错误校正码解码失败时，通过基于所述第一数据的状态数据改变读取电压来对所述用户数据执行第二错误校正码解码，performing second error correction code decoding on the user data by changing a read voltage based on state data of the first data when decoding the first error correction code of the user data fails, 其中，将通过改变所述读取电压对所述用户数据执行第二错误校正码解码的步骤重复预定次数，直到对所述用户数据的所述第二错误校正码解码成功，wherein, the step of performing second error correction code decoding on the user data by changing the read voltage is repeated a predetermined number of times until the second error correction code decoding of the user data is successful, 其中，所述状态数据包括编程/擦除循环组的索引，所述索引包括当所述第一数据被存储到所述半导体存储器系统中时使用的编程电压的信息，wherein the state data includes an index of a program/erase cycle group, the index including information on a programming voltage used when the first data is stored in the semiconductor memory system, 其中，所述编程/擦除循环组对应于数据编程操作期间所述半导体存储器系统的编程/擦除循环数，以及wherein the set of program/erase cycles corresponds to the number of program/erase cycles of the semiconductor memory system during a data programming operation, and 其中，所述状态数据表示与要用于被编程的用户数据的读取的读取电压相对应的编程电压。Wherein, the status data represents a programming voltage corresponding to a read voltage to be used for reading of the programmed user data. 2.根据权利要求1所述的操作方法，其中所述编程电压的所述信息是与多个编程电压组之一相对应的索引，所述多个编程电压组中的每一个是用于将数据存储到所述半导体存储器系统中的编程电压的组，且所述多个编程电压组中的每一个被编索引。2 . The operating method of claim 1 , wherein the information of the programming voltage is an index corresponding to one of a plurality of programming voltage groups, each of the plurality of programming voltage groups being used to convert 2 . Data is stored into sets of programming voltages in the semiconductor memory system, and each of the plurality of sets of programming voltages is indexed. 3.根据权利要求2所述的操作方法，其中对所述用户数据执行所述第二错误校正码解码的步骤是根据与所述索引相对应的一个或更多读取-重试电压并通过读取-重试的方式来执行的。3. The operating method of claim 2, wherein the step of performing the second error correction code decoding on the user data is based on one or more read-retry voltages corresponding to the index and by Read-retry method to execute. 4.根据权利要求1所述的操作方法，4. operating method according to claim 1, 其中所述半导体存储器系统是多级单元存储器系统，以及wherein the semiconductor memory system is a multi-level cell memory system, and 其中，所述状态数据是最低有效位数据。Wherein, the status data is least significant bit data. 5.根据权利要求4所述的操作方法，其中与所述状态数据相对应的最高有效位数据具有“FF”值。5. The operating method of claim 4, wherein the most significant bit data corresponding to the status data has a "FF" value. 6.根据权利要求1所述的操作方法，其中所述状态数据包括多个在所述第一数据被存储到所述半导体存储器系统中时使用的编程电压的信息。6. The operating method of claim 1, wherein the state data includes a plurality of information of program voltages used when the first data is stored in the semiconductor memory system. 7.根据权利要求1所述的操作方法，7. The operating method according to claim 1, 其中所述半导体存储器系统包括状态数据存储区域，以及wherein the semiconductor memory system includes a state data storage area, and 其中，用于编程操作的数据单元的索引和所述数据单元的状态数据被存储在所述状态数据存储区域中。Wherein, an index of a data unit for a program operation and state data of the data unit are stored in the state data storage area. 8.一种半导体存储器系统，包括：8. A semiconductor memory system comprising: 半导体存储器设备；以及semiconductor memory devices; and 控制器，controller, 其中所述控制器包括：Wherein the controller includes: 对存储在所述半导体存储器 系统中的第一数据的用户数据执行第一错误校正码解码的第一设备，其中，所述第一数据包括用户数据、针对所述用户数据的错误校正码数据以及针对所述用户数据的状态数据；以及A first apparatus that performs first error correction code decoding on user data of first data stored in the semiconductor memory system, wherein the first data includes user data, error correction code data for the user data, and state data for the user data; and 在对所述用户数据的所述第一错误校正码解码失败时，通过基于所述第一数据的状态数据改变读取电压来对所述用户数据执行第二错误校正码解码的第二设备，a second device that performs second error correction code decoding on the user data by changing a read voltage based on state data of the first data when decoding the first error correction code of the user data fails, 其中，将通过改变所述读取电压对所述用户数据执行第二错误校正码解码的步骤重复预定次数，直到对所述用户数据的所述第二错误校正码解码成功，wherein, the step of performing second error correction code decoding on the user data by changing the read voltage is repeated a predetermined number of times until the second error correction code decoding of the user data is successful, 其中，所述状态数据包括编程/擦除循环组的索引，所述索引包括当所述第一数据被存储到所述半导体存储器系统中时使用的编程电压的信息，wherein the state data includes an index of a program/erase cycle group, the index including information on a programming voltage used when the first data is stored in the semiconductor memory system, 其中，所述编程/擦除循环组对应于数据编程操作期间所述半导体存储器系统的编程/擦除循环数，以及wherein the set of program/erase cycles corresponds to the number of program/erase cycles of the semiconductor memory system during a data programming operation, and 其中，所述状态数据表示与要用于被编程的用户数据的读取的读取电压相对应的编程电压。Wherein, the status data represents a programming voltage corresponding to a read voltage to be used for reading of the programmed user data. 9.根据权利要求8所述的半导体存储器系统，其中所述编程电压的所述信息是与多个编程电压组之一相对应的索引，所述多个编程电压组中的每一个是用于将数据存储到所述半导体存储器系统中的编程电压的组，且所述多个编程电压组中的每一个被编索引。9. The semiconductor memory system of claim 8, wherein the information of the programming voltage is an index corresponding to one of a plurality of programming voltage groups, each of the plurality of programming voltage groups being used for Data is stored into sets of programming voltages in the semiconductor memory system, and each of the plurality of sets of programming voltages is indexed. 10.根据权利要求9所述的半导体存储器系统，其中所述第二设备根据与所述索引相对应的一个或更多读取-重试电压并通过读取-重试的方式对所述用户数据执行所述第二错误校正码解码。10. The semiconductor memory system of claim 9, wherein the second device issues the user to the user in a read-retry manner according to one or more read-retry voltages corresponding to the index. The data is decoded by the second error correction code. 11.根据权利要求8所述的半导体存储器系统，11. The semiconductor memory system of claim 8, 其中所述半导体存储器系统是多级单元存储器系统，wherein the semiconductor memory system is a multi-level cell memory system, 其中，所述状态数据是最低有效位数据，以及wherein the status data is the least significant bit data, and 其中，与所述状态数据相对应的最高有效位数据具有“FF”值。Wherein, the most significant bit data corresponding to the status data has a value of "FF". 12.根据权利要求8所述的半导体存储器系统，其中所述状态数据包括多个在所述第一数据被存储到所述半导体存储器系统中时使用的编程电压的信息。12. The semiconductor memory system of claim 8, wherein the state data includes information on a plurality of programming voltages used when the first data is stored in the semiconductor memory system. 13.根据权利要求8所述的半导体存储器系统，13. The semiconductor memory system of claim 8, 其中所述半导体存储器系统包括状态数据存储区域，以及wherein the semiconductor memory system includes a state data storage area, and 其中，用于编程操作的数据单元的索引和所述数据单元的状态数据被存储在所述状态数据存储区域中。Wherein, an index of a data unit for a program operation and state data of the data unit are stored in the state data storage area. 14.一种控制器，包括：14. A controller comprising: 第一设备，其利用第一读取电压对存储在半导体存储器 系统中的第一数据的用户数据执行第一错误校正码解码，并用于确定对所述用户数据的所述第一错误校正码解码是否成功，其中，所述第一数据包括用户数据、针对所述用户数据的错误校正码数据以及针对所述用户数据的状态数据；a first device for performing first error correction code decoding on user data of first data stored in a semiconductor memory system using a first read voltage and for determining decoding of the first error correction code on the user data Whether it is successful, wherein the first data includes user data, error correction code data for the user data, and status data for the user data; 第二设备，其在对所述用户数据的所述第一错误校正码解码失败时，基于所述第一数据的状态数据将所述第一读取电压改变为第二读取电压；以及a second device that changes the first read voltage to a second read voltage based on state data of the first data when decoding the first error correction code of the user data fails; and 第三设备，其利用所述第二读取电压对所述用户数据执行第二错误校正码解码，并用于确定对所述用户数据的第二解码是否成功，a third device that performs second error correction code decoding on the user data using the second read voltage, and is configured to determine whether the second decoding of the user data is successful, 其中，所述第三设备通过改变所述第二读取电压预定次数重复所述用户数据的所述第二错误校正码解码的执行，直到对所述用户数据的第二错误校正码解码成功，Wherein, the third device repeats the execution of the decoding of the second error correction code of the user data by changing the second read voltage a predetermined number of times until the decoding of the second error correction code of the user data is successful, 其中，所述状态数据包括编程/擦除循环组的索引，所述索引包括当所述第一数据被存储到所述半导体存储器系统中时使用的编程电压的信息，wherein the state data includes an index of a program/erase cycle group, the index including information on a programming voltage used when the first data is stored in the semiconductor memory system, 其中，所述编程/擦除循环组对应于数据编程操作期间所述半导体存储器系统的编程/擦除循环数，以及wherein the set of program/erase cycles corresponds to the number of program/erase cycles of the semiconductor memory system during a data programming operation, and 其中，所述状态数据表示与要用于被编程的用户数据的读取的读取电压相对应的编程电压。Wherein, the status data represents a programming voltage corresponding to a read voltage to be used for reading of the programmed user data. 15.根据权利要求14所述的控制器，其中所述编程电压的所述信息是与多个编程电压组之一相对应的索引，所述多个编程电压组中的每一个是用于将数据存储到所述半导体存储器系统中的编程电压的组，且所述多个编程电压组中的每一个被编索引。15. The controller of claim 14, wherein the information of the programming voltages is an index corresponding to one of a plurality of programming voltage groups, each of the plurality of programming voltage groups being used to Data is stored into sets of programming voltages in the semiconductor memory system, and each of the plurality of sets of programming voltages is indexed. 16.根据权利要求15所述的控制器，其中所述第三设备根据与所述索引相对应的一个或更多读取-重试电压并通过读取-重试的方式对所述用户数据执行所述第二错误校正码解码。16. The controller of claim 15, wherein the third device verifies the user data in a read-retry manner according to one or more read-retry voltages corresponding to the index The second error correction code decoding is performed. 17.根据权利要求14所述的控制器，其中所述状态数据包括在所述第一数据被存储到所述半导体存储器系统中时使用的多个重复的编程电压的信息。17. The controller of claim 14, wherein the state data includes information of a plurality of repeated programming voltages used when the first data is stored into the semiconductor memory system.
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