CN105718402B - Programmable timing generator - Google Patents
Programmable timing generator Download PDFInfo
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- CN105718402B CN105718402B CN201610020516.1A CN201610020516A CN105718402B CN 105718402 B CN105718402 B CN 105718402B CN 201610020516 A CN201610020516 A CN 201610020516A CN 105718402 B CN105718402 B CN 105718402B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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Abstract
The invention provides a programmable timing generator, which comprises a counter unit, an FIFO unit, a comparator unit and a latch unit, wherein the counter unit is connected with the FIFO unit; the counter unit and the FIFO unit are both connected with the comparator unit, and both the FIFO unit and the comparator unit are connected with the latch unit; the FIFO unit stores A, B, C three sets of values; reading A, B, C values from the FIFO cells; the comparator unit compares the A value output by the FIFO unit with the count value of the counter unit, and latches the current output data into the latch unit after clearing the counter unit when the A value and the count value are equal, wherein the calculation formula of the output data is as follows: current output data (last output data and (notc)) or (b and c); when the current output data is output data in an initial state, the last output data is 0; the next set of A, B, C values is then read from the FIFO. The invention can output any time sequence without solidifying the output time sequence and occupies little CPU resource.
Description
Technical Field
The invention relates to a programmable timing generator.
Background
Both ICs and IC connections communicate by following an agreed-upon timing sequence to transmit and receive data to and from each other. Therefore, many controllers such as IIC controller, SPI controller, LCD controller, etc. are provided inside the IC. There is a timing generator at the output of each controller, but existing products are designed to pin it out, resulting in ICs that cannot support non-standard or upgraded versions. In this case, one may choose to use GPIO to simulate the corresponding timing, but the CPU resources are occupied and the frequency is not high.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a programmable timing generator, which can output any timing through software configuration and occupies less CPU resources.
The invention is realized by the following steps: a programmable timing generator comprises a counter unit, a FIFO unit, a comparator unit and a latch unit;
(1) the counter unit and the FIFO unit are connected with the comparator unit, and the FIFO unit and the comparator unit are connected with the latch unit;
(2) the FIFO unit stores A, B and C groups of values;
(3) reading A, B and C values from the FIFO cells;
(4) the comparator unit compares the value A output by the FIFO unit with the count value of the counter unit, and latches the current output data into the latch unit after clearing the counter unit when the value A is equal to the count value of the counter unit, wherein the calculation formula of the output data is as follows:
current output data ═ (last output data and (notc)) or (bandc); when the current output data is output data in an initial state, the last output data is 0;
(5) then the next set of A, B and C values are read from the FIFO and the process returns to step (4), so that the specified data can be output at the specified time, and the effect of the programmable timing generator can be achieved.
Further, the counter unit receives signals of clock, operation enable and reset, and the FIFO unit receives signals of write enable;
when the reset is high, the counter unit is set to be-1, the FIFO unit is emptied at the same time, and the latch unit is set to be 0;
storing A, B and the value of C in the FIFO cell at the rising delay of the clock when reset low and write enable high; when the reset is low and the read enable is low, the FIFO unit outputs the most advanced data when the clock is delayed;
when the reset is low and the operation enable is high, the counter unit starts counting, the comparator unit compares the count value of the counter unit with the value A output by the FIFO unit, if the count value is equal, the counter unit is set to 0, the read enable of the FIFO unit is set to 1, the latch unit latches the output data, the FIFO unit outputs the next group of A, B and C values, and if the count value is not equal, the read enable of the FIFO unit is set to 0.
Furthermore, the FIFO unit consists of three FIFOs, wherein the three FIFOs respectively store A, B and C values, the A value is a comparison value, the B value is an output value, and the C value is an output enabling value.
The invention has the following advantages: the timing generator comprises a counter unit, an FIFO unit, a comparator unit and a latch unit, wherein A, B and C three groups of values stored in the FIFO unit can be configured according to requirements, so that the output timing can not be solidified and any timing can be output, and the CPU resource is little occupied.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
FIG. 1 is an architecture diagram of a programmable timing generator according to the present invention.
FIG. 2 is a diagram illustrating a result of an execution process of the programmable timing generator according to the present invention.
Detailed Description
As shown in FIG. 1, the programmable timing generator of the present invention comprises a counter unit, a FIFO unit, a comparator unit and a latch unit;
(1) the counter unit and the FIFO unit are connected with the comparator unit, and the FIFO unit and the comparator unit are connected with the latch unit;
(2) the FIFO unit stores A, B and C groups of values; in a specific implementation, the FIFO unit may be composed of three FIFOs, and the three FIFOs respectively store A, B and C values, where a value is a comparison value, B value is an output value, and C value is an output enable value.
(3) Reading A, B and C values from the FIFO cells;
(4) the comparator unit compares the value A output by the FIFO unit with the count value of the counter unit, and latches the current output data into the latch unit after clearing the counter unit when the value A is equal to the count value of the counter unit, wherein the calculation formula of the output data is as follows:
current output data ═ (last output data and (notc)) or (bandc); when the current output data is output data in an initial state, the last output data is 0;
(5) then the next set of A, B and C values are read from the FIFO and the process returns to step (4), so that the specified data can be output at the specified time, and the effect of the programmable timing generator can be achieved.
In a specific implementation, as shown in fig. 1, the counter unit receives signals of a clock, a run enable signal and a reset signal, and the FIFO unit receives a write enable signal;
when the reset is high, the counter unit is set to be-1, the FIFO unit is emptied at the same time, and the latch unit is set to be 0;
storing A, B and the value of C in the FIFO cell at the rising delay of the clock when reset low and write enable high; when the reset is low and the read enable is low, the FIFO unit outputs the most advanced data when the clock is delayed;
when the reset is low and the operation enable is high, the counter unit starts counting, the comparator unit compares the count value of the counter unit with the value A output by the FIFO unit, if the count value is equal, the counter unit is set to 0, the read enable of the FIFO unit is set to 1, the latch unit latches the output data, the FIFO unit outputs the next group of A, B and C values, and if the count value is not equal, the read enable of the FIFO unit is set to 0.
For example, when inputting two sets of data into the FIFO cells:
a first group: comparing the value A to 4, outputting the enabling value C to 1, and outputting the value B to 1;
second group: the comparison value a is 2, the output enable value C is 2, and the output value B is 2.
As shown in fig. 2, when the enable bit is 1, the internal starts to operate, and after 4 cycles, 1 is output, and after 2 cycles, the output value is 3.
The timing generator comprises a counter unit, an FIFO unit, a comparator unit and a latch unit, wherein the three groups of values A, B and C stored in the FIFO unit can be configured as required, so that the output timing can not be solidified and any timing can be output, and the CPU resource is very little.
Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.
Claims (3)
1. A programmable timing generator, comprising: the device comprises a counter unit, a FIFO unit, a comparator unit and a latch unit;
(1) the counter unit and the FIFO unit are connected with the comparator unit, and the FIFO unit and the comparator unit are connected with the latch unit;
(2) the FIFO unit stores A, B and C groups of values configured as required; wherein, A is a comparison value, C is an output enabling value, and B is an output value;
(3) reading A, B and C values from the FIFO cells;
(4) the comparator unit compares the value A output by the FIFO unit with the count value of the counter unit, and latches the current output data into the latch unit after clearing the counter unit when the value A is equal to the count value of the counter unit, wherein the calculation formula of the current output data is as follows:
current output data (last output data and (notc)) or (b and c); when the current output data is output data in an initial state, the last output data is 0;
(5) then the next set of A, B and C values is read from the FIFO element and the process returns to step (4).
2. The programmable timing generator of claim 1, wherein: the counter unit receives signals of a clock, operation enable and reset, and the FIFO unit receives signals of write enable;
when the reset is high, the counter unit is set to be-1, the FIFO unit is emptied at the same time, and the latch unit is set to be 0;
storing A, B and the value of C in the FIFO cell at the rising delay of the clock when reset low and write enable high; when the reset is low and the read enable is low, the FIFO unit outputs the most advanced data when the clock is delayed;
when the reset is low and the operation enable is high, the counter unit starts counting, the comparator unit compares the count value of the counter unit with the value A output by the FIFO unit, if the count value is equal, the counter unit is set to 0, the read enable of the FIFO unit is set to 1, the latch unit latches the output data, the FIFO unit outputs the next group of A, B and C values, and if the count value is not equal, the read enable of the FIFO unit is set to 0.
3. The programmable timing generator of claim 1 or 2, wherein: the FIFO unit consists of three FIFOs, wherein the three FIFOs are used for storing A, B and C values respectively, the A value is a comparison value, the B value is an output value, and the C value is an output enabling value.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610020516.1A CN105718402B (en) | 2016-01-13 | 2016-01-13 | Programmable timing generator |
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| CN201610020516.1A CN105718402B (en) | 2016-01-13 | 2016-01-13 | Programmable timing generator |
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| CN105718402A CN105718402A (en) | 2016-06-29 |
| CN105718402B true CN105718402B (en) | 2021-04-20 |
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| CN112073472B (en) * | 2020-08-18 | 2023-04-07 | 浙江鸿城科技有限责任公司 | Soft zero clearing processing method for counter |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1119813A (en) * | 1994-05-06 | 1996-04-03 | 三星电子株式会社 | Variable Length Decoder for Image Signals |
| CN101535917A (en) * | 2006-03-08 | 2009-09-16 | 飞思卡尔半导体公司 | Dynamic timing adjustment in a circuit device |
| CN102207922A (en) * | 2010-03-30 | 2011-10-05 | 新唐科技股份有限公司 | Bus interface and clock frequency control method of bus interface |
| CN102902648A (en) * | 2012-10-11 | 2013-01-30 | 东莞润风电子科技有限公司 | A DMA-based GPIO module capable of flashing LED displays |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003263884A (en) * | 2002-03-07 | 2003-09-19 | Mitsubishi Electric Corp | Fifo circuit |
| JP4681830B2 (en) * | 2004-06-24 | 2011-05-11 | パナソニック株式会社 | PWM circuit and PWM circuit control method |
| CN1937424A (en) * | 2006-07-27 | 2007-03-28 | 重庆重邮信科股份有限公司 | Method for designing timing control circuit and its circuit |
| CN100419696C (en) * | 2006-08-10 | 2008-09-17 | 北京中星微电子有限公司 | Safeguard device and safeguard interruption prewarm method |
| KR20120032104A (en) * | 2010-09-28 | 2012-04-05 | 삼성전자주식회사 | Under-run compensation circuit, method thereof, and apparatuses having the same |
| CN103200407B (en) * | 2013-04-16 | 2016-05-18 | 中国科学院光电技术研究所 | Self-adaptive entropy encoder |
-
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- 2016-01-13 CN CN201610020516.1A patent/CN105718402B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1119813A (en) * | 1994-05-06 | 1996-04-03 | 三星电子株式会社 | Variable Length Decoder for Image Signals |
| CN101535917A (en) * | 2006-03-08 | 2009-09-16 | 飞思卡尔半导体公司 | Dynamic timing adjustment in a circuit device |
| CN102207922A (en) * | 2010-03-30 | 2011-10-05 | 新唐科技股份有限公司 | Bus interface and clock frequency control method of bus interface |
| CN102902648A (en) * | 2012-10-11 | 2013-01-30 | 东莞润风电子科技有限公司 | A DMA-based GPIO module capable of flashing LED displays |
Non-Patent Citations (1)
| Title |
|---|
| 利用TIMER的捕获比较功能模拟MSP430 UART的研究;付明;《沈阳大学学报》;20081231;第20卷(第6期);第114-116页 * |
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