CN105703780B - Matrix keyboard Scan orientation circuit - Google Patents

Abstract

A matrix keyboard scanning positioning circuit is composed of a matrix keyboard, a buffer register, a status code register and an encoder. The circuit converts the positioning of single-key operation, combined key operation, and keyboard maintenance state operation into valid state codes and invalid state codes of the same binary length through clock pulse scanning, and the encoder outputs the corresponding to each valid state code. Valid key numbers or output invalid key numbers corresponding to all invalid state codes; different single-key operations, key combination operations, and keyboard maintenance state operations are only reflected in the different state codes; if you need to increase or decrease key operation functions or adjust The key operation function does not need to modify the structure of the keyboard scanning circuit, but only needs to change the encoder according to the corresponding relationship between the increased and decreased state code and the key number. The inventive circuit does not need to write and run programs, and works reliably.

Description

Matrix keyboard scanning positioning circuit

technical field

The invention relates to a keyboard scanning circuit, in particular to a matrix keyboard scanning and positioning circuit.

Background technique

With the continuous development of embedded technology, various electronic products generally use microcontrollers as the control core, and keyboards as the main input device, which have been widely used.

The current keyboard scanning is mainly controlled by the microcontroller, which needs to be carried out by running the program in the microcontroller. When encountering interference, the program will run away, and the scanning program will not work normally.

The invention patent with the application number CN201010153560.2 "A Quick Scanning and Positioning Method for a Matrix Keyboard" adopts the method of keyboard interrupt triggering to enter the scanning and positioning process of the keyboard, and uses the method of repeating the keyboard scanning steps several times to determine whether the keys are valid, and The state of the obtained key value is judged; if the state of multiple sampling is the same, it is in a stable state, and the key value is valid; if the state of multiple sampling is different, the key value is invalid. A single key operation or a key combination operation needs to be judged separately. If it is a single key operation, enter the single key processing mode; if it is a key combination operation, enter the key combination processing mode. The method described in this patent solves the problems of wrong keys, continuous key touches and other errors caused by the keyboard shaking caused by the mechanical characteristics of the keyboard itself, as well as the problem of support for combination keys and repeated keys. However, the single-key operation and the combined key operation of the method need to be processed separately; the keyboard operation function of effective operation is not performed after the keyboard state is maintained for a period of time; when increasing or decreasing the key operation function or adjusting the key operation function, it is necessary to modify the keyboard scan Locating the program structure.

Contents of the invention

In order to solve the above-mentioned technical problems existing in the existing keyboard scanning positioning method, the present invention provides a matrix keyboard scanning positioning circuit, which is composed of a matrix keyboard, a buffer register, a status code register, and an encoder.

The matrix keyboard has X rows and Y columns in total, and is provided with an N-bit keyboard status signal output terminal; the N-bit keyboard status signal is a level signal; and the N=X+Y.

The buffer register is an N-bit binary register; the N-bit data input end of the buffer register is connected to the N-bit keyboard state signal output end.

The status code register is a 2×N bit binary register; the N bits in the 2×N bit data input terminals of the status code register are connected to the N bit keyboard status signal output terminals, and the other N bits are connected to the N bit data output of the buffer register end.

The encoder has a 2×N-bit coding input terminal, and the 2×N-bit coding input terminal is connected to the 2×N-bit data output terminal of the state code register; the encoder has an M-bit key number output terminal.

Both the receiving pulse input end of the buffer register and the receiving pulse input end of the status code register are connected to the clock pulse.

Described matrix type keyboard is made up of X row-Y row button matrix, row tristate buffer, row tristate buffer, row status register, column status register; Output terminals, the column lines of all key matrixes are respectively connected to the output terminals of the column tri-state buffers; all input terminals of the row tri-state buffers and column tri-state buffers are connected to low level; the row lines of all key matrixes are respectively connected to To the input end of the row state register, all the column lines of the key matrix are respectively connected to the input end of the column state register; the output end of the row state register and the output end of the column state register together form a keyboard state signal output end.

The matrix keyboard is controlled by the sampling pulse to obtain the keyboard state signal; when the low level of the sampling pulse is enabled and valid, the row tri-state buffer requires the column state register to perform data latching and column three on the rising edge of the sampling pulse. The state buffer is enabled at the high level of the sampling pulse, and the row status register performs data latching at the falling edge of the sampling pulse; or, when the row tri-state buffer is enabled at the high level of the sampling pulse, it requires the column The status register performs data latching on the falling edge of the sampling pulse, the column tri-state buffer is enabled and valid at the low level of the sampling pulse, and the row status register performs data latching on the rising edge of the sampling pulse.

The buffer register and the status code register perform data latching simultaneously on the rising edge of the clock pulse, or simultaneously perform data latching on the falling edge of the clock pulse; the 2×N bit data output terminals of the status code register output 2×N bit The status code; the status code is composed of valid status code and invalid status code; the key number output by the encoder is composed of valid key number and invalid key number; The corresponding valid key number is output when the encoder inputs each valid status code; the invalid status code is generated by an invalid keyboard operation or state, and the encoder outputs corresponding invalid key numbers when all invalid status codes are input.

The encoder has an M-bit key number output terminal, and the selection of the M value should meet the requirement that 2 ^M be greater than or equal to the sum of the valid key numbers and the invalid key numbers.

The period of the clock pulse is 20-100 ms; the period of the sampling pulse is not greater than the period of the clock pulse, and a special example is that the sampling pulse is the clock pulse.

The matrix keyboard scanning positioning circuit also includes an oscillator; the oscillator outputs clock pulses and sampling pulses.

The matrix keyboard scanning positioning circuit also includes a keyboard state change pulse generating unit for judging whether the key numbers output by the matrix keyboard change, and outputting keyboard state change pulses when the key numbers output by the matrix keyboard change.

The keyboard state change pulse generation unit is made up of an M-bit delay buffer, M exclusive-or gates and an OR gate; the M-bit delay buffer is used to respectively carry out signal delay on the M-bit key numbers output by the matrix keyboard; M exclusive-or gates The inputs of the gates are the input and output signals of the M-bit delay buffer respectively; the outputs of the M XOR gates are respectively connected to the input terminals of the OR gates; the output terminals of the OR gates output keyboard state change pulses.

The N bits, 2×N bits, and M bits all refer to binary bit data.

The beneficial effects of the present invention are: the positioning of single-key operation, combined key operation, and keyboard maintenance state operation is converted into a state code of the same binary length by clock pulse scanning, and is processed in a unified coding manner. Single-key operation, combination Key operation and keyboard maintenance state operation are only reflected in the difference of the status code; if it is necessary to increase or decrease the key operation function or adjust the key operation function, there is no need to modify the keyboard scanning circuit structure, just according to the increased or decreased status code and key number The corresponding relationship between the coder can be changed, that is, the stored content of the read-only memory can be rewritten. The circuit of the invention does not use microcontrollers such as single-chip microcomputers and ARMs, does not need to run programs, and works reliably.

Description of drawings

Fig. 1 is a schematic block diagram of a matrix keyboard scanning positioning circuit;

Fig. 2 is a matrix keyboard circuit diagram of an embodiment of the present invention;

Fig. 3 is the scanning positioning circuit diagram of the embodiment of the present invention;

Fig. 4 is the circuit diagram of the keyboard state change pulse generation unit of the embodiment of the present invention;

FIG. 5 is a schematic diagram of waveforms related to the effective operation of the keyboard according to the embodiment of the present invention.

Detailed ways

The present invention will be further described below in conjunction with accompanying drawing.

1 is a schematic block diagram of a matrix keyboard scanning and positioning circuit, which is composed of a matrix keyboard 400 , a buffer register 100 , a status code register 200 , an encoder 300 and an oscillator 500 .

The oscillator 500 is a multivibrator with a CP clock pulse output terminal and a CK sampling pulse output terminal. The period of the CP clock pulse is 20-100 ms, and the period of the CK sampling pulse is not greater than the period of the CP clock pulse.

2 is a circuit diagram of a matrix keyboard 400 according to an embodiment of the present invention. There are 2 rows and 2 columns, and 4 keys in total, consisting of key S1, key S2, key S3, key S4 and the pull-up resistor R1 connected to the power supply +VCC , pull-up resistor R2, pull-up resistor R3, pull-up resistor R4, row tri-state buffer 401, column tri-state buffer 402, row status register 403, and column status register 404. The two output terminals Y1 and Y2 of the row tri-state buffer 401 are respectively connected to two row lines, and the two output terminals Y3 and Y4 of the column tri-state buffer 402 are respectively connected to two column lines; the row tri-state buffer 401 All input terminals X1 ˜ X4 of the sum column tri-state buffer 402 are connected to low level.

The two input terminals D41 and D42 of the row status register 403 are respectively connected to two row lines, and the two input terminals D43 and D44 of the column status register 404 are respectively connected to two column lines; the two output terminals Q41 of the row status register 403 , Q42 output row status signals I1, I2, 2 output terminals Q43, Q44 of column status register 404 output column status signals I3, I4; 2 output terminals of row status register 403 are common with 2 output terminals of column status register 404 4-bit keyboard status signal output terminals are formed to output keyboard status signals I1, I2, I3, and I4.

In an embodiment, the enable input EN1 of the row tri-state buffer 401 is active at low level, and the enable input EN2 of the column tri-state buffer 402 is active at high level; both EN1 and EN2 are connected to the CK sampling pulse output of the oscillator 500 end. The receiving pulse input terminals CLK3 and CLK4 of the row status register 403 and the column status register 404 are all connected to the CK sampling pulse output terminal of the oscillator 500, the row status register 403 performs data latching on the falling edge of the CK sampling pulse, and the column status register 404 Data is latched on the rising edge of the CK sampling pulse.

When row tri-state buffer 401 and column tri-state buffer 402 use the same type of tri-state buffer, for example, when tri-state buffer 74HC241 is used at the same time, the enable input of 74HC241 is active high, so the CK sampling pulse Between the output end and the enable input end EN1 of the row tri-state buffer 401 , a NOT gate needs to be added. Similarly, when row status register 403 and column status register 404 use the same type of data register, for example, when row status register 403 and column status register 404 both use double D flip-flops 74HC74 to form data registers, the trigger input of 74HC74 is valid on the rising edge , therefore, a NOT gate needs to be added between the CK sampling pulse output terminal and the receiving pulse input terminal CLK3 of the row status register 403 .

The buffer register 100, the status code register 200, and the encoder 300 in FIG. 1 form a scanning positioning circuit, and its embodiment circuit diagram is shown in FIG. 3 . The matrix keyboard circuit has 4 keys, and the keyboard state signal output by the matrix keyboard is a 4-bit binary code. Therefore, the buffer register 100 is required to store 4-bit binary data, and the status code register 200 is required to store 8-bit binary data. The 4 data input terminals of buffer register 100 are connected to I1, I2, I3, I4; Among the 8 data input terminals of status code register 200, 4 data input terminals are connected to I1, I2, I3, I4, and the other 4 data input terminals The input terminals are connected to the 4 output terminals of the buffer register 100 ; the 8 input terminals of the encoder 300 are connected to the 8 output terminals of the status code register 200 . The encoder 300 outputs the 4-digit binary key number determined through scanning and positioning.

In FIG. 3 , the flip-flop 101 forms the buffer register 100 , and the flip-flop 201 forms the status code register 200 . Flip-flop 101 is made up of 4 edge triggers, and the trigger input end of 4 edge triggers is the receiving pulse input end of buffer register 100, is connected to the CP clock pulse output end of oscillator 500; Flip-flop 201 is made up of 8 edge triggers The trigger input terminals of the eight edge triggers are the receiving pulse input terminals of the status code register 200 , and are all connected to the CP clock pulse output terminals of the oscillator 500 . Flip-flop 101 and flip-flop 201 are preferably composed of edge-triggered D flip-flops, for example, composed of double D flip-flop 74HC74 and 4D flip-flop 74HC175. In the embodiment of Fig. 3, flip-flop 101 and flip-flop 201 both select the 8D flip-flop 74HC273 triggered by the rising edge. At this time, the clear input terminal not shown in Fig. The function is in an invalid state and only has a trigger function; the flip-flop 101 only needs 4D flip-flops, and the 4 D flip-flops in the selected 8D flip-flop 74HC273 can be used arbitrarily. The trigger input terminals CLK1 and CLK2 of the two 8D flip-flops 74HC273 are connected to the CP.

In FIG. 3 , the read-only memory constitutes the encoder 300 . Address input terminals A7 - A0 of the ROM are input terminals of the encoder 300 , and data output terminals D3 - D0 of the ROM are encoding output terminals C3 - C0 of the encoder 300 .

The working principle of the matrix keyboard scanning positioning circuit is as follows:

In Figure 2, the 4 keys of the matrix keyboard are arranged in a 2×2 matrix, and all row lines and column lines are connected to the power supply +VCC through pull-up resistors. The matrix keyboard is controlled by CK sampling pulse, and the keyboard status signals I4, I3, I2, and I1 are obtained by the inversion method. For example, the keyboard status signal of no key pressed is 1111, the keyboard status signal of S1 pressed is 1010, and the keyboard status signal of S1 and S2 pressed simultaneously is 0010. The 4-bit binary code of the keyboard status signal is called the key value.

CK sampling pulse control The method of sampling and reading the key value of the matrix keyboard is: at the low level of the CK sampling pulse, control all row lines to output low level through the row tri-state buffer 401, and the column tri-state buffer 402 outputs High-impedance state opens the column line; at the rising edge of the CK sampling pulse, the column state register 404 samples and reads the column line state as the upper 2 bits of the key value; at the high level of the CK sampling pulse, it is controlled by the column tri-state buffer 402 All column lines output low level, and the row tri-state buffer 401 outputs a high-impedance open row line; at the falling edge of the CK sampling pulse, the state of the row line is sampled and read by the row state register 403 as the lower 2 bits of the key value; the above process Repeatedly, the 4-bit key value output by the column state register 404 and the row state register 403 is always the latest state of the matrix keyboard.

From the method of sampling and reading the key value of the matrix keyboard by controlling the CK sampling pulse, it can be seen that the row tri-state buffer 401 requires the column state register 404 to be activated when the CK sampling pulse rises when the row tri-state buffer 401 is active. Data latching is performed on the edge, the column tri-state buffer 402 is enabled and valid at the high level of the CK sampling pulse, and the row status register 403 is data latched on the falling edge of the CK sampling pulse. Conversely, if the row tri-state buffer 401 is valid when the high level of the CK sampling pulse is enabled, the column status register 404 is required to perform data latching on the falling edge of the CK sampling pulse, and the column tri-state buffer 402 is required to perform data latching at the falling edge of the CK sampling pulse. The low level of the pulse is effective, and the row status register 403 performs data latching on the rising edge of the CK sampling pulse.

In the above-mentioned CK sampling pulse control sampling and reading key value process, the moment when the row state register 403 and the column state register 404 are sampled is exactly the moment when the state of the column tri-state buffer 402 and the row tri-state buffer 401 are reversed, The row status register 403 or the column status register 404 under normal operation can be correctly sampled. If a certain timing margin is required, the CK sampling pulse connected to the column tri-state buffer 402 and the row tri-state buffer 401 can be delayed by making the CK sampling pulse pass through an RC delay circuit and then connected to the row three The delay time of EN1 and EN2 of state buffer 401 and column tri-state buffer 402 is determined by the RC delay circuit. The principle of determining the delay time of the RC delay circuit is that the delayed CK sampling pulse phase does not exceed 90°; or CK sampling The pulse is buffered by several gate circuits and then connected to EN1 and EN2 of the row tri-state buffer 401 and column tri-state buffer 402 , and the delay time at this time is the total delay time of the several gate circuits.

Under the control of the CP clock pulse, the buffer register 100 and the status code register 200 perform data latching on the effective trigger edge of each cycle of the CP. In Fig. 3, 74HC273 is effective for the rising edge trigger, therefore, the effective trigger edge of the CP clock pulse is the rising edge.

Among the 8 data input terminals of the status code register 200, 4 data input terminals D20-D23 are directly connected to the status signals I1, I2, I3, and I4 output by the matrix keyboard, and the other 4 data input terminals D24-D27 are connected to the buffer The data output terminals Q10～Q13 of the register 100, and the 4 data input terminals D10～D13 of the buffer register 100 are directly connected to the status signals I1, I2, I3, and I4 output by the matrix keyboard. Therefore, at the effective trigger edge of the CP clock pulse , among the 8 data output terminals of the state code register 200, the data latched by the 4 data output terminals Q20-Q23 corresponding to the state signals I1, I2, I3, and I4 directly connected to the matrix keyboard output are matrix keyboard Its 4-bit data is called the current state key value; the data latched by the 4 data output terminals Q24-Q27 corresponding to the data output terminals connected to the buffer register 100 is the previous state of the matrix keyboard, and its The 4-bit data is called the pre-state key. The 4-bit current state key value and the 4-bit previous state key value output by the data output terminal of the status code register 200 together form an 8-bit status code.

The 8-bit status code is used to identify the current status and operating status of the matrix keyboard. For example, in this embodiment, the state code of pressing no key is 11111111; the state code of S1 key single key press operation is 11111010; the state code of S1 key single key press and maintenance is 10101010; S1 key single key release operation The status code of the S2 button is 10101111; the status code of the S2 key single-key press operation is 11110110; the S4 key single-key press operation status code is 11110101; the S1 press operation of the S2+S1 combination operation means that after pressing S2 first, When S2 is kept pressed and then S1 is pressed, the status code of this operation is 01100010.

The encoder 300 is used to convert the status code into a key number. In the embodiment, there are 6 effective keyboard operations and states, including:

Operation 0: Single key press operation of key S1, key number is 0000;

Operation 1: Single key press operation of key S2, the key number is 0001;

Operation 2: Single key press operation of key S3, key number is 0010;

Operation 3: The key number is 0011 after the key S3 is pressed to maintain the state;

Operation 4: After pressing the single key of the key S4, then press the key combination of the key S2 to operate, the key number is 0100;

Operation 5: Single-key release operation of key S1, the key number is 0101.

See code table 1 for the status code and key number obtained according to the above regulations:

Table 1 Coding table

keyboard operation status code (address) key number (store data) S1 single key press 11111010 0000 S2 single key press 11110110 0001 S3 single key press 11111001 0010 S3 single key press hold 10011001 0011 S4+S2 combination operation 01010100 0100 S1 single key release 10101111 0101 other operations or states *********** 1111

The encoder 300 is a combinational logic circuit, and it is only necessary to design the circuit to satisfy the logical relationship in Table 1.

The encoder 300 of an embodiment preferably consists of a read-only memory. The read-only memory has an 8-bit address, a total of ²⁸ 4-bit binary storage units. 6 valid keyboard operations and states have 6 valid status codes, corresponding to 6 valid key numbers; use the status codes as the addresses A7-A0 of the read-only memory, in the storage unit corresponding to the 6 valid status codes, Write the corresponding key number as stored data. The status codes other than the 6 valid keyboard operations and statuses are invalid status codes, that is, the status codes generated by other operations or statuses in Table 1 are invalid status codes; in other storage units, all invalid key numbers are written, invalid The key number is a value other than 6 valid key numbers. In the embodiment, the invalid key number is 1111.

The read-only memory has been working in the data output state. When the read-only memory has chip selection control and data output buffer control functions, the chip selection control and data output buffer control should be in an effective state.

The key number in the embodiment is a 4-bit binary code. The binary digits of the key number can be increased or decreased as required. At this time, it is only necessary to select the matching ROM. Assuming that the binary digits of the key number is M, the selection of the M value should meet the requirement that 2 ^M be greater than or equal to the sum of the number of valid key numbers and invalid key numbers. When the matrix keyboard has N-bit keyboard status signal output, the ROM needs to have 2×N-bit address input and M-bit data output.

If it is necessary to increase or decrease the key operation function or to adjust the key operation function, it is only necessary to modify Table 1 as required, and rewrite the modified content to the storage content of the read-only memory.

In the embodiment, when the matrix keyboard S1 single key is pressed, the encoder 300 starts from the effective trigger edge of the CP clock pulse after the S1 single key is pressed, and until the effective trigger edge of the next CP clock pulse, the encoding output terminal C3～C0 output key number 0000; when matrix keyboard S2 single key is pressed, encoder 300 starts from the effective trigger edge of CP clock pulse after S2 single key is pressed, and ends at the effective trigger edge of next CP clock pulse , the output key number is 0001; when the matrix keyboard first presses S4 and then presses S2, the encoder 300 starts at the effective triggering edge of the CP clock pulse after the S2 combination key is pressed, and ends at the effective triggering of the next CP clock pulse When the matrix keyboard S1 single key is released, the encoder 300 starts from the effective trigger edge of the CP clock pulse after the S1 single key is released, and outputs until the effective trigger edge of the next CP clock pulse. Key number 0101; therefore, it can be seen that when the effective key operation of the matrix keyboard is identified, the encoder 300 starts at the effective trigger edge of the CP clock pulse after the effective key operation, until the effective trigger of the next CP clock pulse Output the valid key number whose duration is the width of one CP clock pulse period.

In the embodiment, when the matrix keyboard S3 single key is pressed, the encoder 300 starts from the effective trigger edge of the CP clock pulse after the S3 single key is pressed, and outputs the key number until the effective trigger edge of the next CP clock pulse 0010; at the beginning of the effective trigger edge of the next CP clock pulse, until the effective trigger edge of the next CP clock pulse after the end of the S3 single key press maintenance state, the encoder 300 outputs the key number 0011; therefore it can be seen that, When the recognized state of the matrix keyboard is maintained, the duration for which the encoder 300 outputs valid key numbers is adapted to the duration of the maintained state.

When the state or operation of the keyboard is out of the six valid keyboard operations and states described in Table 1, the encoder 300 outputs an invalid key number 1111 . Whether outputting a valid key number or an invalid key number, the moment when the encoder 300 changes the output content is the valid trigger edge of the CP clock pulse; in the embodiment, the moment when the encoder 300 changes the output content is the rising edge of the CP clock pulse.

The period of the CP clock pulse is the scanning period of the matrix keyboard. When the keyboard scanning period is above 20ms, it can effectively avoid the influence of keyboard key shake; when the keyboard scanning period is below 100ms, the keyboard operation will not be missed; therefore, the period of the CP clock pulse should be controlled at 20-100ms.

The period of the CK sampling pulse is required to be no greater than the period of the CP clock pulse. In this way, when the status code is obtained at each effective trigger edge of the CP clock pulse, it can be guaranteed that the 4-bit key value output by the column status register 404 and the row status register 403 is always a matrix The latest status of keyboards. A special case of the CK sampling pulse is to directly use the CP clock pulse as the CK sampling pulse.

In the embodiment, both the CP clock pulse and the CK sampling pulse are generated and output by the oscillator 500 . The CP clock pulse and CK sampling pulse can also be provided by circuits or devices other than the matrix keyboard scanning and positioning circuit.

FIG. 4 is a circuit diagram of a keyboard state change pulse generating unit according to an embodiment of the present invention. When identifying an effective key operation of the matrix keyboard, the encoder 300 starts at the effective trigger edge of the CP clock pulse after the effective key operation, and until the effective trigger edge of the next CP clock pulse, the output duration is one CP Valid key numbers for clock pulse period width. The device receiving the output of the matrix keyboard needs to query the output of the matrix keyboard at all times to obtain the key numbers. The cycle interval of the query must be smaller than the cycle of the CP clock pulse.

The circuit shown in Figure 4 is used to judge whether the key number output by the matrix keyboard changes. When the key number output by the matrix keyboard changes, the keyboard state change pulse is output, and the receiving device for assisting the matrix keyboard receives the matrix keyboard. The output key number, for example, takes the keyboard state change pulse as an interrupt request signal of the receiving device.

The circuit shown in FIG. 4 is composed of a delay buffer 601 , an exclusive OR gate 602 , an exclusive OR gate 603 , an exclusive OR gate 604 , an exclusive OR gate 605 , and an OR gate 606 . The delay buffer 601 is composed of 4 edge triggers with only trigger functions, and the trigger input terminals of the 4 edge triggers are the receiving pulse input terminals of the delay buffer 601, which are all connected to the CP clock pulse output terminal of the oscillator 500; The delay buffer 601 performs data latching on the valid trigger edge of the CP clock pulse.

The delay buffer 601 is used to respectively perform delay processing on the 4-bit data C3 - C0 at the encoded output end of the encoder 300 . The four data input terminals D63～D60 of the delay buffer 601 are connected to the encoding output terminals C3～C0 of the encoder 300, and the corresponding output data of the four data output terminals Q63～Q60 of the delay buffer 601 are C31～C01; C31～C01; After C01 is first buffered by the delay buffer 601, its signal is delayed by one CP clock pulse cycle than C3-C0. FIG. 5 is a schematic diagram of relevant waveforms of the effective operation of the keyboard according to the embodiment of the present invention. Set in the T1 interval of the CP clock pulse, there is an effective operation of the matrix keyboard, and the effective operations of the embodiment include: S1 single key press, S2 single key press, S3 single key press, S2 key press of S4+S2 combined operation Down, S1 single key release. On the next valid trigger edge of a valid operation, that is, the rising edge after the CP clock pulse T1 interval in Figure 5, the codes C3-C0 output by the encoder 300 change; in the T2 interval, the encoder 300 outputs a valid code of one cycle C3～C0; in T3, T4 and subsequent intervals, the codes C3～C0 output by the encoder 300 change again and enter the maintenance state. This maintenance state may be, for example, the maintenance state after the S1 single key is pressed, and an invalid key number is output. It may also be the maintenance state after the S3 single key is pressed, and the effective key number is output until the next effective operation.

The D6 pulse in FIG. 5 schematically indicates whether the codes C3-C0 output by the encoder 300 are in a maintained state, unchanged, or changed. The D6 pulse does not exist in the actual circuit. As shown in Figure 5, the D6 pulse is at a low level, which schematically indicates that the codes C3-C0 output by the encoder 300 are in a maintained state and does not change; the D6 pulse is at a high level, which schematically indicates that the encoder 300 outputs a valid code for one cycle C3～C0. What Q6 in Fig. 5 reflects is the change situation of C31～C01, obviously, Q6 delays one CP clock pulse period than D6. Likewise, the Q6 pulse does not exist in the actual circuit.

In FIG. 5 , whether the codes C3-C0 output by the encoder 300 are in a maintained state, unchanged, or changed, is actually determined by the 4-bit delay buffer 601, the exclusive OR gate 602, the exclusive OR gate 603, the exclusive OR gate 604, The logic circuit formed by the XOR gate 605 and the OR gate 606 is completed. The 4 XOR gates correspond to 1 bit of the encoding output terminals C3 - C0 of the encoder 300 respectively, and the inputs are the input and output signals of the 4-bit delay buffer 601 . For example, the two input signals of the exclusive OR gate 602 are C0 and C01 respectively, and C01 is delayed by one CP clock pulse cycle than C0, so when C0 changes, the exclusive OR gate 602 outputs a positive pulse with a width of one CP clock pulse cycle ; When C0 is a CP clock pulse cycle width change signal, the XOR gate 602 outputs a positive pulse with a CP clock pulse cycle width of 2. The XOR gate 603 , the XOR gate 604 , and the XOR gate 605 respectively judge whether C1 - C3 change, and the principle is the same as judging whether C0 changes. The output terminals of the exclusive OR gate 602, the exclusive OR gate 603, the exclusive OR gate 604, and the exclusive OR gate 605 are respectively connected to the input terminals of the OR gate 606, and the OR gate 606 is used for comprehensively judging whether C0～C3 changes, as long as C0～C3 change, the OR gate 606 outputs the keyboard state change pulse F, which is a positive pulse.

In an embodiment, the delay buffer 601 selects a rising edge triggered 8D flip-flop 74HC273. In the embodiment, the output of the encoder 300 is a 4-bit binary key number, therefore, the delay buffer 601 only needs 4 D flip-flops. Since the trigger inputs of the four D flip-flops in the delay buffer 601 and the four D flip-flops in the flip-flop 101 are connected to the CP clock pulse output of the oscillator 500, the delay buffer 601 and the flip-flop 101 Can share an 8D flip-flop 74HC273.

Delay buffer 601 can also adopt other schemes, for example, adopt RC circuit, use 4 RC circuits to delay C0～C3 respectively; When the effective codes are C3~C0, a keyboard state change pulse is generated at the beginning of outputting effective codes C3~C0 and at the end of outputting effective codes C3~C0, and the width of the keyboard state changing pulse is equal to the delay time of the RC circuit; if the delay time of the RC circuit is greater than Equal to one CP clock pulse period, when the encoder 300 outputs one period of valid codes C3-C0, a keyboard state change pulse is generated at the beginning of outputting valid codes C3-C0, and the pulse width is greater than or equal to 2 CP clock pulse periods. It is required that the delay time of the RC circuit does not exceed 2 CP clock pulse cycles to avoid false positives.

In the described invention circuit, the positioning of single-key operation, combination key operation, and keyboard maintenance state operation is converted into a state code of the same binary length by CP pulse scanning, and is processed in a unified coding manner. Single-key operation, combination Key operation and keyboard maintenance state operation are only reflected in the different status codes; if you need to increase or decrease the key operation function or adjust the key operation function, you do not need to modify the structure of the keyboard scanning circuit, you only need to update the code according to the state code table after the increase or decrease device 300, that is, rewrite and update the storage content of the read-only memory. The circuit of the invention does not use microcontrollers such as single-chip microcomputers and ARMs, does not need to run programs, and works reliably.

Claims (6)

1. a kind of matrix keyboard Scan orientation circuit, which is characterized in that posted by matrix keyboard, buffer register, conditional code Storage, encoder composition；

The matrix keyboard shares X rows, Y row, is equipped with N bit keyboard status signal outputs；The N bit keyboards status signal is Level signal；The N=X+Y；

The buffer register is N binary registers；The positions the N data input pin of buffer register is connected to N bit keyboard shapes State signal output end；

The state Code memory is 2 × N binary registers；N in the positions the 2 × N data input pin of state Code memory Position is connected to N bit keyboard status signal outputs, in addition the N positions the N data output ends for being connected to buffer register；

The encoder has 2 × N coding input ends, the coding input end 2 × N to be connected to 2 × N of state Code memory Position data output end；

The reception pulse input end of the buffer register and the reception pulse input end of state Code memory are connected to clock Pulse；The matrix keyboard is controlled by sampling pulse and obtains N bit keyboard status signals.

2. matrix keyboard Scan orientation circuit according to claim 1, it is characterised in that：The matrix keyboard is by X Row-Y row key-press matrix, row three state buffer, row three state buffer, row status register, column-shaped state register group at；It is all to press The line of key matrix is respectively connected to the output end of row three state buffer, and the alignment of all key-press matrixs is respectively connected to row tri-state The output end of buffer；All input terminals of row three state buffer and row three state buffer are connected to low level；It is all to press bond moment The line of battle array is respectively connected to the input terminal of row status register, and the alignment of all key-press matrixs is respectively connected to row Status register The input terminal of device；The output end of the row status register collectively constitutes keyboard state signal with the output end of row status register Output end.

3. matrix keyboard Scan orientation circuit according to claim 2, it is characterised in that：The row three state buffer exists When the low level of sampling pulse enables effective, it is desirable that row status register carries out data latch, row in the rising edge of sampling pulse Three state buffer carries out data lock in enabled effective, the row status register of high level of sampling pulse in the failing edge of sampling pulse It deposits；Either, row three state buffer is when the high level of sampling pulse enables effective, it is desirable that row status register is in sampling pulse Failing edge carry out data latches, row three state buffer the low level of sampling pulse is enabled effectively, row status register is taking The rising edge of sample pulse carries out data latch.

4. matrix keyboard Scan orientation circuit according to claim 1, it is characterised in that：The buffer register and shape State Code memory is carried out at the same time data in the rising edge of clock pulses and latches, or is carried out at the same time number in the failing edge of clock pulses According to latch；2 × N data output ends of the state Code memory export 2 × N conditional codes；The conditional code is by effective shape State code and invalid state code composition；The key number of the encoder output is made of effective key number and invalid key number；Effective shape State code is generated by effective keyboard operation or state, and encoder corresponds to output corresponding effective key when inputting each effective status code Number；The invalid state code is generated by invalid keyboard operation or state, and encoder all corresponds to defeated when inputting all invalid state codes Go out invalid key number.

5. matrix keyboard Scan orientation circuit according to claim 4, it is characterised in that：The encoder has M keys Number output end, the selection of M values should meet 2^MMore than or equal to the sum of effective key number and the quantity of invalid key number.

6. a kind of matrix keyboard Scan orientation circuit according to claim 5, it is characterised in that：It further include keyboard state Change pulse generates unit, and whether the key number for the output of judgment matrix formula keyboard changes, when matrix keyboard output When key number changes, keyboard state change pulse is exported.