CN105702630A - Semiconductor structure and formation method thereof - Google Patents
Semiconductor structure and formation method thereof Download PDFInfo
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Abstract
The invention provides a semiconductor structure and a formation method thereof. The formation method of the semiconductor structure includes: a substrate and an etching stopping layer covering the surface of the substrate are provided, and a plurality of discrete bottom metal layers are arranged in the substrate; the etching stopping layer is etched, and grooves exposing the surfaces of the bottom metal layers are formed; by employing the self-alignment growth technology, electric connection layers filling the grooves are formed, and the electric connection layers are electrically connected with the bottom metal layers; and a plurality of discrete first graphene layers, storage medium layers positioned on the surfaces of the first graphene layers, and second graphene layers positioned on the surfaces of the storage medium layers are formed, and the first graphene layers are positioned on the surfaces of the electric connection layers and a part of the surface of the etching stopping layer. According to the semiconductor structure and the formation method thereof, the process steps are simplified, the adverse influence brought by extra process is avoided, the conversion efficiency and the erasing rate are improved, and the electrical performance of the semiconductor structure is optimized.
Description
Technical field
The present invention relates to field of semiconductor fabrication technology, particularly to a kind of semiconductor structure and forming method thereof。
Background technology
Non-liability memorizer has at non-transformer for the advantage at once remaining to keep data message, has very important status at area information storage, is also one of the study hotspot of current information memory technology。But, there is the problems such as operation voltage is high, speed is slow, endurance is poor in current main flow nonvolatile memory flash memory (flash)。Resistor type random access memory (RRAM, ResistanceRandomAccessMemory) has shown the advantages such as operating rate is fast, memory density is high, data hold time length, endurance are strong, is the strong candidate of generation semiconductor memorizer。
The basic unit of storage of resistor type random access memory includes metal-insulator-metal type (MIM, a Metal-insulation-Metal) construction unit。By voltage or current impulse, it is possible to make the resistance of mim structure unit change between high low resistance state, to realize write and the erasing of data。RRAM work it is crucial that the electric resistance changing of some material and memory effect, under voltage or the function of current, the resistance of these materials can send reversible, huge change。
But, the electric property of the semiconductor structure including resistor type random access memory that prior art is formed has much room for improvement。
Summary of the invention
The problem that this invention address that is to provide a kind of semiconductor structure and forming method thereof, Simplified flowsheet step, it is to avoid the harmful effect that grinding technics brings, and improves the electric property of semiconductor structure。
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor structure, including: substrate is provided and is covered in the etching stop layer of substrate surface, there is in described substrate some discrete bottom metal layers；Etch described etching stop layer, form the groove exposing bottom metal layer surface；Adopting autoregistration growth technique, form the electric connection layer filling full described groove, described electric connection layer electrically connects with bottom metal layer；Form some the first discrete graphene layers, be positioned at the storage medium layer on the first graphene layer surface and be positioned at second graphene layer on storage medium layer surface, and the first graphene layer is positioned at electric connection layer surface and partial etching stop-layer surface。
Optionally, the material of described electric connection layer is cobalt tungsten phosphorus, cobalt tungsten boron, cobalt tungsten phosphorus boron, cobalt molybdenum phosphorus, cobalt molybdenum boron, cobalt molybdenum chromium or cobalt molybdenum chromium boron。
Optionally, galvanoplastic are adopted to carry out described autoregistration growth technique。
Optionally, the material of described bottom metal layer is copper, when the material of electric connection layer is cobalt tungsten phosphorus, the electroplating solution of described galvanoplastic includes cobaltous sulfate, sodium citrate, boric acid, sodium hypohosphate and ammonium tungstate, the pH value of electroplating solution is 8.5 to 9.2, and electroplating solution temperature is 60 degrees Celsius to 85 degrees Celsius。
Optionally, the top of described electric connection layer flushes with etching stop layer surface。
Optionally, described bottom metal layer top flushes with substrate surface。
Optionally, described bottom metal layer top is lower than substrate surface；After etching described etching stop layer, also etching removes the substrate of segment thickness, forms described groove。
Optionally, the material of described storage medium layer is one or more in non-crystalline silicon, polysilicon, titanium oxide or aluminium oxide。
Optionally, the material of described etching stop layer is silicon nitride, carborundum or carbon dope silicon nitride。
Optionally, the thickness of described first graphene layer is 50 angstroms to 500 angstroms；The thickness of the second graphene layer is 50 angstroms to 500 angstroms。
Optionally, the material of described bottom metal layer be copper, aluminum or tungsten。
Optionally, the processing step forming described first graphene layer, storage medium layer and the second graphene layer includes: the storage medium film that sequentially form the first graphene film being covered in described electric connection layer surface and etching stop layer surface, is covered in described first graphene membrane surface, the second graphene film being covered in described storage medium film surface；The mask layer with opening is formed in described second graphene membrane surface；With described mask layer for mask, being sequentially etched the second graphene film, storage medium film and the first graphene film along opening, until exposing partial etching stop-layer surface, forming described first graphene layer, storage medium layer and the second graphene layer；Remove described mask layer。
Optionally, before there is described in being formed after described second graphene film, being formed the mask layer of opening, further comprise the steps of: and form the pellumina being covered in described second graphene membrane surface。
Optionally, the material of described mask layer is one or more in silicon oxide, silicon nitride, titanium nitride or tantalum nitride。
The present invention also provides for a kind of semiconductor structure, including: substrate and the etching stop layer being positioned at substrate surface, has some discrete bottom metal layers in described substrate；It is positioned at described etching stop layer and exposes the groove on bottom metal layer surface；Filling the electric connection layer of full described groove, described electric connection layer electrically connects with bottom metal layer；It is positioned at the first some discrete graphene layer on described electric connection layer surface and partial etching stop-layer surface；It is positioned at the storage medium layer on described first graphene layer surface；It is positioned at second graphene layer on described storage medium layer surface。
Optionally, the material of described electric connection layer is cobalt tungsten phosphorus, cobalt tungsten boron, cobalt tungsten phosphorus boron, cobalt molybdenum phosphorus, cobalt molybdenum boron, cobalt molybdenum chromium or cobalt molybdenum chromium boron。
Optionally, described electric connection layer top flushes with etching stop layer surface。
Optionally, the material of described storage medium layer is one or more in non-crystalline silicon, polysilicon, titanium oxide or aluminium oxide。
Optionally, also include: be positioned at the alumina layer on described second graphene layer surface。
Compared with prior art, technical scheme has the advantage that
In the technical scheme of the forming method of semiconductor structure provided by the invention, at the etching stop layer that etching provides, after forming the groove exposing bottom metal layer surface, adopt autoregistration growth technique, form the electric connection layer filling full groove, and electric connection layer electrically connects with bottom metal layer。Present invention, avoiding the grinding technics formed in electric connection layer technical process, thus avoiding the harmful effect that grinding technics brings, it is prevented that reliability and the electric property of semiconductor structure are brought harmful effect by grinding technics。
Meanwhile, define some the first discrete graphene layers, be positioned at the storage medium layer on the first graphene layer surface and be positioned at second graphene layer on storage medium layer surface, and the first graphene layer is positioned at electric connection layer surface and partial etching stop-layer surface。In the present invention, bottom metal layer, electric connection layer and the first graphene layer are collectively as the bottom electrode of resistor type random access memory, owing to electric current transfer rate in the first graphene layer is very fast, therefore the harmful effect of electric current transfer rate almost can be ignored by electric connection layer；Second graphene layer is as the upper electrode of resistor type random access memory；Therefore, the present invention Simplified flowsheet step, avoid that extra grinding technics brings dysgenic while, improve the conversion rate of semiconductor structure and erasable speed, optimize the electric property of semiconductor structure。
Further, the material of described electric connection layer is cobalt tungsten phosphorus, cobalt tungsten boron, cobalt tungsten phosphorus boron, cobalt molybdenum phosphorus, cobalt molybdenum boron, cobalt molybdenum chromium or cobalt molybdenum chromium boron, when adopting autoregistration growth technique, the electric connection layer that quality is of a relatively high can be formed, so that the resistance of electric connection layer reduces, optimize the electric property of semiconductor structure further。
The present invention also provides for the semiconductor structure that a kind of structural behaviour is superior, including: substrate and the etching stop layer being positioned at substrate surface, has some discrete bottom metal layers in described substrate；It is positioned at described etching stop layer and exposes the groove on bottom metal layer surface；Filling the electric connection layer of full described groove, described electric connection layer electrically connects with bottom metal layer；It is positioned at the first some discrete graphene layer on described electric connection layer surface and partial etching stop-layer surface；It is positioned at the storage medium layer on described first graphene layer surface；It is positioned at second graphene layer on described storage medium layer surface。Bottom metal layer, electric connection layer and the first graphene layer are collectively as the bottom electrode of resistor type random access memory, second graphene layer is the upper electrode of resistor type random access memory, owing to electric current transfer rate in the first graphene layer and the second graphene layer is very fast so that semiconductor structure has high conversion rate and high erasable speed。
Accompanying drawing explanation
Fig. 1 to Fig. 9 forms the cross-sectional view of process for the semiconductor structure that one embodiment of the invention provides。
Detailed description of the invention
By background technology it can be seen that the electric property of semiconductor structure that prior art is formed has much room for improvement。
Common, the formation process of the semiconductor structure containing resistor type random access memory comprises the following steps: step S1, offer substrate, has some discrete bottom metal layers in described substrate；Step S2, formed and be covered in the etching stop layer of described substrate surface；Step S3, etch described etching stop layer, form the groove exposing bottom metal layer surface；The conductive barrier film expiring described groove is filled in step S4, formation, and described conductive barrier film is also covered in etching stop layer surface；The conductive barrier film higher than etching stop layer surface is removed in step S5, grinding, forms the electrically conductive barrier filling completely groove；Step S6, the upper electrode film sequentially forming the storage medium film being covered in etching stop layer surface and electrically conductive barrier surface, being covered in storage medium film surface；Step S7, etching described upper electrode film and storage medium film, form some discrete storage medium layer and be positioned at the upper electrode layer on storage medium layer surface, wherein, described storage medium layer is positioned at electrically conductive barrier surface and partial etching stop-layer surface。
In said method, bottom metal layer and electrically conductive barrier are collectively as the lower electrode layer of resistor type random access memory, and the material of electrically conductive barrier is generally TiN or TaN。But, substrate and bottom metal layer can be caused certain damage by the grinding technics formed in electrically conductive barrier technical process, and introduce unnecessary impurity, cause the reliability of semiconductor structure and electric property low。
For this, the present invention provides the forming method of a kind of semiconductor structure, adopts self-registered technology to form the electric connection layer filling full groove, Simplified flowsheet step, it is to avoid the harmful effect that extra grinding technics brings；And, adopt the first graphene layer as part bottom electrode, second graphene layer is as upper electrode, electric current transfer rate in the first graphene layer and the second graphene layer is very fast, the defect big to make up the resistance of electric connection layer that self-registered technology formed, improves the electric property of semiconductor structure further。
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail。
Fig. 1 to Fig. 9 forms the cross-sectional view of process for the semiconductor structure that one embodiment of the invention provides。
Refer to Fig. 1, it is provided that substrate 100 and be covered in the etching stop layer 102 on substrate 100 surface, there is in described substrate 100 some discrete bottom metal layers 101。
The material of described substrate 100 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium；Described substrate 100 can also be the silicon substrate on insulator。Semiconductor device can also be formed with in described substrate 100, for instance, PMOS transistor, nmos pass transistor, CMOS transistor, resistor, capacitor or inducer etc.。
In the present embodiment, the material of described substrate 100 is silicon。
In the present embodiment, described bottom metal layer 101 top flushes with substrate 100 surface。As a specific embodiment, the processing step forming bottom metal layer 101 includes: provide initial substrate；Patterned mask layer is formed at described initial substrate surface；With described patterned mask layer for mask, in described initial substrate, form Damascus opening, form the substrate 100 with Damascus opening；Forming the underlying metal film filling full described Damascus opening, described underlying metal film is also covered in substrate 100 surface；Grinding and remove the underlying metal film being positioned at substrate 100 surface, form the bottom metal layer 101 filling full Damascus opening, described bottom metal layer 101 top flushes with substrate 100 surface。
Described Damascus opening is single Damascus opening or dual damascene openings。In other embodiments, bottom metal layer top can also lower than substrate surface, follow-up etching be positioned at substrate surface etching stop layer formed groove time, in addition it is also necessary to etching remove segment thickness substrate so that the top of bottom metal layer is exposed。
The material of described bottom metal layer 101 is copper, aluminum or tungsten。The material of bottom metal layer 101 described in the present embodiment is copper。
In the present embodiment, in the process forming described bottom metal layer 101, conductive metal layer 121 can also be formed in substrate 100, described conductive metal layer 121 concurrently forms with bottom metal layer 101 and material is identical, follow-up is formed over the first graphene layer, storage medium layer and the second graphene layer without conductive metal layer 121 again。Described etching stop layer 102 is also covered in conductive metal layer 121 surface。
The silicon nitride that material is carbon dope (NDC) of described etching stop layer 102, silicon nitride or carborundum；In the present embodiment, the material of etching stop layer 102 is the silicon nitride of carbon dope。
On the one hand, etching stop layer 102 is avoided that conductive metal layer 121 is caused unnecessary etching by subsequent etching processes；The opposing party, described etching stop layer 102 provides Process ba-sis for being subsequently formed electric connection layer, form the electric connection layer electrically connected with bottom metal layer 101, make bottom metal layer 101 by electric connection layer to electrically connect with the first graphene layer being subsequently formed, so that bottom metal layer 101 and the first graphene layer are collectively as the lower electrode layer of resistor type random access memory。
Refer to Fig. 2, etch described etching stop layer 102, form the groove 103 exposing bottom metal layer 101 surface。
As a specific embodiment, the processing step forming described groove 103 includes: form patterned photoresist layer forming etching stop layer 102 surface；With described patterned photoresist layer for mask, adopting dry etch process to etch described etching stop layer 102, until exposing bottom metal layer 101 top surface, forming the groove 103 exposing bottom metal layer 101 surface。
In the present embodiment, the bottom size of described groove 103 is less than the top dimension of bottom metal layer 101, so that the small volume of the electric connection layer being subsequently formed, thus reducing the resistance of semiconductor structure, reduces RC late effect。If the bottom size of groove is excessive, the volume of the electric connection layer being so subsequently formed accordingly is also by relatively larger, and owing to the resistivity of electric connection layer material is relatively big, can cause that the resistance of electric connection layer is bigger, in turn result in semiconductor structure and there is bigger resistance, be unfavorable for reducing RC late effect。
In other embodiments, the bottom size of groove can also more than or equal to the top dimension of bottom metal layer。In other embodiments, if bottom metal layer top is lower than substrate surface, then after etching stop layer is performed etching, in addition it is also necessary to etching removes the substrate of segment thickness, form groove, make bottom metal layer surface be exposed。
Refer to Fig. 3, adopt autoregistration growth technique, form the electric connection layer 104 filling full described groove 103 (with reference to Fig. 2), described electric connection layer 104 electrically connects with bottom metal layer 101。
Acting as of described electric connection layer 104: electrically connected with the first graphene layer being subsequently formed by bottom metal layer 101, makes bottom metal layer 101 and the first graphene layer can collectively as bottom electrode。
The material of electric connection layer 104 described in the present embodiment is cobalt tungsten phosphorus, cobalt tungsten boron, cobalt tungsten phosphorus boron, cobalt molybdenum phosphorus, cobalt molybdenum boron, cobalt molybdenum chromium or cobalt molybdenum chromium boron；Electric connection layer 104 top flushes with etching stop layer 102 surface。Although the resistivity of electric connection layer 104 material is of a relatively high, electric connection layer 104 still is able to play the effect electrically connected by bottom metal layer 101 with the first graphene layer being subsequently formed。
Further, owing to the first graphene layer has the performance of extraordinary conduction and heat conduction, the resistivity of the first graphene layer is extremely low, and electric current transmits very fast in the first graphene layer；Even if therefore the resistivity of electric connection layer 104 material is relatively big, the electric property of semiconductor structure is affected also very little by described electric connection layer 104。
The present embodiment adopts autoregistration growth technique simultaneously, form the electric connection layer filling full described groove 103, it is to avoid the harmful effect that grinding technics can bring, improve reliability and the electric property of semiconductor structure。
Galvanoplastic are adopted to carry out described autoregistration growth technique。Concrete, carrying out from bottom to top in groove 103 grows described electric connection layer 104, and when electric connection layer 104 top flushes with etching stop layer 102 surface, namely the growth technique of electric connection layer 104 stops。
As a specific embodiment, the material of described bottom metal layer 101 is copper, when the material of electric connection layer 104 is cobalt tungsten phosphorus, the material produced in electroplating process only can deposit on bottom metal layer 101 surface, electric connection layer 104 will not be deposited on etching stop layer 102 surface, thus the electric connection layer 104 forming the full groove 103 of filling from bottom to top；The electroplating solution of galvanoplastic includes the aqueous solution of cobaltous sulfate, sodium citrate, boric acid, sodium hypohosphate and ammonium tungstate, and the pH value of electroplating solution is 8.5 to 9.2, for instance being 8.75,8.95,9.15 etc., electroplating solution temperature is 60 degrees Celsius to 85 degrees Celsius。
Wherein, the concentration of cobaltous sulfate is 5.5g/L to 6.5g/L, for instance 6g/L；The concentration of sodium citrate is 20g/L to 30g/L, for instance 25g/L；The concentration of boric acid is 25g/L to 35g/L, for instance 30g/L；The concentration of sodium hypohosphate is 6g/L to 10g/L, for instance 8g/L；The concentration of ammonium tungstate is 1g/L to 5g/L, for instance 2.5g/L。Surfactant can also be passed in electroplating solution。
In prior art, it is typically first formed the electrical connection film filling full groove, and the electrical connection film formed also is covered in etching stop layer surface；Then adopt grinding technics, for instance chemical mechanical milling tech, grind and remove the electrical connection film higher than etching stop layer surface, form the electric connection layer filling full groove。But, grinding technics can introduce harmful effect, for instance, grinding technics introduces unnecessary impurity, substrate causes the interface between damage, bottom metal layer and substrate space etc. occur, causes that the electric property of semiconductor structure is low。
Refer to Fig. 4, form the first graphene film 105 being covered in described electric connection layer 104 surface and etching stop layer 102 surface。
Described first graphene film 105 provides Process ba-sis as being subsequently formed the first graphene layer, after subsequent etching removes the first graphene film 105 being positioned at partial etching stop-layer 102 surface, formed and be covered in electric connection layer 104 and first graphene layer on partial etching stop-layer 102 surface。
Mechanical stripping method, graphene oxide chemical reduction method, epitaxial growth method or chemical vapour deposition technique is adopted to form described first graphene film 105。
Wherein, chemical vapour deposition technique can be Low Pressure Chemical Vapor Deposition, plasma chemical vapor deposition or laser induced chemical vapor depostion method。
As in a specific embodiment, the thickness of described first graphene film 105 is 50 angstroms to 500 angstroms。
Refer to Fig. 5, form the storage medium film 106 being covered in described first graphene film 105 surface。
Described storage medium film 106 provides Process ba-sis for being subsequently formed storage medium layer, after subsequent etching storage medium film 106, forms the storage medium layer being covered in the first graphene layer surface。
Storage medium layer plays the effect of the insulating medium layer between the first graphene layer and the second graphene layer being subsequently formed。The material of described storage medium film 106 is the material with electricity induction resistive characteristic, and described electricity induction refers to that the resistance of material can change under specific external signal, and will not recover because of removing of the signal of telecommunication after material change in resistance。And, described storage medium film 106 has binary resistive characteristic, namely the resistance of storage medium film 106 material is reversible, and the signal of telecommunication applying a kind of form can make the resistance of material diminish, and applies the another form of signal of telecommunication and resistance change can be made again to return to greatly high resistant。
The material of described storage medium film 106 is one or more in non-crystalline silicon, polysilicon, aluminium oxide, titanium oxide, copper oxide, niobium pentaoxide or zirconium oxide。
The material of storage medium film described in the present embodiment 106 is non-crystalline silicon (a-Si, AmorphousSilicon), and the thickness of storage medium film 106 is 50 angstroms to 1000 angstroms；Chemical vapor deposition method is adopted to form described storage medium film 106。
Refer to Fig. 6, form the second graphene film 107 being covered in described storage medium film 106 surface。
Described second graphene film 107 provides Process ba-sis for being subsequently formed the second graphene layer, after subsequent etching removes part the second graphene film 107, forming some the second discrete graphene layers, described second graphene layer is as the upper electrode of resistor type random access memory in semiconductor structure。
It is referred to the forming method of aforementioned first graphene film about the forming method of the second graphene film 107, does not repeat them here。As in a specific embodiment, the thickness of described second graphene layer 107 is 50 angstroms to 500 angstroms。
After forming described second graphene film 107; the pellumina 108 being covered in the second graphene film 107 surface can also be formed; described pellumina 108 plays the effect of protection the second graphene film 107, it is prevented that the second graphene film 107 is polluted or damages by external environment。
As a specific embodiment, metal organic chemical vapor deposition technique is adopted to form described pellumina 108。
Refer to Fig. 7, form the mask layer 109 with opening 110 on described second graphene film 107 surface。
Described mask layer 109 is positioned at the top of electric connection layer 104 and the top of partial etching stop-layer 102, follow-up with the described mask layer 109 with opening 110 for mask, etching oxidation aluminum film the 108, second graphene film 107, storage medium film 106 and the first graphene film 105。
The material of described mask layer 109 is silicon oxide, silicon nitride, titanium nitride or tantalum nitride。Described mask layer 109 is single layer structure or laminated construction。
With described mask layer 109 for single layer structure exemplarily, the material of described mask layer 109 is silicon oxide to the present embodiment。
As a specific embodiment, the processing step of the mask layer 109 described in formation with opening 110 includes: form the original mask layer being covered in pellumina 108 surface；Patterned photoresist layer is formed on described original mask layer surface；With described patterned photoresist layer for mask, etch described original mask layer, form the mask layer 109 with opening 110。
In other embodiments, mask layer can be photoresist layer, it is also possible to include bottom antireflective coating or reflection coating provided。
Refer to Fig. 8, with described mask layer 109 for mask, it is sequentially etched the second graphene film 107 (with reference to Fig. 7) along opening 110 (with reference to Fig. 7), storage medium film 106 (with reference to Fig. 7) and the first graphene film 105 (with reference to Fig. 7), until exposing etching stop layer 102 surface, form some the first discrete graphene layers 115, it is positioned at the storage medium layer 116 on the first graphene layer 115 surface, and it is positioned at second graphene layer 117 on storage medium layer 116 surface, described first graphene layer 115 is positioned at electric connection layer 104 surface and partial etching stop-layer 102 surface。
In the present embodiment, adopt dry etch process, be sequentially etched the second graphene film 107, storage medium film 106 and the first graphene film 105。
Described first graphene layer 115 electrically connects with electric connection layer 104, and bottom metal layer 101 electrically connects with electric connection layer 104, therefore the first graphene layer 115 is made to electrically connect with bottom metal layer 101 by described electric connection layer 104, first graphene layer 115, electric connection layer 104 and bottom metal layer 101 can collectively as the bottom electrodes of resistor type random access memory, and the second graphene layer 117 is as the upper electrode of resistor type random access memory。
Owing to the first graphene layer 115 in bottom electrode has excellent electric property, electric current transfer rate in the first graphene layer 115 very fast, therefore the impact of the resistance of electric connection layer 104 is almost negligible so that the advantage that semiconductor structure still has high conversion rate, high erasable speed。Simultaneously, owing to the present embodiment adopting autoregistration growth technique form described electric connection layer 104, avoid introducing extra grinding technics, such as chemically mechanical polishing grinding technics, thus preventing unnecessary impurity and the damage that described extra grinding technics introduces, substrate 100 and bottom metal layer 101 is made to keep excellent performance, thus improving reliability and the electric property of semiconductor structure further。
In the present embodiment, before etching the second graphene film 107, further comprise the steps of: etching and be positioned at the pellumina 108 on the second graphene film 107 surface, form alumina layer 118。Described alumina layer 118 is positioned at the second graphene layer 117 surface, plays the effect of protection the second graphene layer 117, it is to avoid the second graphene layer 117 contacts with external environment。
Accordingly, the material of the first graphene layer 115 is Graphene, and the thickness of the first graphene layer 115 is 50 angstroms to 500 angstroms；The material of the second graphene layer 117 is Graphene, and the thickness of the second graphene layer 117 is 50 angstroms to 500 angstroms。
Refer to Fig. 9, remove described mask layer 109 (with reference to Fig. 8)。
Wet-etching technology etching is adopted to remove described mask layer 109。In the present embodiment, the material of described mask layer 109 is silicon nitride, and the etch liquids of wet-etching technology is phosphoric acid solution, and wherein, solution temperature is 80 degrees Celsius to 160 degrees Celsius, and in solution, the mass percent of phosphoric acid is 65% to 85%。
Accordingly, the present invention also provides for a kind of semiconductor structure, refer to Fig. 9, and described semiconductor structure includes:
Substrate 100 and be positioned at the etching stop layer 102 on substrate 100 surface, has some discrete bottom metal layers 101 in described substrate 100；
It is positioned at described etching stop layer 102 and exposes the groove on bottom metal layer 101 surface；
Filling the electric connection layer 104 of full described groove, described electric connection layer 104 electrically connects with bottom metal layer 101；
It is positioned at the first some discrete graphene layer 115 on described electric connection layer 104 surface and partial etching stop-layer 102 surface；
It is positioned at the storage medium layer 116 on described first graphene layer 115 surface；
It is positioned at second graphene layer 117 on described storage medium layer 116 surface。
In the present embodiment, the material of described substrate 100 is silicon。
The material of described bottom metal layer 101 is copper, aluminum or tungsten, and described bottom metal layer 101 top flushes with substrate 100 surface。
In other embodiments, when bottom metal layer top is lower than substrate surface, then groove is except being positioned at etching stop layer, is also located in segment thickness substrate, to ensure that bottom portion of groove exposes bottom metal layer top surface, so that electric connection layer electrically connects with bottom metal layer。
The material of described etching stop layer 102 is the silicon nitride of carbon dope, silicon nitride or carborundum；Described bottom portion of groove exposes bottom metal layer top surface；The material of described electric connection layer 104 is cobalt tungsten phosphorus, cobalt tungsten boron, cobalt tungsten phosphorus boron, cobalt molybdenum phosphorus, cobalt molybdenum boron, cobalt molybdenum chromium or cobalt molybdenum chromium boron；Described electric connection layer 104 top flushes with etching stop layer 102 surface。
The material of bottom metal layer 101 described in the present embodiment is copper, and the material of electric connection layer 104 is cobalt tungsten phosphorus。
The material of described first graphene layer 115 is Graphene；The material of described second graphene layer 117 is Graphene。
The material of described storage medium layer 116 is the material with electricity induction resistive characteristic, and the resistance of material changes under specific external signal, and will not recover because of removing of the signal of telecommunication after material change in resistance；And described storage medium layer 116 has binary resistive characteristic, namely the resistance of storage medium layer 116 material is reversible, and the signal of telecommunication applying a kind of form can make the resistance of material diminish, and applies the another form of signal of telecommunication and resistance change can be made again to return to greatly high resistant。The material of described storage medium layer 116 is one or more in non-crystalline silicon, polysilicon, titanium oxide or aluminium oxide。The material of storage medium layer 116 described in the present embodiment is non-crystalline silicon。
Making bottom metal layer 101 electrically connect with the first graphene layer 115 by electric connection layer 104, bottom metal layer 101, electric connection layer 104 and the first graphene layer 115 are collectively as the bottom electrode of resistor type random access memory；Second graphene layer 117 is as the upper electrode of resistor type random access memory。
Owing to the first graphene layer 115 has the electric property of excellence, electric current transfer rate in the first graphene layer 115 is very fast, even if therefore the resistivity of electric connection layer 104 material is relatively big, electric current transfer rate in bottom electrode will be relatively larger；And electric current also has very fast transfer rate in upper electrode so that resistor type random access memory has high transformation efficiency, high erasable speed so that semiconductor structure has excellent electric property。
In the present embodiment, semiconductor structure also includes: be positioned at the alumina layer 118 on the second graphene layer 117 surface。Described alumina layer 118 plays the effect of protection the second graphene layer 117, it is prevented that the second graphene layer 117 is exposed in external environment and sustains damage。
Although present disclosure is as above, but the present invention is not limited to this。Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range。
Claims (19)
1. the forming method of a semiconductor structure, it is characterised in that including:
Substrate is provided and is covered in the etching stop layer of substrate surface, there is in described substrate some discrete bottom metal layers；
Etch described etching stop layer, form the groove exposing bottom metal layer surface；
Adopting autoregistration growth technique, form the electric connection layer filling full described groove, described electric connection layer electrically connects with bottom metal layer；
Form some the first discrete graphene layers, be positioned at the storage medium layer on the first graphene layer surface and be positioned at second graphene layer on storage medium layer surface, and the first graphene layer is positioned at electric connection layer surface and partial etching stop-layer surface。
2. the forming method of semiconductor structure according to claim 1, it is characterised in that the material of described electric connection layer is cobalt tungsten phosphorus, cobalt tungsten boron, cobalt tungsten phosphorus boron, cobalt molybdenum phosphorus, cobalt molybdenum boron, cobalt molybdenum chromium or cobalt molybdenum chromium boron。
3. the forming method of semiconductor structure according to claim 2, it is characterised in that adopt galvanoplastic to carry out described autoregistration growth technique。
4. the forming method of semiconductor structure according to claim 3, it is characterized in that, the material of described bottom metal layer is copper, when the material of electric connection layer is cobalt tungsten phosphorus, the electroplating solution of described galvanoplastic includes cobaltous sulfate, sodium citrate, boric acid, sodium hypohosphate and ammonium tungstate, the pH value of electroplating solution is 8.5 to 9.2, and electroplating solution temperature is 60 degrees Celsius to 85 degrees Celsius。
5. the forming method of semiconductor structure according to claim 1, it is characterised in that the top of described electric connection layer flushes with etching stop layer surface。
6. the forming method of semiconductor structure according to claim 1, it is characterised in that described bottom metal layer top flushes with substrate surface。
7. the forming method of semiconductor structure according to claim 1, it is characterised in that described bottom metal layer top is lower than substrate surface；After etching described etching stop layer, also etching removes the substrate of segment thickness, forms described groove。
8. the forming method of semiconductor structure according to claim 1, it is characterised in that the material of described storage medium layer is one or more in non-crystalline silicon, polysilicon, titanium oxide or aluminium oxide。
9. the forming method of semiconductor structure according to claim 1, it is characterised in that the material of described etching stop layer is silicon nitride, carborundum or carbon dope silicon nitride。
10. the forming method of semiconductor structure according to claim 1, it is characterised in that the thickness of described first graphene layer is 50 angstroms to 500 angstroms；The thickness of the second graphene layer is 50 angstroms to 500 angstroms。
11. the forming method of semiconductor structure according to claim 1, it is characterised in that the material of described bottom metal layer is copper, aluminum or tungsten。
12. the forming method of semiconductor structure according to claim 1, it is characterized in that, the processing step forming described first graphene layer, storage medium layer and the second graphene layer includes: the storage medium film that sequentially form the first graphene film being covered in described electric connection layer surface and etching stop layer surface, is covered in described first graphene membrane surface, the second graphene film being covered in described storage medium film surface；The mask layer with opening is formed in described second graphene membrane surface；With described mask layer for mask, being sequentially etched the second graphene film, storage medium film and the first graphene film along opening, until exposing partial etching stop-layer surface, forming described first graphene layer, storage medium layer and the second graphene layer；Remove described mask layer。
13. the forming method of semiconductor structure according to claim 12, it is characterized in that, before there is described in being formed after described second graphene film, being formed the mask layer of opening, further comprise the steps of: and form the pellumina being covered in described second graphene membrane surface。
14. the forming method of semiconductor structure according to claim 12, it is characterised in that the material of described mask layer is one or more in silicon oxide, silicon nitride, titanium nitride or tantalum nitride。
15. a semiconductor structure, it is characterised in that including: substrate and be positioned at the etching stop layer of substrate surface, there is in described substrate some discrete bottom metal layers；
It is positioned at described etching stop layer and exposes the groove on bottom metal layer surface；
Filling the electric connection layer of full described groove, described electric connection layer electrically connects with bottom metal layer；
It is positioned at the first some discrete graphene layer on described electric connection layer surface and partial etching stop-layer surface；
It is positioned at the storage medium layer on described first graphene layer surface；
It is positioned at second graphene layer on described storage medium layer surface。
16. semiconductor structure according to claim 15, it is characterised in that the material of described electric connection layer is cobalt tungsten phosphorus, cobalt tungsten boron, cobalt tungsten phosphorus boron, cobalt molybdenum phosphorus, cobalt molybdenum boron, cobalt molybdenum chromium or cobalt molybdenum chromium boron。
17. semiconductor structure according to claim 15, it is characterised in that described electric connection layer top flushes with etching stop layer surface。
18. semiconductor structure according to claim 15, it is characterised in that the material of described storage medium layer is one or more in non-crystalline silicon, polysilicon, titanium oxide or aluminium oxide。
19. semiconductor structure according to claim 15, it is characterised in that also include: be positioned at the alumina layer on described second graphene layer surface。
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