CN105702280B - A kind of circuit and method reducing quiescent dissipation under DRAM energy-saving modes - Google Patents
A kind of circuit and method reducing quiescent dissipation under DRAM energy-saving modes Download PDFInfo
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- CN105702280B CN105702280B CN201610028544.8A CN201610028544A CN105702280B CN 105702280 B CN105702280 B CN 105702280B CN 201610028544 A CN201610028544 A CN 201610028544A CN 105702280 B CN105702280 B CN 105702280B
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 230000006837 decompression Effects 0.000 claims description 4
- 230000011664 signaling Effects 0.000 claims description 2
- 230000003068 static effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
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Abstract
The present invention discloses a kind of circuit and method reducing quiescent dissipation under DRAM energy-saving modes, and circuit includes internal DRAM supply voltage generator and mode control circuit；The internal DRAM supply voltage generator is used to generate the voltage of DRAM work；The mode control circuit is used for：When dram chip works normally, the operating voltage that internal DRAM supply voltage generator generates is transmitted directly to internal DRAM supply voltage network；When dram chip is in energy-saving mode, internal DRAM supply voltage network is sent to after the operating voltage that internal DRAM supply voltage generator generates is depressured.The present invention is in traditional DRAM products in the design basis of internal supply voltage module, and additional one mode of adding controls gating circuit so that dram chip in a normal operation mode, still uses scheduled internal supply voltage；And in a power saving mode, the internal supply voltage reduced using one, to achieve the purpose that reduce the quiescent dissipation under DRAM energy-saving modes.
Description
【Technical field】
It is the present invention relates to dynamic random access memory technical field, more particularly to quiet under a kind of reduction DRAM energy-saving modes
The circuit and method of state power consumption.
【Background technology】
With the fast development of portable electronic device, the demand of DRAM products is quickly increased, simultaneously for
Especially more stringent requirements are proposed for power consumption performance for the performance of DRAM products.
Under normal conditions, DRAM enters after energy-saving mode, and most power consumption module has been switched off, and institute is with the power-saving mode
Under the power consumption overwhelming majority come from the static leakage currents of all devices in dram chip.And the static leakage current of device and inside
The characterisitic parameter strong correlation of supply voltage and device itself.At present in order to reduce the leakage current of device in technique, pass through increasing more
The threshold voltage of device is added to realize.This results in a negative effect, and being exactly the timing performance of device reduces, whole to reduce
The timing performance parameter of a DRAM products causes core timing performance parameter such as tAA in back end test to exceed SPEC (memory readings
Time constant tAA is taken to have exceeded defined standard) range.
【Invention content】
The purpose of the present invention is to provide the circuits and method of quiescent dissipation under a kind of reduction DRAM energy-saving modes, to solve
Above-mentioned technical problem.The present invention in the design basis of internal supply voltage module, additionally adds one in traditional DRAM products
Kind scheme control gating function so that dram chip in a normal operation mode, still uses scheduled internal supply voltage；And
In a power saving mode, the internal supply voltage reduced using one, to reach the static work(reduced under DRAM energy-saving modes
The purpose of consumption.
To achieve the goals above, the present invention adopts the following technical scheme that：
A kind of circuit reducing quiescent dissipation under DRAM energy-saving modes, including internal DRAM supply voltage generator and pattern
Control circuit；
The internal DRAM supply voltage generator is used to generate the voltage of DRAM work；
The mode control circuit is used for：When dram chip works normally, internal DRAM supply voltage generator is produced
Raw operating voltage is transmitted directly to internal DRAM supply voltage network；It, will be in DRAM when dram chip is in energy-saving mode
Internal DRAM supply voltage network is sent to after the operating voltage decompression that portion's supply voltage generator generates.
Further, the mode control circuit includes switch S1, switch S2, PMOS tube and whole control circuit；
The output end of internal DRAM supply voltage generator is divided into two-way, is powered all the way by switch S1 connection internal DRAM
Voltage network, another way connect internal DRAM supply voltage network with PMOS tube by concatenated switch S2；
Whole control circuit, which is used to generate energy-saving mode when dram chip is in energy-saving mode, controls Signal-controlled switch
S1 is disconnected, switch S2 is closed；And non-energy-saving mode control signaling switch S1 is generated when dram chip is in non-energy-saving mode
It is closed, switch S2 is disconnected.
Further, when dram chip is in energy-saving mode, the voltage that internal DRAM supply voltage generator generates passes through
Internal DRAM supply voltage network is sent to after one PMOS tube decompression.
Further, when dram chip is in energy-saving mode, the operating voltage of internal DRAM supply voltage generator generation
Internal DRAM supply voltage network is sent to after being depressured the threshold voltage of a PMOS tube.
Further, the threshold voltage of PMOS tube is 300~400mv.
A method of reducing quiescent dissipation under DRAM energy-saving modes, when dram chip works normally, by internal DRAM
The operating voltage that supply voltage generator generates is transmitted directly to internal DRAM supply voltage network；It is in economize on electricity in dram chip
When pattern, internal DRAM supply voltage net is sent to after the operating voltage that internal DRAM supply voltage generator generates is depressured
Network.
Further, it is depressured by the operating voltage that a PMOS tube generates internal DRAM supply voltage generator.
Further, when dram chip is in energy-saving mode, the work that internal DRAM supply voltage generator generates is electric
Internal DRAM supply voltage network is sent to after the threshold voltage of pressure drop one PMOS tube of pressure.
Further, the threshold voltage of PMOS tube is 300~400mv.
Compared with the existing technology, the invention has the advantages that：The present invention is internal in traditional DRAM products to be supplied
In the design basis of piezoelectric voltage module, additional one mode of adding controls gating circuit so that dram chip is in normal operating mould
Under formula, scheduled internal supply voltage is still used；And in a power saving mode, the internal supply voltage reduced using one,
To achieve the purpose that reduce the quiescent dissipation under DRAM energy-saving modes.
【Description of the drawings】
Fig. 1 is a kind of structural schematic diagram reducing the circuit of quiescent dissipation under DRAM energy-saving modes of the present invention.
【Specific implementation mode】
Refering to Figure 1, a kind of circuit reducing quiescent dissipation under DRAM energy-saving modes of the present invention, including it is traditional
Internal DRAM supply voltage generator (left sides Fig. 1 box inside points) and mode control circuit (on the right of Fig. 1).Mode control circuit
Including switch S1, switch S2, PMOS tube PMOS2 and whole control circuit.The output end of internal DRAM supply voltage generator
It is divided into two-way, all the way by switch S1 connection internal DRAM supply voltage networks, another way passes through concatenated switch S2 and PMOS
Pipe connects internal DRAM supply voltage network.The input of whole control circuit be external command signal, according to input external command,
Judge whether dram chip is in energy-saving mode, and the corresponding generation energy-saving mode control letter when dram chip is in energy-saving mode
Number and generate non-energy-saving mode control signal in non-energy-saving mode.Static work(under a kind of reduction DRAM energy-saving modes of the present invention
The method of consumption, when energy-saving mode control signal is high, switch S2 conductings, internal supply voltage vint_int passes through one
PMOS2 is managed, and voltage is sent to internal supply voltage Vint after reducing a threshold voltage (300~400mv), gives internal DRAM institute
Some logic module power supplies.In such a mode, since voltage value reduces 300~400mv, all logic modules it is quiet
State power consumption greatly reduces, and thus reduces the quiescent dissipation under DRAM energy-saving modes.When non-energy-saving mode control signal is high,
Switch S1 conductings, the voltage of internal voltage generator output are fed directly to internal supply voltage network, the various behaviour of dram chip
It is normally carried out.
Under 45nm techniques, for size is 1um/60nm NMOS tubes, if supply voltage is down to from 1.2V
After 0.8v, simulation result sees that leakage current is reduced to 100pA from 200pA；And so on, if in a power saving mode will be internal
Supply voltage is reduced to 0.8v from 1.2v, then the quiescent dissipation under energy-saving mode will greatly reduce.
Claims (6)
1. a kind of circuit reducing quiescent dissipation under DRAM energy-saving modes, which is characterized in that produced including internal DRAM supply voltage
Raw device and mode control circuit；
The internal DRAM supply voltage generator is used to generate the voltage of DRAM work；
The mode control circuit is used for：When dram chip works normally, internal DRAM supply voltage generator is generated
Operating voltage is transmitted directly to internal DRAM supply voltage network；When dram chip is in energy-saving mode, internal DRAM is supplied
Internal DRAM supply voltage network is sent to after the operating voltage decompression that piezoelectric voltage generator generates；
The mode control circuit includes switch S1, switch S2, PMOS tube and whole control circuit；
The output end of internal DRAM supply voltage generator is divided into two-way, passes through switch S1 connection internal DRAM supply voltages all the way
Network, another way connect internal DRAM supply voltage network with PMOS tube by concatenated switch S2；
It is disconnected that whole control circuit is used to generate energy-saving mode control Signal-controlled switch S1 when dram chip is in energy-saving mode
It opens, switch S2 is closed；And non-energy-saving mode control signaling switch S1 is generated when dram chip is in non-energy-saving mode and is closed
It closes, switch S2 is disconnected；
When dram chip is in energy-saving mode, the voltage that internal DRAM supply voltage generator generates is depressured by a PMOS tube
After send internal DRAM supply voltage network to；
When dram chip is in energy-saving mode, the operating voltage that internal DRAM supply voltage generator generates is depressured a PMOS tube
Threshold voltage after send internal DRAM supply voltage network to.
2. a kind of circuit reducing quiescent dissipation under DRAM energy-saving modes according to claim 1, which is characterized in that PMOS
The threshold voltage of pipe is 300~400mv.
3. a kind of method reducing quiescent dissipation under DRAM energy-saving modes, which is characterized in that be based on one kind described in claim 1
The circuit for reducing quiescent dissipation under DRAM energy-saving modes generates internal DRAM supply voltage when dram chip works normally
The operating voltage that device generates is transmitted directly to internal DRAM supply voltage network；It, will when dram chip is in energy-saving mode
Internal DRAM supply voltage network is sent to after the operating voltage decompression that internal DRAM supply voltage generator generates.
4. a kind of method reducing quiescent dissipation under DRAM energy-saving modes according to claim 3, which is characterized in that pass through
The operating voltage that one PMOS tube generates internal DRAM supply voltage generator is depressured.
5. a kind of method reducing quiescent dissipation under DRAM energy-saving modes according to claim 4, which is characterized in that
When dram chip is in energy-saving mode, the operating voltage that internal DRAM supply voltage generator generates is depressured the threshold of a PMOS tube
Send internal DRAM supply voltage network after threshold voltage to.
6. a kind of method reducing quiescent dissipation under DRAM energy-saving modes according to claim 5, which is characterized in that PMOS
The threshold voltage of pipe is 300~400mv.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610028544.8A CN105702280B (en) | 2016-01-15 | 2016-01-15 | A kind of circuit and method reducing quiescent dissipation under DRAM energy-saving modes |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610028544.8A CN105702280B (en) | 2016-01-15 | 2016-01-15 | A kind of circuit and method reducing quiescent dissipation under DRAM energy-saving modes |
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| Publication Number | Publication Date |
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| CN105702280A CN105702280A (en) | 2016-06-22 |
| CN105702280B true CN105702280B (en) | 2018-08-21 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101387843A (en) * | 2007-09-14 | 2009-03-18 | 株式会社理光 | Power control system |
| CN103000221A (en) * | 2011-09-09 | 2013-03-27 | 华邦电子股份有限公司 | Semiconductor device |
| CN205384876U (en) * | 2016-01-15 | 2016-07-13 | 西安紫光国芯半导体有限公司 | Reduce circuit of quiescent power dissipation under DRAM energy -saving mode |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5041631B2 (en) * | 2001-06-15 | 2012-10-03 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device |
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- 2016-01-15 CN CN201610028544.8A patent/CN105702280B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101387843A (en) * | 2007-09-14 | 2009-03-18 | 株式会社理光 | Power control system |
| CN103000221A (en) * | 2011-09-09 | 2013-03-27 | 华邦电子股份有限公司 | Semiconductor device |
| CN205384876U (en) * | 2016-01-15 | 2016-07-13 | 西安紫光国芯半导体有限公司 | Reduce circuit of quiescent power dissipation under DRAM energy -saving mode |
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| CN105702280A (en) | 2016-06-22 |
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