CN105681815B - The method for improving block-eliminating effect filtering Restructuring Module data rate memory - Google Patents
The method for improving block-eliminating effect filtering Restructuring Module data rate memory Download PDFInfo
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Abstract
The present invention relates to the methods for improving block-eliminating effect filtering Restructuring Module data rate memory.In order to ensure external DDR2 memory can be reliably written in the mass data of H.264 HD video coding block-eliminating effect filtering module at high speed, it is different from traditional two-dimensional address mapping storage mode, the present invention proposes a kind of linear address mapping method based on macro block.The write operation requests that response coding core issues；It will be in the write-in caching of data continuously linear；Calculate the external memory base address to be accessed；Splice data, calculate rank addresses；It is write data into chip external memory when the chip external memory free time, thus the storage speed demand of DBF data needed for meeting high definition real-time coding.
Description
Technical field
The invention belongs to IC design technology, it is related to improving block-eliminating effect filtering Restructuring Module data rate memory
Method.
Background technique
Since the reconstruct write operation data volume for the DBF module that H.264 HD video encodes is huge, and write operation is to be based on
(each macro block has 16 row, 2 column data) of macro block, thus when DDR2SDRAM is written according to two-dimensional address often write a macro block will be into
16 row operations of row, this greatly reduces the speed of write operation and efficiency.In order not to change firmware (firmware) to external memory
Address space allocation improves the reconstruct data write efficiency of block-eliminating effect filtering module, realizes high definition real-time coding, proposes to improve
The method of block-eliminating effect filtering module (abbreviation DBF module) reconstruct data rate memory.
Summary of the invention
The object of the present invention is to provide a kind of methods for improving block-eliminating effect filtering Restructuring Module data rate memory, not
In the case that the connection type and firmware address space for changing chip external memory are distributed, DBF Restructuring Module can be effectively improved
The high speed write service speed and efficiency of data.
The technical solution of the invention is as follows:
The method for improving block-eliminating effect filtering Restructuring Module data rate memory, comprising the following steps:
1) caching is written into the block-eliminating effect filtering data continuously linear for encoding the frame image that core issues；
2) block-eliminating effect filtering data are spliced into the format of chip external memory needs:
2.1) splicing block-eliminating effect filtering data are read from caching；
2.2) vacancy of 4 row brightness, 2 row colorations is reserved after the write-in of the data of first macro-block line；
2.3) judge whether next macro-block line is 20 rows, if so, being transferred to step 2.4；If not, by the macro-block line
Data will be divided into the data of 6 row coloration of 4 row brightness, 2 row coloration and 12 row brightness, then by the data of 4 row brightness, 2 row coloration
Last macro-block line is written to correspond at the reserved location of macro block, the corresponding macro block position of this macro-block line is written into 12 row brightness, 6 row coloration
It sets, while reserved empty position is written for next macro-block line；Repeat step 2.3；
2.4) reserved location that 4 rows correspond to macro block for filling last macro-block line is first write to the brightness data of the macro-block line,
4 row data of remaining 12 row and request next time are merged into the corresponding position of the last one macro-block line again；
3) the frame image is calculated in the initial address of chip external memory；
4) address of cache of chip external memory is carried out:
4.1) in chip external memory, signal is judged according to top bottom to distinguish top field, bottom, then by the frame image
Brightness data is placed on according to one-dimensional mode Coutinuous store, top field data therein by the luminance frame the initial address of the frame image
The top half in space, bottom field data are placed under the luminance frame space of the corresponding address of half height in the frame space
Half part；
4.2) in chip external memory, signal is judged according to top bottom to distinguish top field, bottom, then by the frame image
Chroma data is placed on according to one-dimensional mode Coutinuous store, top field data therein across the initial address of the frame brightness space
The top half in chrominance frames space, bottom field data are placed on the chrominance frames that the corresponding address of half height in chrominance frames space is risen
The lower half portion in space；The height in the luminance frame space is two times of chrominance frames space；
4.3) new_addr is mapped external storage in blocks to the address of cache new_addr of chip external memory by calculation code core
The physical address that device is identified, then by the reconstruct data of DBF module according to " top field brightness-bottom field brightness-top coloration-bottom
The sequence of field coloration " is successively continuously written into chip external memory；
Address of cache new_addr such as following formula of the calculation code core to chip external memory:
mc_width_mbs×mb_rows_cnt÷32+wxloc÷2×32+(new_yloc×2–mb_rows_cnt×
32)；
Mc_width_mbs: the picture traverse as unit of macro block；
Mb_rows_cnt: macro-block line counts；
Wxloc: the abscissa of each macro block as unit of pixel；
New_yloc: the ordinate of each macro block as unit of pixel.
Above-mentioned steps 1 will encode the tool of the block-eliminating effect filtering data continuously linear write-in caching for the frame image that core issues
Body step are as follows:
Each macro block is sequentially written in from left to right as in macro-block line, then writes the data of next macro-block line, until most
Until all data of the latter macro-block line are all run through from coding core.
Above-mentioned steps 3 calculate the frame image in the specific steps of the initial address of chip external memory are as follows:
When new request arrives, DBF module distinguishes reconstruct data and down-sampled data, for reconstructing data, DBF module
The two-dimensional coordinate of the current frame address provided according to firmware and this operation, calculates the module and is mapped to chip external memory input terminal
Initial address.
Beneficial effects of the present invention:
The present invention can reliably at high speed in order to ensure the mass data that H.264 HD video encodes block-eliminating effect filtering module
External DDR2 memory is written, in the case where the connection type and firmware address space for not changing chip external memory are distributed, mentions
It is a kind of out to be different from traditional two-dimensional address mapping storage mode, i.e. the linear address mapping method based on macro block.This method is first
Then the first write operation requests that response coding core issues calculate the outside to be accessed in the write-in caching of data continuously linear
Base memory address；Splice data again, calculate rank addresses；Chip external memory is just write data into when the chip external memory free time
In.Therefore, the present invention can effectively improve the high speed write service speed and efficiency of DBF Restructuring Module data, to meet height
The storage speed demand of DBF data needed for clear real-time coding
Detailed description of the invention
Fig. 1 is module system architecture diagram used in the present invention；
Fig. 2 is data connecting method of the present invention；
Fig. 3 is the storage mode in chip external memory of the present invention；
Fig. 4 is control module state machine of the present invention；
Fig. 5 is that the data flow of DBF write operation of the present invention moves towards figure；
Fig. 6 is flow diagram of the invention.
Specific embodiment
The present invention improves the method for block-eliminating effect filtering Restructuring Module data rate memory (below block-eliminating effect filtering module
Abbreviation DBF module), referring to Fig. 6, have follow steps:
Step 1, the data continuously linear that core issues will be encoded and caching is written；
Step 2, block-eliminating effect filtering data are read to from caching and are spliced into the format of chip external memory needs: for
The macro-block line number of data lines of one frame image beginning and end is not 16 (brightness), 8 (colorations), therefore the data of first macro-block line
The vacancy of 4 row brightness, 2 row colorations should be reserved after each macro block is written；
Data for line number for 16 macro-block line will be divided into two parts (4 row brightness, 2 row coloration, 12 row brightness, 6 row color
Degree) data, and last macro-block line is written into the data of 4 row brightness, 2 row coloration and is corresponded at the reserved location of macro block, it then will be remaining
12 row brightness, 6 row coloration the corresponding macro block position of this macro-block line is written, while still reserved empty position is for subsequent macro block row write
Enter；
When being written to the last one macro-block line, for brightness data: each macro block operates in three times, first writes 4 rows for filling out
It fills the reserved location that a macro-block line corresponds to macro block with, then 4 row data of remaining 12 row and request next time is merged into last
The corresponding position of a macro-block line；
Step 3, a frame image is calculated in the initial address of chip external memory；
Step 4, address of cache of the block-eliminating effect filtering data in chip external memory: in chip external memory, image is pressed
Stored according to one-dimensional mode, brightness data according to a frame image initial address Coutinuous store.Top field data is placed on a frame space
Top half (initial address), bottom field data are placed on lower half portion (the corresponding address of half height of a frame)；
The write operation of coloration is identical as brightness design method, and only the initial address of coloration needs the sky across a frame brightness
Between.The write operation processing mode of field mode is similar with frame pattern, only needs to judge signal according to top bottom to distinguish top field, bottom
?.The reconstruct data of DBF module are successively continuously according to the suitable of " top field brightness-bottom field brightness-top coloration-bottom coloration "
Sequence is written in chip external memory；
It is as follows from the address of cache of coding core to chip external memory:
new_addr:mc_width_mbs*mb_rows_cnt*32+wxloc/2*32+(new_yloc*2–mb_rows_
cnt*32)；
Mc_width_mbs: the picture traverse as unit of macro block；
Mb_rows_cnt: macro-block line counts；
Wxloc: the abscissa of each macro block as unit of pixel；
New_yloc: the ordinate of each macro block as unit of pixel；
New_addr is mapped to the physical address (time-sharing multiplex two-dimensional address) that chip external memory is identified.
In above-mentioned steps 1, the initial address of each macro block is not considered respectively, and the data in each macro block are linear in order
Write-in (that is, each macro block is sequentially written in from left to right as in macro-block line, then writes the data of next macro-block line, until most
The data of the latter macro-block line write complete)；Data can be regarded as one-dimensional Coutinuous store by this write operation, and when write operation only needs
Latch the initial address of each brightness and chrominance macroblock.Each macro block has 16 rows 2 to arrange a data, and each write operation is all
Be that first line by line, end of being expert at goes to next wardrobe again, until all 32 data being written into all from encode run through in core for
Only.
In above-mentioned steps 3,
Distinguish data type: the address calculation of DBF module is used in differentiation reconstruct data and down-sampled data, when
When DBF new write operation requests arrive, data type is judged according to type signal, when piece external memory is written in the data once requested
In reservoir, the state machine of address calculation module will be transferred to IDLE state, wait request next time；
Step 3 calculates initial address: the address calculation of DBF module is used to generate rising for block-eliminating effect filtering write operation
Beginning address, the module can be according to the two-dimensional coordinate of the space the DBF initial address that firmware (firmware) is provided and this operation, meters
Calculate the initial address that the module is mapped to chip external memory input terminal.
Module system architecture diagram of the invention is as shown in Figure 1.
1, the handshake operation of block-eliminating effect filtering module:
It encodes core and issues write operation requests signal, the data of write request module judgement write-in are reconstruct or down-sampling number
According to, while judging whether DBF Write post module becomes full, it is then responding to request signal, and issue grant signal；Next week
Phase issues strobe signal again, in the data that the coding core of the same period that strobe signal issues is written to rear end DBF module.
The write operation of data is realized according to interaction is shaken hands as req-grant-strobe.By each macro block by macro-block line
It is sequentially written in from left to right, then writes the data of next macro-block line, until the data of the last one macro-block line write complete.
Each macro block has 16 rows 2 column, and write operation is all to carry out line by line every time, and end of being expert at goes to next wardrobe again, until
Until 32 all data are all read from caching.
2, the write operation initial address of block-eliminating effect filtering reconstruct data calculates:
When the write operation requests for encoding core issue, data type is judged according to type signal.DBF address calculation module
Distinguish reconstruct data and down-sampled data.When data type is reconstruct data, DBF address module can be provided according to firmware
The two-dimensional coordinate { x, y } of the space DBF initial address and this operation, calculates the starting that DBF module is mapped to chip external memory
Address.
3, the data connecting method of DBF module:
As shown in Figure 2.The number of data lines of first macro-block line is 12, is spliced into the macro block of 16 rows, is in a macro block
Continuation address storage, then each initial address all should be 32 alignment of data.Therefore 4 rows are reserved after each macro block write-in
Brightness, 2 row colorations vacancy.
The data of second macro-block line will be divided into two parts (4 row brightness, 2 row coloration, 12 row brightness, 6 row coloration) data, so
The reserved of each macro block in last macro-block line is written into 4 row brightness (8 continuous datas) or 2 row colorations (4 continuous datas) afterwards
At position.The write operation initial address of 4 row brightness, 2 row coloration is the corresponding initial address of a upper macro-block line before each macro block.
12 row brightness remaining for second macro-block line or 6 row colorations, then be written the corresponding initial address of this macro-block line
Position, while still leave a blank in advance 4 row brightness or 2 row colorations are so that subsequent macro-block line uses.And so on, for except first and
Macro-block line other than the last one is all made of this method splicing data.
When being written to the last one macro-block line, by taking brightness as an example: each macro block operates in three times, first writes 4 rows for filling
Last macro-block line corresponds to the reserved location of macro block, then 4 row data of remaining 12 row and request next time are merged into the last one
The corresponding position of macro-block line.
4, DBF reconstructs address of cache mode of the data in chip external memory:
It is as shown in Figure 3 that DBF reconstructs address of cache mode of the data in chip external memory.
In chip external memory, image is stored according to one-dimensional mode, and brightness data connects according to the initial address of a frame image
Renew storage.Top field data is placed on the top half (initial address) in a frame space, and bottom field data is placed on lower half portion (the two of a frame
The corresponding address of/mono- height).
The write operation of coloration is identical as brightness design method, and only the initial address of coloration needs the sky across a frame brightness
Between.The write operation processing mode of field mode is similar with frame pattern, only needs to judge signal according to top bottom to distinguish top field, bottom
?.The reconstruct data of DBF module are successively continuously according to the suitable of " top field brightness-bottom field brightness-top coloration-bottom coloration "
Sequence is written in chip external memory.
It is as follows from the address of cache of coding core to chip external memory:
new_addr:mc_width_mbs*mb_rows_cnt*32+wxloc/2*32+(new_yloc*2–mb_rows_
cnt*32)
New_addr is finally mapped to the time-sharing multiplex two-dimensional address that chip external memory is identified.
5, state machine control and data flow:
Fig. 4 is control module state machine of the present invention；
State machine enters DBF_IDLE state after system reset；When FIFO cached a DBF reconstruct write request data,
Then buffer_ready！=0 simultaneously state machine jump to DBF_REQ, show DBF module can to DDR2 issue write request；
If buffer_ready！=0 condition is unsatisfactory for, then state machine is maintained at DBF_IDLE state；
In DBF_REQ state, as wr_ddr2_gnt==1 ' b1, into DBF_RDDATA state, this time slice external memory
Reservoir all set, can start to write DBF reconstruct data；If wr_ddr2_gnt==1 ' b1 is unsatisfactory for, illustrate there are other moulds
Block occupies chip external memory, needs to wait for, and keeps the state for requesting to write DDR2；
In DBF_RDDTA state, as wr_ddr2_end==1 ' b1, into DBF_IDLE state, rear end is patrolled at this time
It collects DBF module and has been completed write operation of the data into DDR2, and go to DBF_IDLE state, response encodes core next time
Write operation requests；If wr_ddr2_end==1 ' b1 is unsatisfactory for, illustrates that data do not write complete into DDR2 also, remain at
In DBF_RDDATA state.
DBF write operation module simply can be divided into several sub-operations according to data flow trend, specifically as shown in Figure 5.
Claims (3)
1. the method for improving block-eliminating effect filtering Restructuring Module data rate memory, it is characterised in that: the following steps are included:
1) caching is written into the block-eliminating effect filtering data continuously linear for encoding the frame image that core issues；
2) block-eliminating effect filtering data are spliced into the format of chip external memory needs:
2.1) splicing block-eliminating effect filtering data are read from caching；
2.2) vacancy of 4 row brightness, 2 row colorations is reserved after the write-in of the data of first macro-block line；
2.3) judge whether next macro-block line is 20 rows, if so, being transferred to step 2.4；If not, by the data of the macro-block line
It is divided into the data of 6 row coloration of 4 row brightness, 2 row coloration and 12 row brightness, then the data of 4 row brightness, 2 row coloration is written
Last macro-block line corresponds at the reserved location of macro block, the corresponding macro block position of this macro-block line is written in 12 row brightness, 6 row coloration, together
When reserved empty position be written for next macro-block line；Repeat step 2.3；
2.4) reserved location that 4 rows correspond to macro block for filling last macro-block line is first write to the brightness data of the macro-block line, then will
Remaining 12 row and 4 row data of request next time are merged into the corresponding position of the last one macro-block line；
3) the frame image is calculated in the initial address of chip external memory；
4) address of cache of chip external memory is carried out:
4.1) in chip external memory, signal is judged according to top bottom to distinguish top field, bottom, then by the brightness of the frame image
Data are placed on according to one-dimensional mode Coutinuous store, top field data therein by the luminance frame space the initial address of the frame image
Top half, the lower half in the luminance frame space that the corresponding address of half height that bottom field data is placed on the frame space is risen
Point；
4.2) in chip external memory, signal is judged according to top bottom to distinguish top field, bottom, then by the coloration of the frame image
Data are placed on the coloration risen across the initial address of the frame brightness space according to one-dimensional mode Coutinuous store, top field data therein
The top half in frame space, bottom field data are placed on the chrominance frames space that the corresponding address of half height in chrominance frames space is risen
Lower half portion；The height in the luminance frame space is two times of chrominance frames space；
4.3) new_addr is mapped to chip external memory institute to the address of cache new_addr of chip external memory by calculation code core
The physical address of identification, then by the reconstruct data of DBF module according to " top field brightness-bottom field brightness-top coloration-bottom color
The sequence of degree " is successively continuously written into chip external memory；
Address of cache new_addr such as following formula of the calculation code core to chip external memory:
mc_width_mbs×mb_rows_cnt÷32+wxloc÷2×32+(new_yloc×2–mb_rows_cnt×32)；
Mc_width_mbs: the picture traverse as unit of macro block；
Mb_rows_cnt: macro-block line counts；
Wxloc: the abscissa of each macro block as unit of pixel；
New_yloc: the ordinate of each macro block as unit of pixel.
2. the method according to claim 1 for improving block-eliminating effect filtering Restructuring Module data rate memory, feature exist
In:
The step 1 will encode the specific step of the block-eliminating effect filtering data continuously linear write-in caching for the frame image that core issues
Suddenly are as follows:
Each macro block is sequentially written in from left to right as in macro-block line, then writes the data of next macro-block line, until last
Until all data of a macro-block line are all run through from coding core.
3. the method according to claim 1 or 2 for improving block-eliminating effect filtering Restructuring Module data rate memory, feature
It is:
The step 3 calculates the specific steps of the initial address of the frame image in chip external memory are as follows:
When new request arrives, DBF module distinguishes reconstruct data and down-sampled data, for reconstructing data, DBF module according to
The two-dimensional coordinate of current frame address and this operation that firmware provides calculates the module and is mapped to rising for chip external memory input terminal
Beginning address.
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| CN108614667B (en) * | 2016-12-12 | 2021-03-26 | 中国航空工业集团公司西安航空计算技术研究所 | Configurable broadcast ELS data frame power-on automatic loading circuit and method |
| CN108024033B (en) * | 2017-11-24 | 2020-06-09 | 中国航空工业集团公司西安航空计算技术研究所 | Video image sending circuit based on ARINC818 protocol |
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