CN105681807B - It is a kind of to divide pixel motion vector computational methods and device based on H264 agreements - Google Patents
It is a kind of to divide pixel motion vector computational methods and device based on H264 agreements Download PDFInfo
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- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
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Abstract
Dividing pixel motion vector computational methods and device based on H264 agreements the invention discloses a kind of, divide pixel motion vector of the described device for computing macro block, described device include buffer unit, main control unit, reference frame multiplexing maintenance unit, SAD cost calculating units, SAD cost selection units.Calculating during dividing pixel motion vector of H264 agreements, acquired size of the original block pixel based on 16x16 blocks obtained the method, ensure that the durability of the original block pixel of 8x8 blocks and 4x4 blocks；When obtaining reference block pixel, it is multiplexed maintenance unit according to reference frame and records the correspondence between whole pixel motion vector, selectively obtain the reference block pixel of the different sub-block of whole pixel motion vector, and the identical reference block pixel of whole pixel motion vector is then not repeated to obtain, to substantially increase the reusability of reference pixel, and the computational efficiency of point pixel motion vector is improved, power consumption is saved, while also ing save hardware cost.
Description
Technical field
The present invention relates to computer chip field more particularly to a kind of pixel motion vector is divided to calculate based on H264 agreements
Method and apparatus.
Background technology
With the fast development of computer technology, the communication technology, Internet technology and multimedia technology, multimedia application is
Through going deep into the every aspect of people's daily life, and gradually change people's lives mode.Video is in multimedia application
The most commonly seen and maximum media of information content.Currently, multimedia service is based on audio from being developed into based on video, no matter
It is that the conventional Multi Medias such as film, TV, video monitoring application or net streaming media video, videophone and video conference etc. are new
Emerging multimedia application, video are all the wherein component parts of core the most.
There are many kinds of the agreements of Video coding, and H264 agreements are exactly one wherein important.And in video coding process, lead to
It crosses and obtains whole pixel motion vector to calculate point pixel motion vector again be an important ring for Video coding step.Divide due to calculating
Pixel motion vector needs to obtain original block pixel and reference block pixel, and the pixel of reference block is to be based on whole pixel motion
Vector is obtained.Existing method often uses the method obtained one by one in the pixel for obtaining reference block, i.e., each original
Block pixel is required for being gone to obtain reference block pixel in corresponding buffer unit according to whole pixel motion vector, leads to reference block pixel
The problems such as reusability is low when acquisition, complex steps, power consumption is big, hardware area is big, of high cost.
Invention content
For this reason, it may be necessary to a kind of technical solution for dividing pixel motion vector to calculate based on H264 agreements be provided, to solve
When dividing pixel motion vector of video pixel block is being calculated, since acquisition reference block pixel step is cumbersome, reusability is low, is causing to regard
The problems such as frequency coding power consumption is big, hardware area is big, of high cost.
To achieve the above object, inventor provide it is a kind of dividing pixel motion vector computing device based on H264 agreements,
Described device divides pixel motion vector, the macro block to be divided into multiple 16x16 sub-blocks for computing macro block；Every 16x16
Sub-block is divided into 4 8x8 sub-blocks, and every 8x8 sub-blocks are divided into 4 4x4 sub-blocks；Described device includes buffer unit, master
Control unit, reference frame multiplexing maintenance unit, SAD cost calculating units, SAD cost selection units；The buffer unit and master control
Unit connects, and the main control unit is connect with reference frame multiplexing maintenance unit, the reference frame multiplexing maintenance unit and SAD costs
Computing unit connects, and the SAD cost calculating units are connect with SAD cost selection units, the SAD costs selection unit and master
Control unit connection；The buffer unit includes the first cache module, the second cache module, third cache module；The master control list
Member includes acquiring unit and register cell；The acquiring unit is obtained including the first acquisition module, the second acquisition module and third
Modulus block；The register cell includes the first register cell and the second register cell；
Whole pixel motion arrow of first acquisition module for obtaining 16x16 sub-blocks from first cache module
Amount, the whole pixel motion vector include the first whole pixel motion vector, the second whole pixel motion vector and the whole pixel fortune of third
Dynamic vector, the whole pixel motion vector that the first whole pixel motion vector is 16x16 layers in 16x16 sub-blocks, described second is whole
The whole pixel motion vector that pixel motion vector is 8x8 layers in 16x16 sub-blocks, the whole pixel motion vector of third are 16x16
4x4 layers of whole pixel motion vector in sub-block；
The reference frame multiplexing maintenance unit is used to record the correspondence between whole pixel motion vector, the whole pixel
The correspondence of motion vector include the correspondence of the first whole pixel motion vector and the second whole pixel motion vector, 8x8 layers
The whole pixel motion of third of the correspondence of second whole pixel motion vector of different 8x8 sub-blocks and 4x4 layers of difference 4x4 sub-blocks
The correspondence of vector；
Second acquisition module is used to obtain the corresponding original block picture of 16x16 sub-blocks from second cache module
Element, first register cell is for caching the corresponding original block pixel of 16x16 sub-blocks；
The third acquisition module is used for according to the correspondence between whole pixel motion vector, and mould is cached from the third
Reference block pixel is obtained in block, second register cell is for caching reference block pixel；
The SAD cost calculating units are used to obtain original block pixel from first register cell, and from institute
It states the second register cell and obtains reference block pixel, and carry out SAD cost calculating, obtain the reference block pixel of multiple and different positions
SAD costs；
The SAD costs selection unit chooses SAD for the reference block pixel SAD costs of different location to be compared
The SAD cost values of the reference block pixel of Least-cost, and calculate the reference block pixel and original block pixel divides pixel motion to swear
Amount；
What the main control unit was used to receive the transmission of SAD cost selection units divides pixel motion vector, and a point pixel is transported
Dynamic vector is written in the first cache module.
It is further, described that " third acquisition module is used for according to the correspondence between whole pixel motion vector, from described
Reference block pixel is obtained in third cache module " include：If the second whole pixel motion vector of 8x8 layers of 8x8 sub-blocks and first
Whole pixel motion vector is identical, then the third acquisition module obtains reference block pixel not from third cache module, and otherwise
Three acquisition modules obtain reference block pixel from third cache module.
It is further, described that " third acquisition module is used for according to the correspondence between whole pixel motion vector, from described
Reference block pixel is obtained in third cache module " include：If reference frame is multiplexed the 8x8 sub-blocks of the 8x8 layers of maintenance unit record
Second whole pixel motion vector is identical as the second whole pixel motion vector of upper a 8x8 layers of 8x8 sub-blocks, then the third obtains
Module obtains reference block pixel not from third cache module, and otherwise third acquisition module obtains reference from third cache module
Block pixel.
It is further, described that " third acquisition module is used for according to the correspondence between whole pixel motion vector, from described
Reference block pixel is obtained in third cache module " include：If reference frame is multiplexed the 4x4 sub-blocks of the 4x4 layers of maintenance unit record
Third pixel motion vector is identical as upper a 4x4 layers of the third pixel motion vector of 4x4 sub-blocks, then the third acquisition module
Reference block pixel is obtained not from third cache module, otherwise third acquisition module obtains reference block picture from third cache module
Element.
Further, described " main control unit will be for that will divide pixel motion vector to be written in the first cache module " includes：It is main
Control unit after dividing pixel motion vector and this that the corresponding whole pixel motion vector of pixel motion vector is divided to be packaged for writing
Enter in the first cache module.
Inventor additionally provides a kind of divides pixel motion vector computational methods, the method to be applied to based on H264 agreements
Pixel motion vector computing device, described device is divided to divide pixel motion vector, institute for computing macro block based on H264 agreements
It states macro block and is divided into multiple 16x16 sub-blocks；Every 16x16 sub-blocks are divided into 4 8x8 sub-blocks, and every 8x8 sub-blocks are divided
For 4 4x4 sub-blocks；Described device includes buffer unit, main control unit, reference frame multiplexing maintenance unit, SAD costs calculating list
Member, SAD cost selection units；The buffer unit is connect with main control unit, and the main control unit is safeguarded single with reference frame multiplexing
Member connection, the reference frame multiplexing maintenance unit are connect with SAD cost calculating units, the SAD cost calculating units and SAD generations
Valence selection unit connects, and the SAD costs selection unit is connect with main control unit；The buffer unit includes the first caching mould
Block, the second cache module, third cache module；The main control unit includes acquiring unit and register cell；The acquisition is single
Member includes the first acquisition module, the second acquisition module and third acquisition module；The register cell includes the first register list
Member and the second register cell；Described method includes following steps：
First acquisition module obtains the whole pixel motion vector of 16x16 sub-blocks from first cache module, described whole
Pixel motion vector includes the first whole pixel motion vector, the second whole pixel motion vector and the whole pixel motion vector of third, institute
State the whole pixel motion vector that the first whole pixel motion vector is 16x16 layers in 16x16 sub-blocks, the second whole pixel motion arrow
The whole pixel motion vector that amount is 8x8 layers in 16x16 sub-blocks, the whole pixel motion vector of third are 4x4 layers in 16x16 sub-blocks
Whole pixel motion vector；
Reference frame multiplexing maintenance unit records the correspondence between whole pixel motion vector, the whole pixel motion vector
Correspondence include the correspondence of the first whole pixel motion vector and the second whole pixel motion vector, 8x8 layers of difference 8x8
Pair of the correspondence of second whole pixel motion vector of block and the whole pixel motion vector of third of 4x4 layers of difference 4x4 sub-blocks
It should be related to；
Second acquisition module obtains the corresponding original block pixel of 16x16 sub-blocks from second cache module, and described
One register cell caches the corresponding original block pixel of 16x16 sub-blocks；
Third acquisition module is obtained according to the correspondence between whole pixel motion vector from the third cache module
Reference block pixel, second register cell cache reference block pixel；
SAD cost calculating units obtain original block pixel from first register cell, and are posted from described second
Storage unit obtains reference block pixel, and carries out SAD cost calculating, obtains the reference block pixel SAD costs of multiple and different positions；
The reference block pixel SAD costs of different location are compared by SAD costs selection unit, choose SAD Least-costs
Reference block pixel SAD cost values, and calculate the reference block pixel and original block pixel divides pixel motion vector；
What main control unit reception SAD cost selection units were sent divides pixel motion vector, and pixel motion vector will be divided to write
Enter in the first cache module.
Further, the step is " third acquisition module according to the correspondence between whole pixel motion vector, from described
Reference block pixel is obtained in third cache module " include：
If the second whole pixel motion vector of 8x8 layers of 8x8 sub-blocks is identical as the first whole pixel motion vector, described
Three acquisition modules obtain reference block pixel not from third cache module, and otherwise third acquisition module is obtained from third cache module
Take reference block pixel.
Further, the step is " third acquisition module according to the correspondence between whole pixel motion vector, from described
Reference block pixel is obtained in third cache module " include：
If reference frame is multiplexed the second whole pixel motion vector of the 8x8 sub-blocks of the 8x8 layers of maintenance unit record and a upper 8x8
Second whole pixel motion vector of the 8x8 sub-blocks of layer is identical, then the third acquisition module is not obtained from third cache module
Reference block pixel, otherwise third acquisition module reference block pixel is obtained from third cache module.
Further, the step is " third acquisition module according to the correspondence between whole pixel motion vector, from described
Reference block pixel is obtained in third cache module " include：
If the third pixel motion vector of the 4x4 sub-blocks of the 4x4 layers of reference frame multiplexing maintenance unit record and upper a 4x4 layers
4x4 sub-blocks third pixel motion vector it is identical, then the third acquisition module obtains reference not from third cache module
Block pixel, otherwise third acquisition module reference block pixel is obtained from third cache module.
Further, the step " main control unit will divide pixel motion vector to be written in the first cache module " includes：
Main control unit will divide pixel motion vector to divide the corresponding whole pixel motion vector of pixel motion vector to be beaten with this
It is written after packet in the first cache module.
Divide pixel motion vector computational methods and device, the method based on H264 agreements described in above-mentioned technical proposal
Applied to described device, described device divides pixel motion vector for computing macro block, and described method includes following steps：First
First acquisition module obtains the whole pixel motion vector of 16x16 sub-blocks from first cache module,；Then reference frame is multiplexed
Maintenance unit records the correspondence between whole pixel motion vector；Then the second acquisition module is used for from the second caching mould
The corresponding original block pixel of 16x16 sub-blocks is obtained in block；Then third acquisition module is according to pair between whole pixel motion vector
It should be related to, reference block pixel be obtained from the third cache module, second register cell is for caching reference block picture
Element；
SAD cost calculating units are used to obtain original block pixel from first register cell, and from described the
Two register cells obtain reference block pixel, and carry out SAD cost calculating, obtain the reference block pixel SAD of multiple and different positions
Cost；
The reference block pixel SAD costs of different location are compared by SAD costs selection unit, choose SAD Least-costs
Reference block pixel SAD cost values, and calculate the reference block pixel and original block pixel divides pixel motion vector；
What main control unit reception SAD cost selection units were sent divides pixel motion vector, and pixel motion vector will be divided to write
Enter in the first cache module.
Divide pixel motion vector computational methods and device, the method application based on H264 agreements described in said program
In dividing pixel motion vector computing device based on H264 agreements, described device divides pixel motion vector for computing macro block,
Described device includes buffer unit, main control unit, reference frame multiplexing maintenance unit, SAD cost calculating units, the selection of SAD costs
Unit.Described method includes following steps：First acquisition module first obtains 16x16 sub-blocks from first cache module
Whole pixel motion vector；Then reference frame multiplexing maintenance unit records the correspondence between whole pixel motion vector；Then
Two acquisition modules obtain the corresponding original block pixel of 16x16 sub-blocks from second cache module, third acquisition module according to
Correspondence between whole pixel motion vector obtains reference block pixel from the third cache module；Then SAD costs meter
It calculates unit and obtains original block pixel from first register cell, and reference block is obtained from second register cell
Pixel, and SAD cost calculating is carried out, obtain the reference block pixel SAD costs of multiple and different positions；Then SAD costs are chosen single
The reference block pixel SAD costs of different location are compared by member, choose the SAD costs of the reference block pixel of SAD Least-costs
Value, and calculate the reference block pixel and original block pixel divides pixel motion vector；Then main control unit receives SAD costs and chooses
What unit was sent divides pixel motion vector, and pixel motion vector will be divided to be written in the first cache module.In this way, calculating H264
Agreement is divided during pixel motion vector, and acquired size of the original block pixel based on 16x16 blocks is obtained, and ensure that
The durability of the original block pixel of 8x8 blocks and 4x4 blocks；When obtaining reference block pixel, maintenance unit note is multiplexed according to reference frame
The correspondence between whole pixel motion vector is recorded, (16x16 layers, 8x8 layers of each layer there is no multiplexed situation is selectively obtained
And 4x4 layers) reference block pixel obtained, and the reference block pixel that can be multiplexed then is not repeated to obtain, to
The reusability of reference pixel is substantially increased, and improves the computational efficiency of point pixel motion vector, saves power consumption, simultaneously also
Hardware cost is saved.
Description of the drawings
Fig. 1 is the signal for dividing pixel motion vector computing device based on H264 agreements that an embodiment of the present invention is related to
Figure；
Fig. 2 is the flow for dividing pixel motion vector computational methods based on H264 agreements that an embodiment of the present invention is related to
Figure.
Specific implementation mode
For the technology contents of technical solution, construction feature, the objects and the effects are described in detail, below in conjunction with specific reality
It applies example and attached drawing is coordinated to be explained in detail.
Referring to Fig. 1, dividing pixel motion vector to calculate dress based on H264 agreements for what an embodiment of the present invention was related to
The schematic diagram set.Divide pixel motion vector of the described device for computing macro block, the macro block are divided into multiple 16x16
Block；Every 16x16 sub-blocks are divided into 4 8x8 sub-blocks, and every 8x8 sub-blocks are divided into 4 4x4 sub-blocks；Described device includes
Buffer unit, main control unit 109, reference frame multiplexing maintenance unit 106, SAD cost calculating units 107, SAD cost selection units
108；The buffer unit is connect with main control unit, and the main control unit is connect with reference frame multiplexing maintenance unit, the reference
Frame multiplexing maintenance unit is connect with SAD cost calculating units, and the SAD cost calculating units are connect with SAD cost selection units,
The SAD costs selection unit is connect with main control unit；The buffer unit includes that the first cache module 101, second caches mould
Block 102, third cache module 105；The main control unit 109 includes acquiring unit 103 and register cell 104；The acquisition
Unit 103 includes the first acquisition module 113, the second acquisition module 123 and third acquisition module 133；The register cell 104
Including the first register cell 114 and the second register cell 124；
Whole pixel motion of first acquisition module 113 for obtaining 16x16 sub-blocks from first cache module
Vector, the whole pixel motion vector include the first whole pixel motion vector, the second whole pixel motion vector and the whole pixel of third
Motion vector, the whole pixel motion vector that the first whole pixel motion vector is 16x16 layers in 16x16 sub-blocks, described second
The whole pixel motion vector that whole pixel motion vector is 8x8 layers in 16x16 sub-blocks, the whole pixel motion vector of third are
4x4 layers of whole pixel motion vector in 16x16 sub-blocks；
The reference frame multiplexing maintenance unit 106 is used to record the correspondence between whole pixel motion vector, described whole
The correspondence of pixel motion vector include the first whole pixel motion vector and the second whole pixel motion vector correspondence,
The whole picture of third of the correspondence of second whole pixel motion vector of 8x8 layers of difference 8x8 sub-blocks and 4x4 layers of difference 4x4 sub-blocks
The correspondence of plain motion vector；
Second acquisition module 123 is used to obtain the corresponding original block of 16x16 sub-blocks from second cache module
Pixel, first register cell is for caching the corresponding original block pixel of 16x16 sub-blocks；
The third acquisition module 133 is used for according to the correspondence between whole pixel motion vector, slow from the third
Reference block pixel is obtained in storing module, second register cell is for caching reference block pixel；
The SAD cost calculating units 107 are used to obtain original block pixel, Yi Jicong from first register cell
Second register cell obtains reference block pixel, and carries out SAD cost calculating, obtains the reference block picture of multiple and different positions
Plain SAD costs；
The SAD costs selection unit 108 is chosen for the reference block pixel SAD costs of different location to be compared
The SAD cost values of the reference block pixel of SAD Least-costs, and calculate the reference block pixel and original block pixel divides pixel motion
Vector；
What the main control unit 109 was used to receive the transmission of SAD cost selection units divides pixel motion vector, and will divide pixel
Motion vector is written in the first cache module.
Using based on H264 agreements when dividing pixel motion vector computing device, the first acquisition module 113 first is from institute
State the whole pixel motion vector that 16x16 sub-blocks are obtained in the first cache module.First cache module is with storage data
The electronic component of function, such as can be ROM memory.For each 16x16 sub-block, it can be divided into
" three layers " structure, i.e. 16x16 layers, 8x8 layers and 4x4 layers.For 16x16 layers, i.e., divided as unit of 16x16
Words, 16x16 sub-blocks can be divided into 1 16x16 block, thus each 16x16 sub-block is corresponding with 1 16x16 layers of whole picture
Plain motion vector, i.e., the first whole pixel motion vector.For 8x8 layers, i.e., if being divided as unit of 8x8,16x16
Sub-block can be divided into 4 8x8 blocks, thus each 16x16 sub-block is corresponding with 4 8x8 layers of whole pixel motion vector, i.e.,
Second whole pixel motion vector.For 4x4 layers, i.e., if being divided as unit of 4x4,16x16 sub-blocks can be drawn
It is divided into 16 4x4 blocks, thus each 16x16 sub-block is corresponding with 16 4x4 layers of whole pixel motion vector, the i.e. whole pixel of third
Motion vector.To sum up, when dividing pixel motion vector of each 16x16 sub-block is being calculated, the first acquisition module is needed from described
1 16x16 layers, 4 8x8 layers and 16 4x4 layers are obtained in first cache module amounts to 21 whole pixel motion vectors.
The reference frame multiplexing maintenance unit 106 is used to record the correspondence between whole pixel motion vector, described whole
The correspondence of pixel motion vector include the first whole pixel motion vector and the second whole pixel motion vector correspondence,
The whole picture of third of the correspondence of second whole pixel motion vector of 8x8 layers of difference 8x8 sub-blocks and 4x4 layers of difference 4x4 sub-blocks
The correspondence of plain motion vector.In the present embodiment, 16x16 layers when dividing pixel motion vector is being calculated, be also based on
What the block of 8x8 sizes was calculated for unit, thus the correspondence of the first whole pixel motion vector and the second whole pixel motion vector
Relationship specifically includes：Record same position 8x8 sub-blocks the first whole pixel motion vector and the second whole pixel motion vector be
It is no identical.
Include 4 16x16 layers of 8x8 sub-blocks such as 16x16 layers, is 8x8 sub-blocks 1,8x8 sub-blocks respectively
2,8x8 sub-blocks 3 and 8x8 sub-blocks 4.Include 4 8x8 layers of 8x8 sub-blocks for 8x8 layers, is 8x8 sub-blocks a, 8x8 respectively
Sub-block b, 8x8 sub-block c and 8x8 sub-block d.8x8 sub-blocks a is corresponding with the position of 8x8 sub-blocks 1,8x8 sub-blocks b and 8x8 sub-blocks 2
Position is corresponding, and 8x8 sub-blocks c is corresponding with the position of 8x8 sub-blocks 3, and 8x8 sub-blocks d is corresponding with the position of 8x8 sub-blocks 4.Then join
Examining frame multiplexing maintenance unit can judge whether the whole pixel motion vector of 8x8 sub-blocks a and 8x8 sub-blocks 1 is identical, illustrates if identical
The reference pixel of the two sub-blocks is the 8x8 sub-blocks that can be multiplexed reference pixel, illustrates that their SAD costs are identical, that is, calculates
What is gone out divides pixel motion vector identical.Thus when calculating to the SAD costs of 8x8 layers of 8x8 sub-blocks a, calculating step can be skipped,
And the SAD costs of the 8x8 sub-blocks 1 for the 16x16 layers being calculated before directly using, it is on the one hand not necessarily to reacquire 8x8
The reference pixel of block 1 saves and calculates step and power consumption, on the other hand avoids difference of identical whole pixel fraction vector
Block computes repeatedly SAD costs, substantially increases code efficiency.
Then the second acquisition module obtains the corresponding original block pixel of 16x16 sub-blocks, institute from second cache module
State the corresponding original block pixel of the first register cell caching 16x16 sub-blocks.In the present embodiment, obtaining original block pixel is
It is that unit is obtained based on 16x16 sub-blocks.In this way, calculating when dividing pixel motion vector of each 16x16 sub-blocks, just will
The original block pixel of required different layers is disposably got in main control unit, and is cached by the first register cell.
Due to either 16x16 layers of 4 8x8 blocks or the 4 of 8x8 layers 8x8 blocks or the 16 of 4x4 layers 4x4 blocks, they are right
The original block pixel answered is both contained in the original block pixel of 16x16 sub-blocks, thus in the SAD for calculating each different straton block
When cost, the second acquisition module need to only be obtained from the first register cell, without again several times from the second caching mould
It is obtained in block, to improve the extent for multiplexing of original block pixel.
Then third acquisition module is according to the correspondence between whole pixel motion vector, from the third cache module
Reference block pixel is obtained, second register cell caches reference block pixel.It is in the present embodiment, described that " third obtains
Module obtains reference block pixel according to the correspondence between whole pixel motion vector from the third cache module " include：
If reference frame is multiplexed the second whole pixel motion vector of the 8x8 sub-blocks of the 8x8 layers of maintenance unit record and a upper 8x8 layers of 8x8
Second whole pixel motion vector of sub-block is identical, then the third acquisition module obtains reference block picture not from third cache module
Element, otherwise third acquisition module reference block pixel is obtained from third cache module.
In the present embodiment, the correspondence of the second whole pixel motion vector of 8x8 layers of difference 8x8 sub-blocks specifically wraps
It includes：Whether the second whole pixel motion vector for recording the 8x8 sub-blocks of the 8x8 layers of adjacent encoder sequence is identical.Such as 8x8 layers include
The 8x8 sub-blocks for having 4 8x8 layers are 8x8 sub-block a, 8x8 sub-block b, 8x8 sub-block c and 8x8 sub-blocks d respectively.Coded sequence is successively
Sub-block a, sub-block b, sub-block c and sub-block d.So reference frame multiplexing maintenance unit can judge successively 8x8 sub-blocks a and 8x8 sub-blocks b it
Between, the second whole pixel motion vector between 8x8 sub-block b and 8x8 sub-blocks c, between 8x8 sub-block c and 8x8 sub-blocks d it is whether identical,
And result is recorded.Such as the second whole pixel motion vector of sub-block a and sub-block b is identical, then illustrates the two sub-blocks
Reference pixel is the 8x8 sub-blocks that can be multiplexed reference pixel, illustrates that their SAD costs are identical, i.e. calculated point of pixel fortune
Dynamic vector is identical.Thus when calculating to the SAD costs of 8x8 layers of 8x8 sub-blocks b, calculating step can be skipped, and directly uses it
On the one hand the SAD costs of the 8x8 sub-blocks a of preceding 8x8 layers be calculated are not necessarily to reacquire the reference pixel of 8x8 sub-blocks b,
It saves calculating step and power consumption, the different sub-blocks on the other hand avoiding identical whole pixel fraction vector computes repeatedly SAD
Cost substantially increases code efficiency.The correspondence of the whole pixel motion vector of third of 4x4 layers of difference 4x4 sub-blocks similarly may be used
, it specifically includes：Whether the second whole pixel motion vector for recording the 8x8 sub-blocks of the 8x8 layers of adjacent encoder sequence is identical.And such as
The second whole pixel motion vector of fruit block a and sub-block b is different, then illustrates the result of calculation of the SAD costs between two sub-blocks
It is different, thus when calculating the SAD costs of sub-block b, needs to obtain the corresponding reference blocks of sub-block b from third cache module
Pixel, the SAD to continue sub-block b are calculated.
It is in some embodiments, described that " third acquisition module is used for according to the corresponding pass between whole pixel motion vector
System obtains reference block pixel from the third cache module " include：If reference frame is multiplexed the 4x4 layers of maintenance unit record
The third pixel motion vector of 4x4 sub-blocks is identical as upper a 4x4 layers of the third pixel motion vector of 4x4 sub-blocks, then and described
Three acquisition modules obtain reference block pixel not from third cache module, and otherwise third acquisition module is obtained from third cache module
Take reference block pixel.
Include 16 4x4 layers of 4x4 sub-blocks for 4x4 layers, with 4x4 layers of first 4 to sort according to coded sequence
It is 4x4 sub-blocks 1,4x4 sub-blocks 2,4x4 sub-blocks 3 and 4x4 sub-blocks 4 respectively for 4x4 sub-blocks.Reference frame multiplexing maintenance unit can be sentenced
Third between disconnected 4x4 sub-blocks 1 and 4x4 sub-blocks 2, between 4x4 sub-blocks 2 and 4x4 sub-blocks 3, between 4x4 sub-blocks 3 and 4x4 sub-blocks 4
Whether whole pixel motion vector is identical, and is stored record to result.When obtaining the reference block pixel of 4x4 sub-blocks 1, third
Acquiring unit can obtain a reference block for being several times as much as 4x4 sub-block sizes from third cache module, and by acquired reference
Block picture element caching is in the second register, such as in the present embodiment, the size of acquired reference block be 32x10 or
10x32 sizes.When calculating the SAD costs of 4x4 sub-blocks 2, if 4x4 sub-blocks 1 and 4x4 that reference frame multiplexing maintenance unit is recorded
The whole pixel motion vector of third is identical between sub-block 2, then illustrates that the reference pixel of 4x4 sub-blocks 1 and 4x4 sub-blocks 2 is that can be multiplexed
The 4x4 sub-blocks of reference pixel illustrate that their SAD costs are identical, i.e., calculated point of pixel motion vector is identical.Thus counting
When calculating the SAD costs of 4x4 sub-blocks 2, calculating step can be skipped, and the SAD for the 4x4 sub-blocks 1 being calculated before directly using
On the one hand cost is not necessarily to reacquire the reference pixel of 4x4 sub-blocks 2, saves and calculate step and power consumption, on the other hand avoid
The different sub-blocks of identical whole pixel fraction vector compute repeatedly SAD costs, substantially increase code efficiency.And if 4x4
Block 1 is different from the whole pixel motion vector of the third of 4x4 sub-blocks 2, then illustrates that the reference block pixel that they to be obtained is different,
Thus third acquisition module can search for the reference block pixel that whether there is needed for 4x4 sub-blocks 2 in the second register first,
(be one due to caching and be several times as much as the reference block of 4x4 sub-block sizes, thus can be scanned in the second register first),
If in the presence of if third acquisition module 2 corresponding reference block pixel of 4x4 sub-blocks is obtained from the second register, to carry out 4x4
The calculating of the SAD costs of block 2, if third acquisition module can acquisition one be several times as much as from third buffer unit again there is no if
The reference block of 4x4 sub-block sizes, and by acquired reference block picture element caching in the second register (refresh register), then
Repeat the above steps the reference block pixel reacquired from the second register needed for 4x4 sub-blocks 2.
Then SAD cost calculating units 107 obtain original block pixel from first register cell, and from described
Second register cell obtains reference block pixel, and carries out SAD cost calculating, obtains the reference block pixel of multiple and different positions
SAD costs.SAD costs can be a numerical value, and it is the block of pixels to calculate the call parameter needed for the SAD costs of some block of pixels
Corresponding original block pixel and reference block pixel, specifically, in H264 agreements, for each reference block pixel, SAD generations
Valence computing unit interpolation can go out the reference block pixel of 49 different locations in its vicinity, and calculate separately this 49 different locations
The corresponding SAD costs of reference block pixel, specific algorithm is according to H264 agreements.
Then the reference block pixel SAD costs of different location are compared by SAD costs selection unit, choose SAD costs
The SAD cost values of minimum reference block pixel, and calculate the reference block pixel and original block pixel divides pixel motion vector.
SAD costs be characterize the reference block pixel whether be optimal reference block pixel physical quantity, SAD costs are smaller, illustrate to refer to
Block pixel is closer to original block pixel.The reference block pixel for 49 different locations that SAD costs selection unit can go out from institute's interpolation
In, the SAD cost values of the reference block pixel of SAD Least-costs are chosen, and calculate point of the reference block pixel with original block pixel
Pixel motion vector, what is be calculated divides pixel motion vector to be that acquired original block pixel divides pixel motion vector.
So far, divide pixel motion vector calculating to finish, next step can be entered.
What the then reception of main control unit 109 SAD cost selection units were sent divides pixel motion vector, and will divide pixel motion
Vector is written in the first cache module.It is in the present embodiment, described that " main control unit will divide pixel motion vector write-in first to delay
In storing module " include：Main control unit will be for that will divide pixel motion vector and this to divide pixel motion vector corresponding whole pixel motion
Vector is written after being packaged in the first cache module.
Referring to Fig. 2, and inventor additionally provide it is a kind of dividing pixel motion vector computational methods based on H264 agreements,
The method is applied to divide pixel motion vector computing device, described device to divide picture for computing macro block based on H264 agreements
Plain motion vector, the macro block are divided into multiple 16x16 sub-blocks；Every 16x16 sub-blocks are divided into 4 8x8 sub-blocks, each
8x8 sub-blocks are divided into 4 4x4 sub-blocks；Described device include buffer unit, main control unit, reference frame multiplexing maintenance unit,
SAD cost calculating units, SAD cost selection units；The buffer unit is connect with main control unit, the main control unit and reference
Frame is multiplexed maintenance unit connection, and the reference frame multiplexing maintenance unit is connect with SAD cost calculating units, the SAD costs meter
It calculates unit to connect with SAD cost selection units, the SAD costs selection unit is connect with main control unit；The buffer unit packet
Include the first cache module, the second cache module, third cache module；The main control unit includes acquiring unit and register list
Member；The acquiring unit includes the first acquisition module, the second acquisition module and third acquisition module；The register cell includes
First register cell and the second register cell；Described method includes following steps：
Initially enter the whole pixel that the first acquisition modules of step S201 obtain 16x16 sub-blocks from first cache module
Motion vector.First cache module is the electronic component with storage data function, such as can be ROM memory.It is right
For each 16x16 sub-block, " three layers " structure can be divided into, i.e. 16x16 layers, 8x8 layers and 4x4 layers.For
For 16x16 layers, i.e., if being divided as unit of 16x16,16x16 sub-blocks can be divided into 1 16x16 block, thus
Each 16x16 sub-block is corresponding with 1 16x16 layers of whole pixel motion vector, i.e., the first whole pixel motion vector.For 8x8
For layer, i.e., if being divided as unit of 8x8,16x16 sub-blocks can be divided into 4 8x8 blocks, thus each
16x16 sub-blocks are corresponding with 4 8x8 layers of whole pixel motion vector, i.e., the second whole pixel motion vector.For 4x4 layers, i.e.,
If being divided as unit of 4x4,16x16 sub-blocks can be divided into 16 4x4 blocks, thus each 16x16 sub-block pair
Should there are 16 4x4 layers of whole pixel motion vector, the i.e. whole pixel motion vector of third.To sum up, each 16x16 sub-block is being calculated
When dividing pixel motion vector, the first acquisition module need from first cache module obtain 1 16x16 layers, 4 8x8
Layer and 16 4x4 layers total 21 whole pixel motion vector.
It then enters step S202 reference frames multiplexing maintenance unit and records correspondence between whole pixel motion vector, institute
The correspondence for stating whole pixel motion vector includes that the first whole pixel motion vector and the corresponding of the second whole pixel motion vector are closed
System, 8x8 layers of difference 8x8 sub-blocks the second whole pixel motion vector correspondence and 4x4 layers of difference 4x4 sub-blocks third it is whole
The correspondence of pixel motion vector.In the present embodiment, calculate 16x16 layers when dividing pixel motion vector and base
It is calculated for unit in the block of 8x8 sizes, thus pair of the first whole pixel motion vector and the second whole pixel motion vector
It should be related to and specifically include：Record the first whole pixel motion vector and the second whole pixel motion vector of the 8x8 sub-blocks of same position
It is whether identical.
Include 4 16x16 layers of 8x8 sub-blocks such as 16x16 layers, is 8x8 sub-blocks 1,8x8 sub-blocks respectively
2,8x8 sub-blocks 3 and 8x8 sub-blocks 4.Include 4 8x8 layers of 8x8 sub-blocks for 8x8 layers, is 8x8 sub-blocks a, 8x8 respectively
Sub-block b, 8x8 sub-block c and 8x8 sub-block d.8x8 sub-blocks a is corresponding with the position of 8x8 sub-blocks 1,8x8 sub-blocks b and 8x8 sub-blocks 2
Position is corresponding, and 8x8 sub-blocks c is corresponding with the position of 8x8 sub-blocks 3, and 8x8 sub-blocks d is corresponding with the position of 8x8 sub-blocks 4.Then join
Examining frame multiplexing maintenance unit can judge whether the whole pixel motion vector of 8x8 sub-blocks a and 8x8 sub-blocks 1 is identical, illustrates if identical
The reference pixel of the two sub-blocks is the 8x8 sub-blocks that can be multiplexed reference pixel, illustrates that their SAD costs are identical, that is, calculates
What is gone out divides pixel motion vector identical.Thus when calculating to the SAD costs of 8x8 layers of 8x8 sub-blocks a, calculating step can be skipped,
And the SAD costs of the 8x8 sub-blocks 1 for the 16x16 layers being calculated before directly using, it is on the one hand not necessarily to reacquire 8x8
The reference pixel of block 1 saves and calculates step and power consumption, on the other hand avoids difference of identical whole pixel fraction vector
Block computes repeatedly SAD costs, substantially increases code efficiency.
It then enters step the second acquisition modules of S203 and obtains the corresponding original of 16x16 sub-blocks from second cache module
Beginning block pixel, first register cell cache the corresponding original block pixel of 16x16 sub-blocks.In the present embodiment, it obtains
It is that unit is obtained that original block pixel, which is based on 16x16 sub-blocks,.In this way, being transported in point pixel for calculating each 16x16 sub-blocks
When dynamic vector, just the original block pixel of required different layers is disposably got in main control unit, and pass through the first register
Unit is cached.Due to either 16x16 layers of 4 8x8 blocks or the 4 of 8x8 layers 8x8 blocks or the 16 of 4x4 layers
A 4x4 blocks, their corresponding original block pixels are both contained in the original block pixel of 16x16 sub-blocks, thus each not in calculating
When the SAD costs of same straton block, the second acquisition module need to only be obtained from the first register cell, more without dividing again
It is secondary to be obtained from the second cache module, to improve the extent for multiplexing of original block pixel.
S204 thirds acquisition module is then entered step according to the correspondence between whole pixel motion vector, from described
Reference block pixel is obtained in three cache modules, second register cell caches reference block pixel.In the present embodiment, institute
State that " third acquisition module obtains reference according to the correspondence between whole pixel motion vector from the third cache module
Block pixel " includes：If reference frame be multiplexed maintenance unit record 8x8 layers 8x8 sub-blocks the second whole pixel motion vector with it is upper
Second whole pixel motion vector of one 8x8 layers of 8x8 sub-blocks is identical, then the third acquisition module is not from third cache module
Reference block pixel is obtained, otherwise third acquisition module obtains reference block pixel from third cache module.
In the present embodiment, the correspondence of the second whole pixel motion vector of 8x8 layers of difference 8x8 sub-blocks specifically wraps
It includes：Whether the second whole pixel motion vector for recording the 8x8 sub-blocks of the 8x8 layers of adjacent encoder sequence is identical.Such as 8x8 layers include
The 8x8 sub-blocks for having 4 8x8 layers are 8x8 sub-block a, 8x8 sub-block b, 8x8 sub-block c and 8x8 sub-blocks d respectively.Coded sequence is successively
Sub-block a, sub-block b, sub-block c and sub-block d.So reference frame multiplexing maintenance unit can judge successively 8x8 sub-blocks a and 8x8 sub-blocks b it
Between, the second whole pixel motion vector between 8x8 sub-block b and 8x8 sub-blocks c, between 8x8 sub-block c and 8x8 sub-blocks d it is whether identical,
And result is recorded.Such as the second whole pixel motion vector of sub-block a and sub-block b is identical, then illustrates the two sub-blocks
Reference pixel is the 8x8 sub-blocks that can be multiplexed reference pixel, illustrates that their SAD costs are identical, i.e. calculated point of pixel fortune
Dynamic vector is identical.Thus when calculating to the SAD costs of 8x8 layers of 8x8 sub-blocks b, calculating step can be skipped, and directly uses it
On the one hand the SAD costs of the 8x8 sub-blocks a of preceding 8x8 layers be calculated are not necessarily to reacquire the reference pixel of 8x8 sub-blocks b,
It saves calculating step and power consumption, the different sub-blocks on the other hand avoiding identical whole pixel fraction vector computes repeatedly SAD
Cost substantially increases code efficiency.The correspondence of the whole pixel motion vector of third of 4x4 layers of difference 4x4 sub-blocks similarly may be used
, it specifically includes：Whether the second whole pixel motion vector for recording the 8x8 sub-blocks of the 8x8 layers of adjacent encoder sequence is identical.And such as
The second whole pixel motion vector of fruit block a and sub-block b is different, then illustrates the result of calculation of the SAD costs between two sub-blocks
It is different, thus when calculating the SAD costs of sub-block b, needs to obtain the corresponding reference blocks of sub-block b from third cache module
Pixel, the SAD to continue sub-block b are calculated.
It is in some embodiments, described that " third acquisition module is used for according to the corresponding pass between whole pixel motion vector
System obtains reference block pixel from the third cache module " include：If reference frame is multiplexed the 4x4 layers of maintenance unit record
The third pixel motion vector of 4x4 sub-blocks is identical as upper a 4x4 layers of the third pixel motion vector of 4x4 sub-blocks, then and described
Three acquisition modules obtain reference block pixel not from third cache module, and otherwise third acquisition module is obtained from third cache module
Take reference block pixel.
Include 16 4x4 layers of 4x4 sub-blocks for 4x4 layers, with 4x4 layers of first 4 to sort according to coded sequence
It is 4x4 sub-blocks 1,4x4 sub-blocks 2,4x4 sub-blocks 3 and 4x4 sub-blocks 4 respectively for 4x4 sub-blocks.Reference frame multiplexing maintenance unit can be sentenced
Third between disconnected 4x4 sub-blocks 1 and 4x4 sub-blocks 2, between 4x4 sub-blocks 2 and 4x4 sub-blocks 3, between 4x4 sub-blocks 3 and 4x4 sub-blocks 4
Whether whole pixel motion vector is identical, and is stored record to result.When obtaining the reference block pixel of 4x4 sub-blocks 1, third
Acquiring unit can obtain a reference block for being several times as much as 4x4 sub-block sizes from third cache module, and by acquired reference
Block picture element caching is in the second register, such as in the present embodiment, the size of acquired reference block be 32x10 or
10x32 sizes.When calculating the SAD costs of 4x4 sub-blocks 2, if 4x4 sub-blocks 1 and 4x4 that reference frame multiplexing maintenance unit is recorded
The whole pixel motion vector of third is identical between sub-block 2, then illustrates that the reference pixel of 4x4 sub-blocks 1 and 4x4 sub-blocks 2 is that can be multiplexed
The 4x4 sub-blocks of reference pixel illustrate that their SAD costs are identical, i.e., calculated point of pixel motion vector is identical.Thus counting
When calculating the SAD costs of 4x4 sub-blocks 2, calculating step can be skipped, and the SAD for the 4x4 sub-blocks 1 being calculated before directly using
On the one hand cost is not necessarily to reacquire the reference pixel of 4x4 sub-blocks 2, saves and calculate step and power consumption, on the other hand avoid
The different sub-blocks of identical whole pixel fraction vector compute repeatedly SAD costs, substantially increase code efficiency.And if 4x4
Block 1 is different from the whole pixel motion vector of the third of 4x4 sub-blocks 2, then illustrates that the reference block pixel that they to be obtained is different,
Thus third acquisition module can search for the reference block pixel that whether there is needed for 4x4 sub-blocks 2 in the second register first,
(be one due to caching and be several times as much as the reference block of 4x4 sub-block sizes, thus can be scanned in the second register first),
If in the presence of if third acquisition module 2 corresponding reference block pixel of 4x4 sub-blocks is obtained from the second register, to carry out 4x4
The calculating of the SAD costs of block 2, if third acquisition module can acquisition one be several times as much as from third buffer unit again there is no if
The reference block of 4x4 sub-block sizes, and by acquired reference block picture element caching in the second register (refresh register), then
Repeat the above steps the reference block pixel reacquired from the second register needed for 4x4 sub-blocks 2.
It then enters step S205SAD cost calculating units and obtains original block pixel from first register cell,
And reference block pixel is obtained from second register cell, and SAD cost calculating is carried out, obtain the ginseng of multiple and different positions
Examine block pixel SAD costs.SAD costs can be a numerical value, and calculating the call parameter needed for the SAD costs of some block of pixels is
The corresponding original block pixel of the block of pixels and reference block pixel, specifically, in H264 agreements, for each reference block pixel
Speech, SAD cost calculating units interpolation can go out the reference block pixel of 49 different locations in its vicinity, and calculate separately this 49 not
The corresponding SAD costs with the reference block pixel of position, specific algorithm is according to H264 agreements.
S206SAD costs selection unit is then entered step to be compared the reference block pixel SAD costs of different location,
The SAD cost values of the reference block pixel of SAD Least-costs are chosen, and calculate point pixel of the reference block pixel and original block pixel
Motion vector.SAD costs be characterize the reference block pixel whether be optimal reference block pixel physical quantity, SAD costs are smaller,
Illustrate reference block pixel closer to original block pixel.The ginseng for 49 different locations that SAD costs selection unit can go out from institute's interpolation
It examines in block pixel, chooses the SAD cost values of the reference block pixel of SAD Least-costs, and calculate the reference block pixel and original block
Pixel divides pixel motion vector, and what is be calculated divides pixel motion vector to be that a point pixel for acquired original block pixel is transported
Dynamic vector.So far, divide pixel motion vector calculating to finish, next step can be entered.
The pixel motion vector that divides that S207 main control units 109 receive the transmission of SAD cost selection units is then entered step, and
Pixel motion vector will be divided to be written in the first cache module.It is in the present embodiment, described that " main control unit will divide pixel motion to swear
In amount the first cache module of write-in " include：Main control unit will be for that will divide pixel motion vector to divide pixel motion vector corresponding with this
Whole pixel motion vector be packaged after be written in the first cache module.
Divide pixel motion vector computational methods and device, the method application based on H264 agreements described in said program
In dividing pixel motion vector computing device based on H264 agreements, described device divides pixel motion vector for computing macro block,
Described device includes buffer unit, main control unit, reference frame multiplexing maintenance unit, SAD cost calculating units, the selection of SAD costs
Unit.Described method includes following steps：First acquisition module first obtains 16x16 sub-blocks from first cache module
Whole pixel motion vector；Then reference frame multiplexing maintenance unit records the correspondence between whole pixel motion vector；Then
Two acquisition modules obtain the corresponding original block pixel of 16x16 sub-blocks from second cache module, third acquisition module according to
Correspondence between whole pixel motion vector obtains reference block pixel from the third cache module；Then SAD costs meter
It calculates unit and obtains original block pixel from first register cell, and reference block is obtained from second register cell
Pixel, and SAD cost calculating is carried out, obtain the reference block pixel SAD costs of multiple and different positions；Then SAD costs are chosen single
The reference block pixel SAD costs of different location are compared by member, choose the SAD costs of the reference block pixel of SAD Least-costs
Value, and calculate the reference block pixel and original block pixel divides pixel motion vector；Then main control unit receives SAD costs and chooses
What unit was sent divides pixel motion vector, and pixel motion vector will be divided to be written in the first cache module.In this way, calculating H264
Agreement is divided during pixel motion vector, and acquired size of the original block pixel based on 16x16 blocks is obtained, and ensure that
The durability of the original block pixel of 8x8 blocks and 4x4 blocks；When obtaining reference block pixel, maintenance unit note is multiplexed according to reference frame
The correspondence between whole pixel motion vector is recorded, (16x16 layers, 8x8 layers of each layer there is no multiplexed situation is selectively obtained
And 4x4 layers) reference block pixel obtained, and the reference block pixel that can be multiplexed then is not repeated to obtain, to
The reusability of reference pixel is substantially increased, and improves the computational efficiency of point pixel motion vector, saves power consumption, simultaneously also
Hardware cost is saved.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that process, method, article or terminal device including a series of elements include not only those
Element, but also include other elements that are not explicitly listed, or further include for this process, method, article or end
The intrinsic element of end equipment.In the absence of more restrictions, being limited by sentence " including ... " or " including ... "
Element, it is not excluded that there is also other elements in process, method, article or the terminal device including the element.This
Outside, herein, " being more than ", " being less than ", " being more than " etc. are interpreted as not including this number；" more than ", " following ", " within " etc. understandings
It includes this number to be.
Although the various embodiments described above are described, once a person skilled in the art knows basic wounds
The property made concept, then additional changes and modifications can be made to these embodiments, so example the above is only the implementation of the present invention,
It is not intended to limit the scope of patent protection of the present invention, it is every to utilize equivalent structure made by description of the invention and accompanying drawing content
Or equivalent process transformation, it is applied directly or indirectly in other relevant technical fields, the patent for being similarly included in the present invention
Within protection domain.
Claims (10)
1. a kind of divide pixel motion vector computing device, a point pixel of the described device for computing macro block to transport based on H264 agreements
Dynamic vector, which is characterized in that the macro block is divided into multiple 16x16 sub-blocks；Every 16x16 sub-blocks are divided into 4 8x8
Block, every 8x8 sub-blocks are divided into 4 4x4 sub-blocks；Described device includes buffer unit, main control unit, reference frame multiplexing maintenance
Unit, SAD cost calculating units, SAD cost selection units；The buffer unit is connect with main control unit, the main control unit
It is connect with reference frame multiplexing maintenance unit, the reference frame multiplexing maintenance unit is connect with SAD cost calculating units, the SAD
Cost calculating unit is connect with SAD cost selection units, and the SAD costs selection unit is connect with main control unit；The caching
Unit includes the first cache module, the second cache module, third cache module；The main control unit includes acquiring unit and deposit
Device unit；The acquiring unit includes the first acquisition module, the second acquisition module and third acquisition module；The register cell
Including the first register cell and the second register cell；
Whole pixel motion vector of first acquisition module for obtaining 16x16 sub-blocks from first cache module, institute
It includes the first whole pixel motion vector, the second whole pixel motion vector and the whole pixel motion arrow of third to state whole pixel motion vector
Amount, the whole pixel motion vector that the first whole pixel motion vector is 16x16 layers in 16x16 sub-blocks, the second whole pixel
The whole pixel motion vector that motion vector is 8x8 layers in 16x16 sub-blocks, the whole pixel motion vector of third are 16x16 sub-blocks
Middle 4x4 layers of whole pixel motion vector；
The reference frame multiplexing maintenance unit is used to record the correspondence between whole pixel motion vector, the whole pixel motion
The correspondence of vector includes：Compare same position the first whole pixel motion vector and the second whole pixel motion vector whether phase
With whether the second whole pixel motion vector of, adjacent encoder sequence identical and the whole pixel vector of third of adjacent encoder sequence is
It is no identical；
Second acquisition module is used to obtain the corresponding original block pixel of 16x16 sub-blocks, institute from second cache module
The first register cell is stated for caching the corresponding original block pixel of 16x16 sub-blocks；
The third acquisition module is used for according to the correspondence between whole pixel motion vector, from the third cache module
Reference block pixel is obtained, second register cell is for caching reference block pixel；
The SAD cost calculating units are used to obtain original block pixel from first register cell, and from described the
Two register cells obtain reference block pixel, and carry out SAD cost calculating, obtain the reference block pixel SAD of multiple and different positions
Cost；
The SAD costs selection unit chooses SAD costs for the reference block pixel SAD costs of different location to be compared
The SAD cost values of minimum reference block pixel, and calculate the reference block pixel and original block pixel divides pixel motion vector；
What the main control unit was used to receive the transmission of SAD cost selection units divides pixel motion vector, and pixel motion will be divided to swear
In amount the first cache module of write-in.
2. dividing pixel motion vector computing device based on H264 agreements as described in claim 1, which is characterized in that described
" third acquisition module is used to, according to the correspondence between whole pixel motion vector, ginseng is obtained from the third cache module
Examine block pixel " include：If the second whole pixel motion vector of 8x8 layers of 8x8 sub-blocks is identical as the first whole pixel motion vector,
The third acquisition module obtains reference block pixel not from third cache module, and otherwise third acquisition module caches mould from third
Reference block pixel is obtained in block.
3. dividing pixel motion vector computing device based on H264 agreements as claimed in claim 1 or 2, which is characterized in that institute
State " third acquisition module be used for according to the correspondence between whole pixel motion vector, obtained from the third cache module
Reference block pixel " includes：If reference frame is multiplexed the second whole pixel motion vector of the 8x8 sub-blocks of the 8x8 layers of maintenance unit record
Identical as the second whole pixel motion vector of upper a 8x8 layers of 8x8 sub-blocks, then the third acquisition module does not cache mould from third
Reference block pixel is obtained in block, otherwise third acquisition module obtains reference block pixel from third cache module.
4. dividing pixel motion vector computing device based on H264 agreements as claimed in claim 1 or 2, which is characterized in that institute
State " third acquisition module be used for according to the correspondence between whole pixel motion vector, obtained from the third cache module
Reference block pixel " includes：If reference frame be multiplexed maintenance unit record 4x4 layers 4x4 sub-blocks third pixel motion vector and
The third pixel motion vector of upper a 4x4 layers of 4x4 sub-blocks is identical, then the third acquisition module is not from third cache module
Reference block pixel is obtained, otherwise third acquisition module obtains reference block pixel from third cache module.
5. dividing pixel motion vector computing device based on H264 agreements as described in claim 1, which is characterized in that described
" main control unit will be for that will divide pixel motion vector to be written in the first cache module " includes：Main control unit will be for that will divide pixel motion
Vector with this divide the corresponding whole pixel motion vector of pixel motion vector to be packaged after be written in the first cache module.
6. a kind of divide pixel motion vector computational methods, the method to be applied to point based on H264 agreements based on H264 agreements
Pixel motion vector computing device, described device divide pixel motion vector for computing macro block, which is characterized in that the macro block
It is divided into multiple 16x16 sub-blocks；Every 16x16 sub-blocks are divided into 4 8x8 sub-blocks, and every 8x8 sub-blocks are divided into 4
4x4 sub-blocks；Described device includes buffer unit, main control unit, reference frame multiplexing maintenance unit, SAD cost calculating units, SAD
Cost selection unit；The buffer unit is connect with main control unit, and the main control unit is connect with reference frame multiplexing maintenance unit,
The reference frame multiplexing maintenance unit is connect with SAD cost calculating units, and the SAD cost calculating units are chosen with SAD costs
Unit connects, and the SAD costs selection unit is connect with main control unit；The buffer unit includes the first cache module, second
Cache module, third cache module；The main control unit includes acquiring unit and register cell；The acquiring unit includes the
One acquisition module, the second acquisition module and third acquisition module；The register cell includes the first register cell and second
Register cell；Described method includes following steps：
First acquisition module obtains the whole pixel motion vector of 16x16 sub-blocks, the whole pixel from first cache module
Motion vector includes the first whole pixel motion vector, the second whole pixel motion vector and the whole pixel motion vector of third, and described the
The whole pixel motion vector that one whole pixel motion vector is 16x16 layers in 16x16 sub-blocks, the second whole pixel motion vector are
8x8 layers of whole pixel motion vector in 16x16 sub-blocks, the whole pixel motion vector of third are 4x4 layers whole in 16x16 sub-blocks
Pixel motion vector；
Reference frame multiplexing maintenance unit records the correspondence between whole pixel motion vector, pair of the whole pixel motion vector
Should be related to including：Whether the first whole pixel motion vector and the second whole pixel motion vector for comparing same position are identical, adjacent
Whether the second whole pixel motion vector of coded sequence identical and whether the whole pixel vector of third of adjacent encoder sequence is identical；
Second acquisition module obtains the corresponding original block pixel of 16x16 sub-blocks, the first register from second cache module
The corresponding original block pixel of unit caches 16x16 sub-blocks；
Third acquisition module obtains reference according to the correspondence between whole pixel motion vector from the third cache module
Block pixel, the second register cell cache reference block pixel；
SAD cost calculating units obtain original block pixel from first register cell, and from second register
Unit obtains reference block pixel, and carries out SAD cost calculating, obtains the reference block pixel SAD costs of multiple and different positions；
The reference block pixel SAD costs of different location are compared by SAD costs selection unit, choose the ginseng of SAD Least-costs
The SAD cost values of block pixel are examined, and calculate the reference block pixel and original block pixel divides pixel motion vector；
What main control unit received that SAD cost selection units send divides pixel motion vector, and will divide pixel motion vector write-in the
In one cache module.
7. dividing pixel motion vector computational methods based on H264 agreements as claimed in claim 6, which is characterized in that the step
Suddenly " third acquisition module obtains reference according to the correspondence between whole pixel motion vector from the third cache module
Block pixel " includes：
If the second whole pixel motion vector of 8x8 layers of 8x8 sub-blocks is identical as the first whole pixel motion vector, the third obtains
Modulus block obtains reference block pixel not from third cache module, and otherwise third acquisition module obtains ginseng from third cache module
Examine block pixel.
8. as claimed in claims 6 or 7 divide pixel motion vector computational methods based on H264 agreements, which is characterized in that institute
Stating step, " third acquisition module is obtained according to the correspondence between whole pixel motion vector from the third cache module
Reference block pixel " includes：
If reference frame be multiplexed the 8x8 sub-blocks of the 8x8 layers of maintenance unit record the second whole pixel motion vector and upper a 8x8 layers
Second whole pixel motion vector of 8x8 sub-blocks is identical, then the third acquisition module obtains reference not from third cache module
Block pixel, otherwise third acquisition module reference block pixel is obtained from third cache module.
9. as claimed in claims 6 or 7 divide pixel motion vector computational methods based on H264 agreements, which is characterized in that institute
Stating step, " third acquisition module is obtained according to the correspondence between whole pixel motion vector from the third cache module
Reference block pixel " includes：
If reference frame be multiplexed the 4x4 sub-blocks of the 4x4 layers of maintenance unit record third pixel motion vector and upper a 4x4 layers
The third pixel motion vector of 4x4 sub-blocks is identical, then the third acquisition module does not obtain reference block from third cache module
Pixel, otherwise third acquisition module reference block pixel is obtained from third cache module.
10. dividing pixel motion vector computational methods based on H264 agreements as claimed in claim 6, which is characterized in that described
Step " main control unit will divide pixel motion vector be written the first cache module in " include：
After main control unit will divide pixel motion vector to divide the corresponding whole pixel motion vector of pixel motion vector to be packaged with this
It is written in the first cache module.
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| CN107197281A (en) * | 2017-05-12 | 2017-09-22 | 武汉斗鱼网络科技有限公司 | A kind of method and electronic equipment for realizing estimation |
| CN110662054B (en) | 2018-06-29 | 2023-01-06 | 北京字节跳动网络技术有限公司 | Method, device, computer-readable storage medium for video processing |
| JP7256265B2 (en) | 2018-06-29 | 2023-04-11 | 北京字節跳動網絡技術有限公司 | Lookup table update: FIFO, limited FIFO |
| CN110662052B (en) | 2018-06-29 | 2022-07-08 | 北京字节跳动网络技术有限公司 | Updating conditions of a look-up table (LUT) |
| KR20240007298A (en) | 2018-06-29 | 2024-01-16 | 베이징 바이트댄스 네트워크 테크놀로지 컴퍼니, 리미티드 | Checking order of motion candidates in lut |
| EP3791589A1 (en) | 2018-06-29 | 2021-03-17 | Beijing Bytedance Network Technology Co. Ltd. | Which lut to be updated or no updating |
| WO2020003282A1 (en) | 2018-06-29 | 2020-01-02 | Beijing Bytedance Network Technology Co., Ltd. | Managing motion vector predictors for video coding |
| WO2020003279A1 (en) | 2018-06-29 | 2020-01-02 | Beijing Bytedance Network Technology Co., Ltd. | Concept of using one or multiple look up tables to store motion information of previously coded in order and use them to code following blocks |
| JP7295231B2 (en) | 2018-06-29 | 2023-06-20 | 北京字節跳動網絡技術有限公司 | Interaction between LUT and AMVP |
| GB2589241B (en) | 2018-07-02 | 2023-06-07 | Beijing Bytedance Network Tech Co Ltd | Update of look-up tables |
| CN111064959B (en) | 2018-09-12 | 2023-09-01 | 北京字节跳动网络技术有限公司 | How many HMVP candidates to check |
| KR20240010576A (en) | 2019-01-10 | 2024-01-23 | 베이징 바이트댄스 네트워크 테크놀로지 컴퍼니, 리미티드 | Invoke of lut updating |
| CN113383554B (en) | 2019-01-13 | 2022-12-16 | 北京字节跳动网络技术有限公司 | Interaction between LUTs and shared Merge lists |
| CN113302937B (en) | 2019-01-16 | 2024-08-02 | 北京字节跳动网络技术有限公司 | Motion candidate derivation |
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