CN105681692B - Cmos image sensor and its reset noise appraisal procedure - Google Patents
Cmos image sensor and its reset noise appraisal procedure Download PDFInfo
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- CN105681692B CN105681692B CN201610019409.7A CN201610019409A CN105681692B CN 105681692 B CN105681692 B CN 105681692B CN 201610019409 A CN201610019409 A CN 201610019409A CN 105681692 B CN105681692 B CN 105681692B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
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- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Cmos image sensor and its reset noise appraisal procedure provided by the invention, cmos image sensor includes pixel circuit, difference channel, analog to digital conversion circuit and memory, wherein, pixel circuit includes photodiode, reset transistor, transmission transistor, storage capacitance, first buffer amplifier circuit and the second buffer amplifier circuit, the input terminal of the output end of transmission transistor and the first buffer amplifier circuit is connected to a node, the node level signal of node stores after the amplification of the first buffer amplifier circuit to storage capacitance, amplification posterior nodal point level signal is exported by the second buffer amplifier circuit to column output line.The present invention proposes a kind of reset noise appraisal procedure, i.e. multiple time points before and after sampling daylighting signal, samples reset signal, the real signal value under double sampled and correlated-double-sampling is respectively obtained, so as to assess reset noise in time domain and frequency domain.The cmos image sensor of the present invention reduces the complexity of pixel circuit, increases the scale of sensor.
Description
Technical field
The invention belongs to field of image sensors, and in particular to a kind of to be used for global shutter and double sampled 7T pixels CMOS
Imaging sensor and its reset noise appraisal procedure.
Background technology
Imaging sensor is the electronic device that incident optical signal is converted into electric signal, and imaging sensor includes being referred to as picture
The two-dimensional array of the light sensing element of element, each pixel in two-dimensional array are worked together with lens system with to scene part
Incident light in region responds, and generates the electric signal for the local feature for describing the scene.From the defeated of light sensing element
Go out and be converted into digital form, and store in digital form, to form the initial data for indicating the scene.Initial data can lead to
The processing of image processor is crossed to generate the digital picture finally presented.
The design of imaging sensor includes charge coupling device (CCD) and complementary metal oxide semiconductor (CMOS) figure
As sensor.Ccd image sensor is not preferred in modern designs, partly because CCD typically consumes higher level
Power, and require relative complex analog front circuit.Cmos image sensor consumes the power of reduced levels, and has
The built-in analog end digital quantizer of numeral output pixel value is provided.Therefore, cmos image sensor increasingly obtains widely
Using.
Existing cmos image sensor is made of CMOS digital-to-analog circuits and pixel unit circuit array, according to said one
The transistor size that pixel unit includes, the interior cmos image sensor without storage capacitance of existing pixel are broadly divided into 3T types
Structure, 4T types structure and 5T type structures.
Referring to Fig. 1, Fig. 1 is a kind of 3T pixel equivalent circuit knots without storage capacitance and without transmission transistor in the prior art
Structure schematic diagram, including：One photodiode PPD1 turns the optical signal received for carrying out opto-electronic conversion in exposure
Change electric signal into, photodiode PPD1 includes p type island region and N-type region, p type island region ground connection.
The imaging sensor further includes a reset transistor RST1, for being carried out before exposure to photodiode PPD1
It resets, reset is controlled by reset signal Vrst signals.In Fig. 1, reset transistor RST1 selects a NMOS tube, multiple
The source electrode of bit transistor RST1 is connected with the N-type region of photodiode PPD1, and the source electrode of reset transistor RST1 is also one simultaneously
Sense voltage node FD1 is also known as floating diffusion region（Floating Diffusion, FD）；The drain electrode of reset transistor RST1 connects
Power supply Vdd, power supply Vdd are a positive supply.When reset signal Vrst is high level, reset transistor RST1 conducting and by photoelectricity
The N-type region of diode PPD1 is connected to power supply Vdd, under the action of power supply Vdd, keeps photodiode PPD1 reverse-biased and meeting is clear
Except the charge of photodiode PPD1 all accumulated, realizes and reset.Reset transistor RST1 can also be by multiple NMOS tube strings
Connection is formed or is formed by multiple NMOS tube parallel connections, can also replace NMOS tube with PMOS pipes.
The imaging sensor further includes an amplifying transistor DX1, the electric signal for generating photodiode PPD1
It is amplified.In Fig. 1, amplifying transistor DX1 selects a NMOS tube, the grid of amplifying transistor DX1 to connect photodiode
The drain electrode of the N-type region of PPD1, amplifying transistor DX1 meets power supply Vdd, and the source electrode of amplifying transistor DX1 is the output of amplified signal
End.Amplifying transistor DX1 can also be connected by multiple NMOS pipes to be formed or is formed by multiple NMOS tube parallel connections, can also be used
PMOS tube replaces NMOS tube.
The imaging sensor further includes that a row selects transistor SX1, for putting the source electrode output of amplifying transistor DX1
Big signal output.In Fig. 1, row selects transistor SX1 to select a NMOS pipe, row that the grid of transistor SX1 is selected to connect row selection letter
Number VSEL, the capable source electrode for selecting the source electrode of transistor SX1 to connect amplifying transistor, it is output end that row, which selects transistor SX1 drain electrodes,.
Shown in Fig. 2 is a kind of 4T pixel equivalent circuit structures without storage capacitance and with transmission transistor in the prior art
Schematic diagram.In the pixel circuit of 3T type structures there is reset transistor RST2, amplifying transistor DX2 and row to select transistor SX2's
On the basis of, the pixel circuit of the cmos image sensor of existing 4T types structure increases a transmission transistor TX2.Transmit crystal
Photodiode PPD2 and amplifying transistor DX2 has been isolated in pipe TX2, is closed when photodiode PPD2 is resetted with electric charge transfer
It closes, to reduce influence of the noise to sense voltage node FD2.
As shown in Fig. 3 one kind is in the prior art without storage capacitance and with transmission transistor and with anti-halation transistor
5T pixel equivalent circuit structure schematic diagrames.There is reset transistor RST3, amplifying transistor in the pixel circuit of 4T type structures
On the basis of DX3, transmission transistor TX3 and row select transistor SX3, the pixel list of the cmos image sensor of existing 5T types structure
First circuit increases one and resets anti-halation transistor RSTAB3.The both ends of anti-halation reset transistor RSTAB3 respectively with power supply
Anode is connected with photodiode PPD3 cathode, is closed when photodiode PPD3 is resetted with electric charge transfer, to reduce noise
Influence to sense voltage node FD3.
In order to realize the functions such as global shutter and correlated-double-sampling, on the basis of the 3T type structures of cmos image sensor
On, the cmos image sensor with storage capacitance is divided into 6T types structure and 9T type structures in existing pixel, wherein 6T type structures
The pixel unit of cmos image sensor increase single storage capacitance and a pole Hyblid Buffer Amplifier, the cmos image of 9T type structures
The pixel unit of sensor increases double storage capacitances and a pole Hyblid Buffer Amplifier.
Cmos image sensor is included in the controlling transistor at each pixel, and controlling transistor is for controlling Photoelectric Detection
Light integral in device, control reset and provide Hyblid Buffer Amplifier for pixel.Cmos image sensor can support rolling shutter mould
Formula and/or global shutter pattern.Under rolling shutter pattern, per one-row pixels all when the pixel gone than immediately front is later
Between start exposure or light integral.Therefore, when the object in scene just when moving, rolling shutter pattern be easy to cause geometry mistake
Very.Under global shutter pattern, all pixels in entire cmos image sensor start simultaneously at and stop exposure or light integral,
It therefore can be to avoid the geometric distortion problem caused by the movement in scene.
Correlated-double-sampling（Correlated Double Sampling,CDS）It is a kind of reset electricity using each pixel
It puts down and attached the daylighting signal of reset level to eliminate the noise and heterogeneity in cmos image sensor pixel response
Method.For correlated-double-sampling, " reset level " first is sampled, re-sampling " daylighting signal " passes through the first sampled value（It is multiple
Bit level signal）Subtract the second sampled value（Daylighting signal）Obtain the actual pixel value of location of pixels.
As shown in Fig. 4 a kind of 6T pixel equivalent circuit knots for realizing global shutter and correlated-double-sampling in the prior art
Structure schematic diagram, it realizes global shutter and correlated-double-sampling.The imaging sensor includes photodiode PPD4, storage capacitance
Cp4, reset transistor RST4, low level reset transistor RSTGND4, the first amplifying transistor DX41, sampling transistor SX41,
Second amplifying transistor DX42 and row select transistor SX42.In order to realize correlated-double-sampling, there is full frame to deposit outside pixel circuit
Reservoir stores reset level.
As shown in Fig. 5 a kind of 9T pixel equivalent circuit knots for realizing global shutter and correlated-double-sampling in the prior art
Structure schematic diagram, it realizes global shutter and correlated-double-sampling.There is storage capacitance Cp51, multiple in the pixel circuit of 6T type structures
Bit transistor RST5, low level reset transistor RSTGND5, the first amplifying transistor DX51, sampling transistor SX51, second are put
On the basis of big transistor DX52 and row select transistor SX52, the pixel circuit of existing 9T types cmos image sensor increases
Storage capacitance Cp52, sampling transistor SX53, amplifying transistor DX54 and row select transistor SX54, and 9T pixel circuits do not have
Have and uses full frame memory.
From the foregoing, it will be observed that the pixel circuit of the cmos image sensor of 6T type structures is fairly simple, but a full frame is needed to deposit
Reservoir stores reset level, has used the outer chip space of more pixel；The pixel of the cmos image sensor of 9T type structures
Circuit has used double storage capacitances and 9 transistors, has used chip space in more pixel.Structure of need in practical application
Compact CMOS pixel circuits, so that the design to radioresistance hardness circuit and control signal Circuit with tolerance etc. is reserved more empty
Between.
Invention content
The main object of the present invention is to provide a kind of compact cmos image sensor simple for structure.
It is a further object of the present invention to provide a kind of cmos image sensor reset noise appraisal procedures.
To realize above-mentioned main purpose, cmos image sensor provided by the invention, including：Pixel circuit, differential electrical
Road, analog to digital conversion circuit and memory, pixel circuit sample daylighting and reset level signal and export to difference channel, lead to
It crosses difference channel and obtains the real signal value of pixel, and real signal value is exported to analog to digital conversion circuit, analog to digital conversion circuit
To output digit signals after real signal value progress analog-to-digital conversion to memory；Wherein, multiple before and after sampling daylighting signal
Time point sampling reset level signal；Pixel circuit include photodiode, transmission transistor, reset transistor, storage capacitance,
First buffer amplifier circuit and the second buffer amplifier circuit；The input of the output end of transmission transistor and the first buffer amplifier circuit
End is connected to a node, and the node level signal of the node is stored in storage capacitance after the amplification of the first buffer amplifier circuit
In, amplified node level signal is exported by the second buffer amplifier circuit to column output line.
By said program as it can be seen that photodiode and sense voltage has been isolated in the transmission transistor of the pixel circuit of the present invention
Node, such sense voltage node reset and photodiode daylighting integral can be carried out at the same time, while reduce full frame storage
Device reduces the complexity of pixel circuit, occupies less Pixel domain so that on the chip of limited areal, Ke Yizeng
Add the scale of cmos sensor.
One Preferable scheme is that, node level signal be daylighting signal or reset level signal.
Therefore when transmission transistor is closed progress global shutter exposure, sense voltage node level VFDIt reflects
Luminance signal, at this time sense voltage node level be daylighting signal, the sense voltage node reset when reset transistor resets, this
When sense voltage node level be reset level.
One Preferable scheme is that, reset level signal is attached on daylighting signal.
Therefore it is similar with correlated-double-sampling, double sampled is a kind of reset level using each pixel and additional
The daylighting signal of reset level eliminates noise and the heteropical method in cmos image sensor pixel response.It is " double
Sampling " is first daylighting signal, then reset level, the first reset level of this and " correlated-double-sampling ", then daylighting signal difference,
The two by reset level subtract daylighting signal obtain generate location of pixels real signal value also difference, the difference have come from
The variation of reset level before and after daylighting signal, is also equivalent to the noise of reset level.
One Preferable scheme is that, real signal value be reset level signal and daylighting signal difference.
It is to subtract daylighting signal by reset level signal to obtain therefore no matter double sampled or correlated-double-sampling
To real signal value.
One Preferable scheme is that, the first buffer amplifier circuit include the first amplifying transistor and sampling transistor, first
The source electrode of amplifying transistor and one in drain electrode connect with one in the source electrode of sampling transistor and drain electrode.
Therefore first buffer amplifier circuit be used to the voltage signal of sense voltage node amplifying output.
One Preferable scheme is that, the second buffer amplifier circuit includes that the second amplifying transistor and row select transistor, second
The source electrode of amplifying transistor and one in drain electrode and row select the source electrode of transistor and one in drain electrode to connect.
Therefore second buffer amplifier circuit be used to the voltage signal of storage capacitance node amplifying output.
One Preferable scheme is that, pixel circuit further includes anti-halation reset transistor, the source of anti-halation reset transistor
One in pole and drain electrode connects power end, another connects the cathode of photodiode.
Therefore photodiode can be resetted by anti-halation reset transistor or reset transistor.
To realize above-mentioned another object, cmos image sensor reset noise appraisal procedure provided by the invention, successively
Including, sampling step first, multiple time point sampling reset level signals before and after sampling daylighting signal the step of；Secondly divide
Step is analysed, after having sampled reset level signal, change profile of the analysis reset level in time domain and frequency domain；Last appraisal procedure,
The first real signal value for being obtained by correlated-double-sampling and be multiple by the difference of double sampled the second obtained real signal value
Position noise, the difference of real signal value can be assessed according to the size of reset noise.
By said program as it can be seen that by multiple spot time-domain sampling, the floating disintegration voltage node of pixel before and after daylighting signal
Voltage signal assesses the noise of reset level, to estimate number of the real signal value in " double sampled " and " correlated-double-sampling "
Value difference is different, also for inhibit reset level noise foundation is provided, by assess reset level variation, can quantitatively analyze by
In the influence of noise brought using double sampled mode.
One Preferable scheme is that, appraisal procedure be included in VDD feeding networks place decoupling capacitor the step of.
Therefore at the VDD supply networks near reset transistor, it is properly positioned decoupling capacitor, it can filter
The radio-frequency component of reset noise can reduce the fluctuation of reset level in this way.
One Preferable scheme is that, appraisal procedure includes monitoring step, and monitoring step includes the reset for monitoring pixel circuit
The step of the step of transistor biasing voltage and stable reset transistor bias voltage.
Therefore the variance analysis based on reset level, it can selectively monitor that some CMOS pixels reset crystal
The bias voltage of pipe, and by stablize reset transistor bias voltage so that CMOS pixels before and after daylighting signal time
Reset level variation is minimum.
The pixel circuit of the present invention is operated under double sampled mode, first sampling daylighting signal, re-sampling reset level, and
Two input terminals for remaining to difference channel respectively, to obtain real signal value；And similar other sensors, when being operated in
When under correlated-double-sampling mode, reset level, re-sampling daylighting signal are first sampled；So as to obtain under different working modes
The variation of real signal value, the variation of above-mentioned real signal value are just the fluctuation of reset level, i.e. reset noise；The present invention
A kind of appraisal procedure of reset noise, i.e. multiple time points before and after sampling daylighting signal are proposed, reset signal is sampled, from
And reset noise can be assessed in time domain and frequency domain.When paying attention to assessing noise, cmos image sensor is operated in assessment mode,
At this time neither double sampled mode, nor correlated-double-sampling mode.For convenience's sake, below " real signal value ", double
It obtains being " the second real signal value " under sampling operation mode, and obtains being that " first is real at present in correlated-double-sampling mode
Border signal value ".
Description of the drawings
Fig. 1 is 3T pixel equivalent circuit structure schematic diagrames without storage capacitance and without transmission transistor in the prior art.
Fig. 2 is 4T pixel equivalent circuit structure schematic diagrames without storage capacitance and with transmission transistor in the prior art.
Fig. 3 is in the prior art without storage capacitance and the 5T pixels with transmission transistor and with anti-halation transistor are equivalent
Electrical block diagram.
Fig. 4 is the 6T pixel equivalent circuit structure schematic diagrames for realizing global shutter and correlated-double-sampling in the prior art.
Fig. 5 is the 9T pixel equivalent circuit structure schematic diagrames for realizing global shutter and correlated-double-sampling in the prior art.
Fig. 6 is the structure diagram of cmos image sensor of the present invention.
Fig. 7 is the pixel equivalent circuit structure schematic diagram of cmos image sensor first embodiment of the present invention.
Fig. 8 is the work flow diagram of cmos image sensor of the present invention.
Fig. 9 is the step flow chart of double sampled step S2 in Fig. 8 cmos image sensor work flow diagrams.
Figure 10 is the method flow diagram of cmos image sensor reset noise appraisal procedure embodiment of the present invention.
Figure 11 be cmos image sensor reset noise appraisal procedure embodiment of the present invention sense voltage node level with
Time change schematic diagram.
Figure 12 is the 8T pixel equivalent circuit structure schematic diagrames of cmos image sensor second embodiment of the present invention.
The invention will be further described with reference to the accompanying drawings and embodiments.
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
It is the structure diagram of cmos image sensor of the present invention with reference to Fig. 6, Fig. 6.The imaging sensor of the present invention includes picture
First circuit 1, difference channel 2, analog to digital conversion circuit 3 and memory 4, pixel circuit 1 export daylighting signal and reset level
Signal obtains the difference between daylighting signal and reset level signal to the anode and cathode of difference channel 2 by difference channel 2
Signal, and difference signal is exported to analog to digital conversion circuit 3, analog to digital conversion circuit 3 is to defeated after difference signal progress analog-to-digital conversion
Go out digital signal to memory 4.
It is the pixel equivalent circuit structure schematic diagram of cmos image sensor first embodiment of the present invention with reference to Fig. 7, Fig. 7,
Pixel circuit 1 includes the first buffer amplifier circuit 11 and the second buffer amplifier circuit 12.The pixel circuit of the present invention includes photoelectricity
Diode PPD7, it transmission transistor TX7, reset transistor RST7, the first amplifying transistor DX71, sampling transistor SX71, deposits
Storing up electricity holds Cp7, the second amplifying transistor DX72, row and selects transistor SX72 and low level reset transistor RSTGND7.
First buffer amplifier circuit 11 includes the first amplifying transistor DX71 and sampling transistor SX71, the first amplification crystal
A pole in the source-drain electrode of pipe is connect with the pole in the source-drain electrode of sampling transistor SX71；Second buffer amplifier circuit 12 includes
Second amplifying transistor DX72 and row select transistor SX72, and the pole in the source-drain electrode of the second amplifying transistor DX72 and row choosing are brilliant
Pole connection in the source-drain electrode of body pipe SX72.
Reset transistor RST7 is resetted for being resetted before exposure to photodiode PPD7 by reset signal Vrst
Signal is controlled.
Transmission transistor TX7 works as photodiode for photodiode PPD7 and the first amplifying transistor DX71 to be isolated
PPD7 resets and is closed the influence for reducing noise to sense voltage node FD7 when electric charge transfer.
First amplifying transistor DX71 and the second amplifying transistor DX72 is source follower, is used for handle by two pole of photoelectricity
The charge that pole is tired out in pipe PPD7 is converted to voltage.
Sampling transistor SX71 is used to make storage capacitance electric discharge Cp7 with the RSTGND7 cooperations of low level reset transistor, and
It will be exported from the daylighting signal of the first amplifying transistor DX71.
Storage capacitance Cp7 is for storing daylighting signal.
Row selects the row selects signal of pixel region output signals of the transistor SX72 for being arranged from line direction according to selection
And the voltage from the second amplifying transistor DX72 is exported, the picture signal as a corresponding pixel.
The plus earth of photodiode PPD7, cathode are connected with the source electrode of transmission transistor TX7, transmission transistor TX7
Drain electrode connect respectively with the source electrode of the grid of the first amplifying transistor DX71 and reset transistor RST7, transmission transistor
The drain electrode of TX7 and the connecting node of reset transistor RST7 source electrodes are sense voltage node FD7, the drain electrode of reset transistor RST7
It is connect with power supply.The drain electrode of first amplifying transistor DX71 is connect with power supply, the source electrode source electrode with sampling transistor SX71 respectively
It is connected with the drain electrode of low level reset transistor RSTGND7, the source electrode ground connection of low level reset transistor RSTGND7, sampling is brilliant
The drain electrode of body pipe SX71 is connect with the grid of one end of storage capacitance Cp7 and the second amplifying transistor DX72 respectively, storage capacitance
The other end of Cp7 is grounded, and the drain electrode of the second amplifying transistor DX72 is connect with power supply, and source electrode selects the source electrode of transistor SX72 with row
Connection, row select the drain electrode of transistor SX72 to be connect with column output line.The wherein level V of sense voltage node FD7FDReflect illumination
Signal or reset level are after exposure daylighting signal, are after the reset reset level.It should be noted that the present embodiment
In transistor be NMOS tube, can also replace NMOS tube with PMOS pipes in practical applications.
It is the work flow diagram of the cmos image sensor of the present invention with reference to Fig. 8, Fig. 8.Step S1 is first carried out, passes through biography
The time for exposure of defeated transistor TX7 controls global shutter, step S2 is then executed, progress is double sampled, then executes step S3, will be double
The pixel value that reset level is eliminated after sampling is converted to digital pixel value by analog to digital conversion, finally executes step S4, will be digital
Pixel value is stored in memory 4（SRAM）.
When carrying out global exposure, reset transistor RST7 and transmission transistor TX7 are closed, photodiode PPD7 and quick
Feel voltage node FD7 to reset；Transmission transistor TX7 is disconnected, and overall situation exposure starts；Reset transistor RST7 is disconnected, and transmits crystal
Pipe TX7 closes, and charge transfer starts；Transmission transistor TX7 is disconnected, and overall situation exposure and charge transfer terminate, transmission transistor TX7
The time of exposure can be controlled.
When carrying out double sampled, sampling transistor SX71 and low level reset transistor RSTGND7, which are closed at, makes storage
Capacitance Cp7 is discharged to low level, and low level reset transistor RSTGND7 is disconnected again；Daylighting signal passes through the first amplifying transistor
DX71 carries out Hyblid Buffer Amplifier output, and then sampling transistor SX71 is disconnected, and daylighting signal is stored to storage capacitance Cp7.When line by line
When reading daylighting signal, row selects transistor SX72 to be closed, and the daylighting signal stored in storage capacitance Cp7 is brilliant by the second amplification
Body pipe DX72 Hyblid Buffer Amplifiers export, and are read by column output line.
When reset transistor RST7 is closed, sense voltage node FD7 resets to obtain reset level；It is adopted based on row reading
When optical signal, after the daylighting signal of the row is read, the sampling transistor SX71 and row of the row select transistor SX72 to be closed, and reset
Level exports after the two poles of the earth Hyblid Buffer Amplifier of the first amplifying transistor DX71 and the second amplifying transistor DX72 again by row
Line is read.
After the completion of double sampled, reset level and daylighting signal are subjected to difference operation by difference channel 2, automatically derived
Difference is just a cancellation the real signal value of reset level, then analog-to-digital conversion is carried out by analog to digital conversion circuit 3, after conversion
Digital pixel value be stored in memory 4, when next line daylighting signal and reset level are read, export the data of this line.
The level of above-mentioned storage capacitance Cp7 needs to reset to low level before the input of daylighting signal buffer.By preceding extremely electric
It is realized when the low level reset transistor RSTGND7 conductings on road, storage capacitance Cp7 discharges at this time.Discharge current
（discharging current）Direction from storage capacitance Cp7, through low level reset transistor RSTGND7, be flowed into ground,
The size of discharge current is controlled by the grid voltage of low level reset transistor RSTGND7.Due to the flow direction and electric current of electronics
Flow to exactly the opposite, so when storage capacitance Cp7 resets to low level, electronics is flowed out from ground, passes through low level reset transistor
RSTGND7 reaches storage capacitance Cp7 in pixel.Therefore, storage capacitance Cp7 " electric discharges（discharge）", also referred to as " precharge
（precharge）", " discharge current simultaneously（discharging current）", also referred to as " pre-charge current
（precharging current）".
It is the step flow of double sampled step S2 in cmos image sensor work flow diagram of the present invention with reference to Fig. 9, Fig. 9
Figure.Step S21 is first carried out, it is global to store daylighting signal in storage capacitance Cp7；Then execute step S22, from column output line by
Row reads daylighting signal and is maintained at an input terminal of difference channel；Step S23 is executed again, reset transistor RST7 is closed,
Sense voltage node FD7 resets, and obtains reset level；Step S24 is executed again, reads reset level line by line and is maintained at differential electrical
Another input terminal on road；Step S25 is finally executed, daylighting signal is subtracted with reset level, the difference automatically derived is to disappear
In addition to the real signal value of reset level.
Double sampled (Double Sampling, DS) is a kind of reset level using each pixel and attached multiple
The daylighting signal of bit level eliminates noise and the heteropical method in cmos image sensor pixel response." daylighting is believed
Number " refer to pixel " the daylighting signal that attached reset level ".It uses and double sampled cmos image sensor is obtained
Better signal noise ratio performance.
It is double sampled in order to execute, it needs to reset pixel, then makes the time of pixel exposure predetermined amount, pixel is in incident light
Photon integrated to generate voltage value.Daylighting signal (attached reset level) is first measured, the first sampled value is obtained, then
Pixel is resetted, and measures reset level, obtains the second sampled value, subtracting the first sampling by the second sampled value is worth to pixel position
The real signal value set.
0, Figure 10 is the method flow of cmos image sensor reset noise appraisal procedure embodiment of the present invention referring to Fig.1
Figure.Step A1 is first carried out, the different time point sampling reset level signal before and after daylighting signal the step of；Then step is executed
Rapid A2, after the completion of sampling, change profile of the analysis reset signal in time domain and frequency domain；Step A3 is finally executed, so, according to multiple
Position noise size can assess real signal value two kinds of working method correlated-double-samplings and it is double sampled under difference.
The method of the double sampled reset noise brought of assessment proposed by the present invention, in the difference before and after obtaining daylighting signal
Between point, sampling reset level Vrst（t）, the reset level of record paper having time stamp, then reset electricity in time domain Huo person's Frequency domain analysis
Flat difference, to estimate numerical value difference of the real signal value in " double sampled " and " correlated-double-sampling " working method, assessment
The variation of real signal value.
Figure 11 illustrates the node level V of sense voltage node FD7FDThe schematic diagram changed over time, sense voltage node
The node voltage signal V of FD7FDCan be reset level Vrst or daylighting signal Vsig.The appraisal procedure of the present invention, to sensitivity
The voltage signal V of voltage node FD7FD, daylighting signal prior time point t1, t2, t3 and t4 and later time points t5,
T6, t7 and t8 carry out multi-point sampling respectively, obtain the time-domain sampling value of corresponding time point corresponding reset level.Again in time domain or
Frequency domain analyzes the difference of reset level, assesses the variation of real signal value.
The double sampled and correlated-double-sampling that the imaging sensor of the present invention is realized is different.Correlation based on full frame is double to adopt
Sample first samples reset level Vrst（t）, re-sampling daylighting signal Vsig（t+△t）, wherein △ t are t sampling times point to sampling
Time difference between daylighting signal time point.And it is double sampled based on full frame, it is first to sample daylighting signal Vsig（t+△t）,
Reset level Vrst again（t+△t+△T）, wherein △ T be sample daylighting signal time point to sample reset level time point it
Between time difference.Real signal value is all that reset level subtracts daylighting signal, has cut down the influence of reset level.Based on full frame
Correlated-double-sampling, first real signal value Va=Vrst（t）- Vsig（t+△T）；It is practical based on the double sampled of full frame, second
Signal value Vb=Vrst（t+△t+△T）- Vsig（t+△t）.The difference Va-Vb of first real signal value and the second real signal value
= Vrst（t）- Vrst（t+△t+△T）, the exactly difference of reset level in different time points, that is, reset noise
Variation.
Assess the variation of double sampled reset noise afterwards, the first reality of the second double sampled real signal value and correlated-double-sampling
The difference of border signal value is Vb-Va=Vrst（t+△t+△T）- Vrst（t）, that is, reset level variation, size can
To be assessed.By to Vrst（t）Time-domain sampling, " reset level " of record paper having time stamp then carry out time domain He Frequency
Reset noise is assessed in domain analysis.
By assessing the variation of reset level, the noise brought due to the use of double sampled working method can be quantitatively analyzed
It influences.In addition, placing decoupling capacitor at the VDD supply networks close to reset transistor RST7, it can not only filter reset and make an uproar
The radio-frequency component of sound can also reduce the fluctuation of reset level.And the variance analysis based on reset level, selectively monitors
The reset level of some pixel circuits, and by stablizing the bias voltage of reset transistor RST7 so that pixel circuit is obtaining
The reset level variation of the surrounding time point of daylighting signal is minimum.
Figure 12 is that the cmos image sensor second of the present invention applies the 8T pixel equivalent circuit structure schematic diagrames of example, this implementation
Example in pixel circuit, first embodiment of the invention pixel circuit have transmission transistor TX8, reset transistor RST8,
First amplifying transistor DX81, sampling transistor SX81, storage capacitance Cp8, the second amplifying transistor DX82, row select transistor
On the basis of SX82 and low level reset transistor RSTGND8, the 8T pixel circuits in the present embodiment increase an anti-halation
Reset transistor RSTAB8.Anti-halation transistor RSTAB8 is resetted in photodiode PPD8 and when electric charge transfer is closed, can be with
Reduce influence of the noise to sense voltage node FD8.
Therefore the present invention provides a kind of extensive cmos image sensor of pixel structure concision and compact, this hairs
Bright cmos image sensor reduces the complexity of pixel circuit, occupies less Pixel domain so that in limited face
On long-pending chip, the scale of cmos sensor can be increased, more will leave radioresistance hardness circuit and control signal in space
The design of Circuit with tolerance, to improve the reliability of cmos image sensor and the yield rate of chip;It is provided by the invention simultaneously
Cmos image sensor reset noise appraisal procedure, by estimating that real signal value works in " double sampled " and " correlated-double-sampling "
Numerical value difference when mode, to inhibit the noise of reset level to provide foundation, to assess the variation of reset level, in order to fixed
The influence of noise that the analysis of amount ground brings due to the use of double sampled mode.
Finally it is emphasized that within the scope of the invention, many modifications and variations are all possible.For example, can be with
It is designed using different active pixel cell in cmos image sensors to obtain with global shutter and double sampled, or will
NMOS tube in embodiment is substituted with PMOS tube, these changes are within the scope of the invention.
Claims (8)
1.CMOS imaging sensors, including：Pixel circuit, difference channel, analog to digital conversion circuit and memory, the pixel electricity
Road samples daylighting signal and reset level signal and exports to the difference channel, and pixel is obtained by the difference channel
Real signal value, and the real signal value is exported to analog-digital conversion circuit as described, analog-digital conversion circuit as described is to the reality
Border signal value carries out after analog-to-digital conversion output digit signals to the memory；
It is characterized in that：
Reset level signal described in multiple time point samplings before and after sampling daylighting signal；
The pixel circuit includes photodiode, transmission transistor, reset transistor, storage capacitance, the first Hyblid Buffer Amplifier electricity
Road and the second buffer amplifier circuit；The output end of the transmission transistor is connect with the input terminal of first buffer amplifier circuit
In the node level signal of a node, the node storage capacitance is stored in after the amplification of the first buffer amplifier circuit
In, the amplified node level signal is exported by the second buffer amplifier circuit to column output line；
First buffer amplifier circuit includes the first amplifying transistor and sampling transistor, the source of first amplifying transistor
One in pole and drain electrode connect with one in the source electrode of the sampling transistor and drain electrode；
Second buffer amplifier circuit includes that the second amplifying transistor and row select transistor, the source of second amplifying transistor
Pole and drain electrode in one with the row select transistor source electrode and drain electrode in one connect；
The sampling transistor and the reset transistor, which are closed at, makes the storage discharge of electricity to low level, and the reset is brilliant
Body pipe disconnects again；Daylighting signal carries out Hyblid Buffer Amplifier output by first amplifying transistor, then the sampling transistor
It disconnects, the daylighting signal is stored to the storage capacitance；
When reading the daylighting signal line by line, the row selects transistor to be closed, the daylighting letter stored in the storage capacitance
Number by the second amplifying transistor Hyblid Buffer Amplifier export, read by column output line；
When the reset transistor is closed, sense voltage node reset obtains reset level；Daylighting signal is being read based on row
When, after the daylighting signal of the row is read, the sampling transistor and the row of the row select transistor to be closed, reset level warp
After crossing the two poles of the earth Hyblid Buffer Amplifier of first amplifying transistor and second amplifying transistor, read by column output line.
2. cmos image sensor according to claim 1, it is characterised in that：
The node level signal is the daylighting signal or the reset level signal.
3. cmos image sensor according to claim 2, it is characterised in that：
It attached the reset level signal on the daylighting signal.
4. cmos image sensor according to claim 1, it is characterised in that：
The real signal value is the difference of the reset level signal and the daylighting signal.
5. cmos image sensor according to any one of claims 1 to 4, it is characterised in that：
The pixel circuit further includes anti-halation reset transistor, the source electrode of the anti-halation reset transistor and one in drain electrode
A to connect power end, another connects the cathode of photodiode.
6.CMOS imaging sensor reset noise appraisal procedures, which is characterized in that including：
Sampling step, multiple time point sampling reset level signals before and after sampling daylighting signal；
Analytical procedure, after having sampled reset level signal, change profile of the analysis reset level in time domain and frequency domain；
Appraisal procedure, the change profile of the reset level signal is for assessing reset noise, to quantitatively determine practical letter
The difference of number value, the difference of the real signal value is the first real signal value obtained by correlated-double-sampling and adopted by double
The difference for the second real signal value that sample obtains；
Wherein, the first real signal value Va=Vrst（t）- Vsig（t+△T）；
Wherein, the second real signal value Vb=Vrst（t+△t+△T）- Vsig（t+△t）；
Wherein, first real signal value and the second real signal value are operated in correlated-double-sampling pattern and double sampled mould respectively
Formula；
Wherein, the operating mode when reset noise appraisal procedure is only and adopts at multiple time points before and after sampling daylighting signal
Sample reset level signal；
Wherein, t and t+ △ t+ △ T are respectively reset level time point before and after the sampling, and t+ △ t are the sampling daylighting signal
Time point, △ t are reset level time point before the sampling to the time difference between sampling daylighting signal time point, and △ T are
Time difference after the time point to sampling for sampling daylighting signal between reset level time point, Vrst（t）,Vrst（t+△t+
△T）To sample reset level, Vsig（t+△t）,Vsig（t+△T）To sample daylighting signal.
7. cmos image sensor reset noise appraisal procedure according to claim 6, it is characterised in that：
The appraisal procedure is included in the step of VDD feeding networks place decoupling capacitor.
8. cmos image sensor reset noise appraisal procedure according to claim 6, it is characterised in that：
The appraisal procedure includes monitoring step, and the monitoring step includes the reset transistor bias voltage for monitoring pixel circuit
The step of and stablize reset transistor bias voltage the step of.
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| JP6997720B2 (en) * | 2016-11-24 | 2022-01-18 | ソニーセミコンダクタソリューションズ株式会社 | Solid-state image sensor, solid-state image sensor, and control method for solid-state image sensor |
| KR102684972B1 (en) * | 2016-11-28 | 2024-07-16 | 삼성전자주식회사 | Image sensor |
| CN111093043B (en) * | 2018-10-24 | 2021-10-22 | 宁波飞芯电子科技有限公司 | Radiation receiving system and method and sensing array |
| CN111665268B (en) * | 2020-06-12 | 2023-04-28 | 上海天马微电子有限公司 | Optical signal detection circuit, method and X-ray detector |
| CN114339088B (en) * | 2020-09-30 | 2025-03-28 | 思特威(上海)电子科技股份有限公司 | A TOF image sensor pixel structure and ranging system |
| CN112422955B (en) * | 2020-10-27 | 2022-08-12 | 西安微电子技术研究所 | A kind of ADC inherent noise analysis method for CMOS image sensor |
| CN115150570B (en) * | 2022-09-06 | 2023-04-28 | 武汉加特林光学仪器有限公司 | Double-sampling signal processing circuit based on digital circuit and display panel detection equipment |
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