CN105680831B - Clock and data recovery circuits and systems using the same - Google Patents

Abstract

A clock and data recovery circuit may include: a phase detection unit configured to generate an early phase detection signal and a late phase detection signal by comparing a clock signal and data; a filtering unit configured to generate an upstream signal and a downstream signal based on the number of generation times of the early phase detection signal and the number of generation times of the late phase detection signal; a phase information summing unit configured to receive an output of the filtering unit at each cycle of the clock signal and generate a first phase control signal and a second phase control signal by summing the number of up signals and the number of down signals received from the filtering unit during a summing time; and a phase interpolator configured to adjust a phase of the clock signal according to the first phase control signal and the second phase control signal.

Description

Clock and data recovery circuits and systems using the same

Cross-reference to related applications

This application claims priority to Korean Application No. 10-2014-0174449 filed in the Korean Intellectual Property Office on December 5, 2014, which is incorporated herein by reference in its entirety.

technical field

Various embodiments relate to a semiconductor device, and more particularly, to a clock and data recovery circuit and a system using the same.

Background technique

In general, systems that perform serial data communications over a small number of data buses use clock and data recovery methods. The clock and data recovery method generates a reference clock signal from serial data, and uses the generated clock signal as a strobe signal for receiving data. Therefore, the transmitter can transmit data having information related to the clock signal, and the receiver can generate a clock signal from the data and then receive data from the transmitter in synchronization with the generated clock signal.

To minimize signal distortion caused by noise and jitter and to increase the data valid window, the receiver can compare the phase of the clock signal generated from the data with the transition point of the data and adjust the phase of the clock signal.

SUMMARY OF THE INVENTION

In an embodiment of the present invention, the clock and data recovery circuit may include a phase detection unit configured to generate an early phase detection signal and a late phase detection signal by comparing the clock signal and the data. The clock and data recovery circuit may further include a filtering unit configured to generate the upstream signal and the downstream signal based on the number of times of generation of the early phase detection signal and the number of times of generation of the late phase detection signal. The clock and data recovery circuit may further include a phase information summing unit configured to receive the output of the filtering unit at each cycle of the clock signal, and by summing the upstream received from the filtering unit during the summing time The number of signals and the number of downstream signals to generate the first phase control signal and the second phase control signal, and the summation time is n times greater than the period of the clock signal, where n is an integer equal to or greater than 2. The clock and data recovery circuit may further include a phase interpolator configured to adjust the phase of the clock signal according to the first phase control signal and the second phase control signal.

In an embodiment of the present invention, the clock and data recovery circuit may include a phase detection unit configured to generate an early phase detection signal and a late phase detection signal by comparing the first clock signal and the data. The clock and data recovery circuit may further include a filtering unit configured to generate the uplink signal and the downlink signal according to the number of times of generation of the early phase detection signal and the number of times of generation of the late phase detection signal. The clock and data recovery circuit may further include a phase information summation unit configured to sum the number of times of generation of the uplink signal and the number of times of generation of the downlink signal in synchronization with the first clock signal, and be synchronous with the first clock signal. The summation results are output as the first phase control signal and the second phase control signal in synchronization with the two clock signals. The clock and data recovery circuit may also include a phase interpolator configured to adjust the phase of the first clock signal based on the first phase control signal and the second phase control signal when updated in synchronization with the second clock signal. phase.

In an embodiment, the clock and data recovery circuit may include a phase detection unit configured to receive the clock signal and the data, generate an early phase detection signal when an edge of the clock signal leads a transition point of the data, and at an edge of the clock signal The late phase detection signal is generated when the edge is after the transition point of the data. The clock and data recovery circuit may further include a filtering unit configured to generate the uplink signal and the downlink signal when the difference between the number of times of generation of the early phase detection signal and the number of times of generation of the late phase detection signal reaches a predetermined value one of the. The clock and data recovery circuit may further include a phase information summing unit configured to sum the number of received upstream signals and the number of downstream signals during the summing time, and to generate the first phase control signal and the first phase control signal. Two-phase control signal. The clock and data recovery circuit may further include a phase interpolator configured to receive the first phase control signal and the second phase control signal and adjust the phase of the clock signal.

Description of drawings

FIG. 1 is a diagram showing the configuration of a system according to an embodiment of the present invention;

2 is a diagram showing a configuration of a clock and data recovery circuit according to an embodiment of the present invention;

3A to 3D are diagrams illustrating operations of the phase detection unit of FIG. 2;

FIG. 4 is a block diagram schematically showing the configuration of the phase information summation unit of FIG. 2;

Fig. 5 is a diagram showing the configuration of the upstream signal adder of Fig. 4;

6 is a timing diagram illustrating the operation of the upstream signal adder of FIG. 5;

7 shows a block diagram of a system employing a memory control circuit according to an embodiment of the present invention.

Detailed ways

Hereinafter, a clock and data recovery circuit according to the present invention and a system using the same will be described below through various embodiments with reference to the accompanying drawings. Various embodiments relate to a clock and data recovery circuit capable of acquiring phase information of a clock signal over short periods and adjusting the phase of the clock signal over longer periods.

Referring to FIG. 1, there is shown a diagram illustrating the configuration of a system 1 according to an embodiment of the present invention. In FIG. 1 , system 1 may include transmitter 110 and receiver 120 . The transmitter 110 may refer to a component representing a data transmission side that transmits data. Also, the receiver 120 may refer to a component representing a data receiving side that receives data from the transmitter 110 . For example, system 1 may include a master device and a slave device. When data is transmitted from the master device to the slave device, the master device may be set as the transmitter 110 . Also, the slave device may be set as the receiver 120 . On the other hand, when data is transmitted from the slave device to the master device, the master device may be set as the receiver 120 . Also, the slave device may be set as the transmitter 110 .

Transmitter 110 and receiver 120 forming system 1 may communicate with each other by serial data transmission methods using a small number of data buses. Referring to FIG. 1 , the transmitter 110 may include a data encoder 111 . The receiver 120 may include a clock and data recovery circuit (CDR) 121 and a data decoder 122 . The transmitter 110 may be electrically coupled to the receiver 120 through a plurality of data buses 131 , 132 and 133 . FIG. 1 shows the use of three data buses 131 , 132 and 133 . However, the present invention is not limited to this. The transmitter 110 may generate data D1 , D2 and D3 by encoding the internal data via the data encoder 111 . The data D1 , D2 and D3 may be serially transmitted through the data buses 131 , 132 and 133 in sequence. The data D1 , D2 and D3 may indicate data transmitted through the data buses 131 , 132 and 133 . Also, the internal data may indicate data used in the transmitter 110 or the receiver 120 .

The clock and data recovery circuit 121 of the receiver 120 may generate the clock signal CLK from the data transmitted through the data buses 131 , 132 and 133 . The clock signal CLK can be used as a strobe signal. Also, the receiver 120 may receive the data D1 , D2 and D3 transmitted through the data buses 131 , 132 and 133 in synchronization with the clock signal CLK. The data decoder 122 may convert the data D1, D2 and D3 transmitted through the data buses 131, 132 and 133 into internal data. The data encoder 111 and the data decoder 122 may include conversion tables for converting the internal data into the data D1, D2 and D3 or converting the data D1, D2 and D3 into the internal data.

The clock and data recovery circuit 121 may generate a clock signal from the data D1, D2 and D3, and adjust the phase of the clock signal CLK by comparing the clock signal CLK with the data D1, D2 and D3.

2, there is shown a diagram illustrating the configuration of the clock and data recovery circuit 2 according to the embodiment of the present invention. In FIG. 2 , the clock and data recovery circuit 2 may include a phase detection unit 210 , a filtering unit 220 , a phase information summation unit 230 and a phase interpolator 240 . The phase detection unit 210 may receive the clock signal CLK and data DATA. The phase detection unit 210 may also compare the clock signal CLK and the data DATA at each cycle of the clock signal CLK. For example, the phase detection unit 210 may detect whether the edge of the clock signal CLK leads or lags the transition point of the data DATA. The phase detection unit 210 may compare the clock signal CLK and the data DATA. The phase detection unit 210 may also generate an early phase detection signal ER and a late phase detection signal LT. For example, the phase detection unit 210 may generate the early phase detection signal ER when the edge of the clock signal CLK leads the transition point of the data DATA. Also, the phase detection unit 210 may generate the late phase detection signal LT when the edge of the clock signal CLK lags behind the transition point of the data DATA. Specific operations of the phase detection unit 210 will be described below.

The filtering unit 220 may receive the early phase detection signal ER and the late phase detection signal LT from the phase detection unit 210 . The filtering unit 220 can also generate an uplink signal UP and a downlink signal DN. The filtering unit 220 may be based on how many times the early phase detection signal ER is generated (hereinafter, referred to as the number of times of generation of the early phase detection signal ER) and how many times the late phase detection signal LT is generated (hereinafter, referred to as late phase detection). The number of times the signal LT is generated) to generate the upstream signal UP and the downstream signal DN. The filtering unit 220 may generate one of the uplink signal UP and the downlink signal DN when the difference between the number of times of generation of the early phase detection signal ER and the number of times of generation of the late phase detection signal LT reaches a predetermined value. The predetermined value may correspond to the filtering depth of the filtering unit 220 . For example, when the filtering depth is set to 3, the filtering unit 220 may generate the downlink signal DN in which the number of times of generation of the early phase detection signal ER is three greater than the number of times of generation of the late phase detection signal LT. In addition, the filtering unit 220 may generate the uplink signal UP, wherein the number of times of generation of the late phase detection signal LT is three larger than the number of times of generation of the early phase detection signal ER. In an embodiment, the filtering unit 220 may comprise a moving average filter.

The phase information summing unit 230 may receive the output signal of the filtering unit 220 at each cycle of the clock signal CLK. The phase information summing unit 230 may also sum the number of the uplink signals UP and the number of the downlink signals DN received from the filtering unit 220 during a time n times the period of the clock signal CLK. At this time, n may indicate an integer equal to or greater than 2. In an embodiment, n may correspond to the filtering depth of the filtering unit 220, but is not limited thereto. A time n times the period of the clock signal CLK may be set as the summation time. The phase information summing unit 230 may sum the number of received uplink signals UP and the number of downlink signals DN during the summing time. The phase information summation unit 230 also generates a first phase control signal MAFUP<0:m> and a second phase control signal MAFDN<0:m>, respectively. For example, the phase information summation unit 230 may change the logical value of the first phase control signal MAFUP<0:m> according to the summed number of the uplink signals UP. In addition, the phase information summation unit 230 may also change the logic value of the second phase control signal MAFDN<0:m> according to the summed number of the downlink signals DN. The first phase control signal MAFUP<0:m> may have information for delaying the phase of the clock signal CLK. Also, the second phase control signal MAFDN<0:m> may have information for advancing the phase of the clock signal CLK.

The phase information summing unit 230 may receive the upstream signal UP or the downstream signal DN output from the filtering unit 220 in synchronization with the clock signal CLK. The phase information summing unit 230 may also output the first phase control signal MAFUP<0:m> and the second phase control signal MAFDN<0 in synchronization with the clock signal CLK/n having a period n times the period of the clock signal CLK :m>. Hereinafter, the clock signal CLK will be referred to as the first clock signal. Also, the clock signal CLK/n having a period n times the period of the clock signal CLK will be referred to as a second clock signal. More specifically, the second clock signal CLK/n may have a frequency that is 1/n of the frequency of the first clock signal CLK.

The phase interpolator 240 may receive the first phase control signal MAFUP<0:m> and the second phase control signal MAFDN<0:m> from the phase information summing unit 230 . The phase interpolator 240 may adjust the phase of the clock signal CLK based on the first phase control signal MAFUP<0:m> and the second phase control signal MAFDN<0:m>. The phase interpolator 240 may receive the second clock signal CLK/n to synchronize time points at which the first phase control signal MAFUP<0:m> and the second phase control signal MAFDN<0:m> are received. Therefore, the phase interpolator 240 can be updated in synchronization with the second clock signal CLK/n. The phase interpolator 240 may further adjust the phase of the clock signal CLK at each period of the second clock signal CLK/n based on the first phase control signal MAFUP<0:m> and the second phase control signal MAFDN<0:m> .

Although not shown, the phase interpolator 240 may include a plurality of unit delay units. The phase interpolator 240 can also adjust the phase of the clock signal CLK by controlling the number of the unit delay units, the unit delay units changing according to the first phase control signal MAFUP<0:m> and the second phase control signal MAFDN<0:m> connected. The phase interpolator 240 may turn on or off one unit delay unit at a time, or turn on or off two units according to the first phase control signal MAFUP<0:m> and the second phase control signal MAFDN<0:m>. one or more unit delay units. More specifically, the phase interpolator 240 may change the phase adjustment of the clock signal based on the first phase control signal MAFUP<0:m> and the second phase control signal MAFDN<0:m>.

The phase detection unit 210 may generate the early phase detection signal ER and the late phase detection signal LT at each cycle of the clock signal CLK. The filtering unit 220 may count the number of times of generation of the early phase detection signal ER and the late phase detection signal LT generated in each cycle of the clock signal CLK. When the early phase detection signal ER and the late phase detection signal LT are alternately generated, the time when the difference between the number of times of generation of the early phase detection signal ER and the number of times of generation of the late phase detection signal LT reaches the filter depth cannot be determined. Therefore, the components electrically coupled behind the filtering unit 220 need to check whether the upstream signal UP or the downstream signal DN is generated from the filtering unit 220 at each cycle of the clock signal CLK. At this time, the phase information summation unit 230 may receive the uplink signal UP and the downlink signal DN generated from the filtering unit 220 in synchronization with the clock signal CLK. The phase information summing unit 230 may also sum the numbers of the up signal UP and down signal DN received during the time corresponding to the period of the second clock signal CLK/n. The phase information summing unit 230 may also provide the summation results as the first phase control signal MAFUP<0:m> and the second phase control signal MAFDN<0:m> in synchronization with the second clock signal CLK/n. Therefore, the phase interpolator 240 can be updated every period of the second clock signal CLK/n, and the power consumption of the phase interpolator 240 can be reduced. When the phase information summing unit 230 does not exist, the phase interpolator 240 must receive the up signal UP and the down signal DN at each clock signal CLK. Then, when the update period becomes shorter, a large amount of power must be consumed. Furthermore, the phase information summing unit 230 can make the filtering unit stably function as a low-pass filter even if the filtering unit 220 is a moving average filter.

3A to 3D, diagrams illustrating the operation of the phase detection unit 210 of FIG. 2 are described. The phase detection unit 210 may compare the clock signal CLK and the data DATA, and generate an early phase detection signal ER and a late phase detection signal LT. The phase detection unit 210 may capture the level of the data DATA at phases corresponding to 0 degrees, 90 degrees, 180 degrees and 270 degrees of the clock signal CLK during one cycle of the clock signal CLK. For this operation, the phase detection unit 210 may use the divided clock signal obtained by dividing the clock signal CLK, and capture the level of the data DATA at the rising edge of the divided clock signal. The divided clock signal may be generated by the phase interpolator 240 and divided by the phase detection unit 210 . In FIGS. 3A to 3C , the divided clock signal CLKI may have the same phase as the clock signal CLK. Also, the divided clock signal CLKQ may have a phase delayed by 90 degrees from the clock signal CLK. Also, the divided clock signal CLKIB may have a phase delayed by 180 degrees from the clock signal CLK, and the divided clock signal CLKQB may have a phase delayed by 270 degrees from the clock signal CLK.

FIG. 3A shows a case where the phase of the clock signal CLK does not need to be adjusted, that is, a locked state. In the locked state, rising edges of the divided clock signals CLKI and CLKIB may be located at transition points A of the data DATA, respectively. Rising edges of the divided clock signals CLKQ and CLKQB may be located at the centers of valid intervals of data DATA, respectively. The phase detection unit 210 may perform operations on the levels of the data DATA captured at the rising edges of the divided clock signals CLKI, CLKQ, CLKIB and CLKQB. The phase detection unit 210 may also generate an early phase detection signal EQ and a late phase detection signal LT. The phase detection unit 210 may perform an exclusive-OR (XOR) operation on the level of the data DATA captured by the divided clock signal CLKI and the level of the data DATA captured by the divided clock signal CLKQ. In addition, the phase detection unit 210 may also perform an XOR operation on the level of the data DATA captured by the divided clock signal CLKQ and the level of the data DATA captured by the divided clock signal CLKIB. The phase detection unit 210 may generate an early phase detection signal ER and a late phase detection signal LT based on the XOR operation result. As shown in FIG. 3B , when the XOR operation result is 0 because the levels I and Q of the data captured by the divided clock signals CLKI and CLKQ are equal to each other, and the XOR operation result is When the levels Q and IB of the data are different from each other and are 1, the phase detection unit 210 may determine that the phase of the edge of the clock signal CLK lags behind the transition point of the data DATA. Then, the phase detection unit 210 may generate the late phase detection signal LT. On the other hand, when the XOR operation result is 1 due to the levels I and Q of the data captured by the divided clock signals CLKI and CLKQ being different from each other, and the XOR operation result is 1 due to the electric level of the data captured by the divided clock signals CLKQ and CLKIB, When the flat Q and IB are equal to each other to be 0, the phase detection unit 210 may determine that the phase of the edge of the clock signal CLK is ahead of the transition point of the data DATA. Then, the phase detection unit 210 may generate an early phase detection signal ER. In other cases than the two above-mentioned cases, the phase detection unit 210 may not generate both the early phase detection signal ER and the late phase detection signal LT.

FIG. 3C shows a case where the phase of the edge of the clock signal CLK lags behind the transition point of the data DATA. When the data DATA is toggled, the levels I and Q of the data captured by the divided clock signals CLKI and CLKQ may be equal to each other. Also, the levels Q and IB of data captured by the divided clock signals CLKQ and CLKIB may be different from each other. Therefore, in the case of FIG. 3C , the phase detection unit 210 can generate the late phase detection signal LT. Referring to FIG. 3D, a case is shown in which the phase of the edge of the clock signal CLK leads the transition time of the data DATA. The levels I and Q of data captured by the divided clock signals CLKI and CLKQ may be different from each other. Also, the levels Q and IB of data captured by the divided clock signals CLKQ and CLKIB may be equal to each other. Therefore, in FIG. 3D, the phase detection unit 210 may generate the early phase detection signal ER.

Referring to FIG. 4 , there is shown a block diagram schematically showing the configuration of the phase information summing unit 230 of FIG. 2 . In FIG. 4 , the phase information summation unit 230 may include an uplink signal adder 410 and a downlink signal adder 420 . The up signal adder 410 may receive the up signal UP, the clock signal CLK and the second clock signal CLK/n output from the filtering unit 220 . The uplink signal adder 410 may also generate the first phase control signal MAFUP<0:m>. The up signal adder 410 may sum the number of input up signals UP during the summing time and output the summation result. The up signal adder 410 may receive the up signal UP at each cycle of the clock signal CLK. The up signal adder 410 may also output information corresponding to the number of up signals UP summed at each cycle of the second clock signal CLK/n as the first phase control signal MAFUP<0:m>. The up signal adder 410 may output the number of up signals UP summed during the summing time as a multi-bit binary code.

The downlink signal adder 420 may receive the downlink signal DN, the clock signal CLK and the second clock signal CLK/n output from the filtering unit 220 . The downlink signal adder 420 may also generate second phase control signals MAFDN<0:m>. The down signal adder 420 may sum the number of input up signals UP during the summing time, and output the summation result. The downstream signal adder 420 may receive the downstream signal DN at each cycle of the clock signal CLK, and output information corresponding to the number of the downstream signals DN summed at each cycle of the second clock signal CLK/n as the second phase Control signals MAFDN<0:m>. The downlink signal adder 420 may output the number of downlink signals DN summed during the summing time as a multi-bit binary code.

Referring to FIG. 5, there is shown a diagram in which the configuration of the uplink signal adder 410 of FIG. 4 is shown. In FIG. 5 , the uplink signal adder 410 may include an XOR gate 501 , an AND gate 503 , and a first flip-flop 511 , a second flip-flop 513 and a third flip-flop 515 . The XOR gate 501 may receive the up signal UP and the output of the first flip-flop 511 and generate a summation signal SUMUP. The AND gate 503 may receive the up signal UP and the output of the first flip-flop 511, and generate a carry signal (carry signal) CARRYUP. The first flip-flop 511 may receive the summation signal SUMUP and the clock signal CLK, and generate a delayed summation signal SUMUPD. The second flip-flop 513 may receive the summation signal SUMUP and the second clock signal CLK/4. The second flip-flop 513 may also generate the LSB MAFUP<0> of the first phase control signal. The third flip-flop 515 may receive the carry signal CARRYUP and the second clock signal CLK/4. The third flip-flop 515 may also generate the MSB MAFUP<1> of the first phase control signal. FIG. 5 shows a configuration in which n is set to 4 and the up signal adder 410 sums two up signals UP during the summing time. However, the uplink signal summer 410 may be adapted to sum a larger number of uplink signals UP using the method described above, or other components may be added to the uplink signal summer 410 . The difference between the downstream signal adder 420 and the upstream signal adder 410 is only that the downstream signal adder 420 receives the downstream signal DN instead of the upstream signal UP. More specifically, the upstream signal adder 420 may have substantially the same configuration as the upstream signal adder 410 .

Referring to FIG. 6, a timing diagram in which the operation of the upstream signal adder 410 of FIG. 5 is shown is shown. In FIG. 6, it is assumed that two up signals UP are input during the summing time (ie, the period of the second clock signal CLK/n). When the first uplink signal UP1 is input, the XOR gate 501 may output a high-level summation signal SUMUP. In addition, the AND gate 503 may output a low-level carry signal CARRYUP. The summation signal SUMUP may be delayed by the period of the clock signal CLK through the first flip-flop 511 and output as the delayed summation signal SUMUP. When the second up signal UP2 is input, the XOR gate 501 may output a low-level summation signal SUMUP. In addition, the AND gate 503 may output a high-level carry signal CARRYUP. The second flip-flop 513 may output a low-level summation signal SUMUP as the LSB MAFUP<0> of the first phase control signal in response to the second clock signal CLK/n. Also, the third flip-flop 515 may output a high-level carry signal CARRYUP as the MSB MAFUP<1> of the first phase control signal in response to the second clock signal CLK/n. Therefore, the first phase control signal MAFUP<0:1> may have a logic value of 1 or 0 and have information indicating that the uplink signal UP is generated twice during the summing time.

Because the filtering unit 220 receives the early phase detection signal ER and the late phase detection signal LT output from the phase detection unit 210 at each cycle of the clock signal CLK, and performs operations on the received signals, the filtering unit 220 can operate within a relatively short period of time. Period to obtain phase information. Even if the phase detecting unit 210 and the filtering unit 220 obtain phase information during a short period, the phase information summing unit 230 may sum the phase information obtained during a relatively long period. The phase interpolator 240 may be updated based on the phase information summed over each relatively long period. Therefore, the power consumption of the clock and data recovery circuit 2 and the power consumption of the system 1 using the clock and data recovery circuit 2 can be effectively reduced.

Referring to FIG. 7 , system 1000 may include one or more processors 1100 . Processor 1100 may be used alone or in combination with other processors. Chipset 1150 may be electrically coupled to processor 1100 . Chipset 1150 is the communication path for signals between processor 1100 and other components of system 1000 . Other components may include memory controller 1200 , input/output (“I/O”) bus 1250 , and disk drive controller 1300 . Depending on the configuration of system 1000, any of several different signals may be transmitted through chipset 1150.

The memory controller 1200 may be electrically coupled to the chipset 1150 . The memory controller 1200 may receive a request provided from the processor 1100 through the chipset 1150 . The memory controller 1200 may be electrically coupled to one or more memory devices 1350 . The memory device 1350 may include the clock and data recovery circuits described above.

Chipset 1150 may also be electrically coupled to I/O bus 1250 . I/O bus 1250 may serve as a communication path for signals from chipset 1150 to I/O devices 1410 , 1420 and 1430 . I/O devices 1410 , 1420 and 1430 may include mouse 1410 , video display 1420 or keyboard 1430 . I/O bus 1250 may employ any of several communication protocols to communicate with I/O devices 1410 , 1420 and 1430 .

The disk drive controller 1300 may also be electrically coupled to the chipset 1150 . Disk drive controller 1300 may serve as a communication path between chipset 1150 and one or more internal disk drives 1450 . Disk drive controller 1300 and internal disk drive 1450 may communicate with each other or with chipset 1150 using virtually any type of communication protocol.

While certain embodiments have been described above, those skilled in the art will appreciate that the embodiments have been described by way of example only. Therefore, the clock and data recovery circuit should not be limited based on the described embodiments. Rather, the clock and data recovery circuit should be limited only by the appended claims when taken in conjunction with the above description and accompanying drawings.

It can be seen from the above embodiments that the present application can provide the following technical solutions.

Technical solution 1. A clock and data recovery circuit, comprising:

a phase detection unit configured to generate an early phase detection signal and a late phase detection signal by comparing the clock signal and the data;

a filtering unit configured to generate an uplink signal and a downlink signal based on the number of times of generation of the early phase detection signal and the number of times of generation of the late phase detection signal;

a phase information summing unit configured to receive the output of the filtering unit at each cycle of the clock signal and to generate the first phase by summing the number of upstream signals and the number of downstream signals received from the filtering unit during the summing time the control signal and the second phase control signal, the summation time is n times greater than the period of the clock signal, wherein n is an integer equal to or greater than 2; and

A phase interpolator configured to adjust the phase of the clock according to the first phase control signal and the second phase control signal.

Technical solution 2. The clock and data recovery circuit according to technical solution 1, wherein the phase detection unit captures the level of the data at the rising edge of the divided clock signal obtained by dividing the clock signal, and responds to the captured level. Operations are performed to generate an early phase detection signal and a late phase detection signal.

Technical solution 3. The clock and data recovery circuit according to technical solution 1, wherein when the difference between the number of times of generation of the early phase detection signal and the number of times of generation of the late phase detection signal reaches a predetermined value, the filtering unit One of an uplink signal and a downlink signal is generated.

Technical solution 4. The clock and data recovery circuit according to technical solution 1, wherein the filtering unit includes a moving average filter.

Technical solution 5. The clock and data recovery circuit according to technical solution 1, wherein the phase information summation unit comprises:

an upstream signal adder configured to sum the number of upstream signals output from the filtering unit during the summing time and output a first phase control signal; and

A downlink signal adder configured to sum the number of downlink signals output from the filtering unit during the summing time and output a second phase control signal.

Technical solution 6. The clock and data recovery circuit according to technical solution 5, wherein the upward signal adder detects whether the upward signal is output in each cycle of the clock signal, and will sum the number of upward signals during the summing time The output is a multi-bit binary code.

Technical solution 7. The clock and data recovery circuit according to technical solution 5, wherein the downlink signal adder detects whether a downlink signal is output in each cycle of the clock signal, and will sum the number of downlink signals during the summing time The output is a multi-bit binary code.

Technical solution 8. A clock and data recovery circuit, comprising:

a phase detection unit configured to generate an early phase detection signal and a late phase detection signal by comparing the first clock signal and the data;

a filtering unit, configured to generate an uplink signal and a downlink signal according to the number of times of generation of the early phase detection signal and the number of times of generation of the late phase detection signal;

a phase information summation unit configured to sum the number of times of generation of the uplink signal and the number of times of generation of the downlink signal in synchronization with the first clock signal, and output the summation result as the first phase in synchronization with the second clock signal a control signal and a second phase control signal; and

A phase interpolator configured to adjust the phase of the first clock signal according to the first phase control signal and the second phase control signal when updated in synchronization with the second clock signal.

Technical solution 9. The clock and data recovery circuit according to technical solution 8, wherein the period of the second clock signal is n times larger than the period of the first clock signal, wherein n is an integer equal to or greater than 2.

Technical solution 10. The clock and data recovery circuit according to technical solution 8, wherein the phase detection unit captures the level of the data at the rising edge of the divided clock signal obtained by dividing the first clock signal, and compares the captured level performs operations to generate an early phase detection signal and a late phase detection signal.

Technical solution 11. The clock and data recovery circuit according to technical solution 8, wherein when the difference between the number of times of generation of the early phase detection signal and the number of times of generation of the late phase detection signal reaches a predetermined value, the filtering unit One of an uplink signal and a downlink signal is generated.

Technical solution 12. The clock and data recovery circuit according to technical solution 8, wherein the filtering unit includes a moving average filter.

Technical solution 13. The clock and data recovery circuit according to technical solution 8, wherein the phase information summation unit comprises:

an upstream signal adder configured to sum the number of upstream signals output from the filtering unit during a time period corresponding to a period of the second clock signal, and output the summation result; and

A downlink signal adder configured to sum the number of downlink signals output from the filtering unit during a time period corresponding to a period of the second clock signal, and output a summation result.

Technical solution 14. The clock and data recovery circuit according to technical solution 13, wherein the uplink signal adder detects whether the uplink signal is output in each cycle of the first clock signal, and will be in the cycle corresponding to the second clock signal. The number of uplink signals summed during the time period is output as a multi-bit binary code.

Technical solution 15. The clock and data recovery circuit according to technical solution 13, wherein the downlink signal adder detects whether the downlink signal is output in each cycle of the first clock signal, and will be in the cycle corresponding to the second clock signal. The number of downlink signals summed during the time period is output as a multi-bit binary code.

Technical solution 16. A clock and data recovery circuit, comprising:

a phase detection unit configured to receive the clock signal and the data, generate an early phase detection signal when an edge of the clock signal leads a transition point of the data, and generate a late phase detection signal when an edge of the clock signal is after the transition point of the data;

a filtering unit configured to generate one of an uplink signal and a downlink signal when the difference between the number of times of generation of the early phase detection signal and the number of times of generation of the late phase detection signal reaches a predetermined value;

a phase information summing unit configured to sum the number of upstream signals and the number of downstream signals received during the summing time, and generate a first phase control signal and a second phase control signal; and

A phase interpolator configured to receive the first phase control signal and the second phase control signal and adjust the phase of the clock signal.

Technical solution 17. The clock and data recovery circuit according to technical solution 16, wherein the phase interpolator is configured to synchronize time points at which the first phase control signal and the second phase control signal are received.

Technical solution 18. The clock and data recovery circuit according to technical solution 16, wherein the phase interpolator is configured to change the phase adjustment of the clock signal according to the first phase control signal and the second phase control signal.

Technical solution 19. The clock and data recovery circuit according to technical solution 16, wherein the phase detection unit is configured to generate an early phase detection signal and a late phase detection signal in each cycle of the clock signal.

Technical solution 20. The clock and data recovery circuit according to technical solution 16, wherein the filtering unit is configured to count the number of times of generation of the early phase detection signal and the late phase detection signal generated in each cycle of the clock signal.

Claims (20)

1. A clock and data recovery circuit comprising:

a phase detection unit configured to generate an early phase detection signal and a late phase detection signal by comparing a clock signal and data;

a filtering unit configured to generate an upstream signal and a downstream signal based on the number of generation times of the early phase detection signal and the number of generation times of the late phase detection signal;

a phase information summing unit configured to receive an output of the filtering unit at each cycle of the clock signal and generate a first phase control signal and a second phase control signal by summing the number of up signals and the number of down signals received from the filtering unit during a summing time that is n times as large as the cycle of the clock signal, where n is an integer equal to or greater than 2; and

a phase interpolator configured to adjust a phase of the clock according to the first phase control signal and the second phase control signal.

2. The clock and data recovery circuit of claim 1, wherein the phase detection unit captures a level of the data at a rising edge of the divided clock signal obtained by dividing the clock signal, and performs an exclusive-or operation on the captured level to generate the early phase detection signal and the late phase detection signal.

3. The clock and data recovery circuit of claim 1, wherein the filtering unit generates one of the up signal and the down signal when a difference between the number of generation times of the early phase detection signal and the number of generation times of the late phase detection signal reaches a predetermined value.

4. The clock and data recovery circuit of claim 1, wherein the filtering unit comprises a moving average filter.

5. The clock and data recovery circuit of claim 1, wherein the phase information summing unit comprises:

an up signal adder configured to sum the number of up signals output from the filtering unit during a summation time and output a first phase control signal; and

a down signal adder configured to sum the number of down signals output from the filtering unit during a summation time and output a second phase control signal.

6. The clock and data recovery circuit of claim 5, wherein the up signal adder detects whether the up signal is output at each cycle of the clock signal and outputs the number of the up signals summed during the summation time as a multi-bit binary code.

7. The clock and data recovery circuit of claim 5, wherein the downstream signal adder detects whether the downstream signal is output at each cycle of the clock signal and outputs the number of downstream signals summed during the summation time as a multi-bit binary code.

8. A clock and data recovery circuit comprising:

a phase detection unit configured to generate an early phase detection signal and a late phase detection signal by comparing a first clock signal and data;

a filtering unit configured to generate an upstream signal and a downstream signal according to the number of generation times of the early phase detection signal and the number of generation times of the late phase detection signal;

a phase information summing unit configured to sum the number of generation times of the up signal and the number of generation times of the down signal in synchronization with the first clock signal and output a result of the summation as a first phase control signal and a second phase control signal in synchronization with the second clock signal; and

a phase interpolator configured to adjust a phase of the first clock signal according to the first phase control signal and the second phase control signal when updated in synchronization with the second clock signal.

9. The clock and data recovery circuit of claim 8, wherein a period of the second clock signal is n times greater than a period of the first clock signal, wherein n is an integer equal to or greater than 2.

10. The clock and data recovery circuit of claim 8, wherein the phase detection unit captures a level of the data at a rising edge of the divided clock signal obtained by dividing the first clock signal, and performs an exclusive-or operation on the captured level to generate the early phase detection signal and the late phase detection signal.

11. The clock and data recovery circuit of claim 8, wherein the filtering unit generates one of the up signal and the down signal when a difference between the number of generation times of the early phase detection signal and the number of generation times of the late phase detection signal reaches a predetermined value.

12. The clock and data recovery circuit of claim 8, wherein the filtering unit comprises a moving average filter.

13. The clock and data recovery circuit of claim 8, wherein the phase information summing unit comprises:

an up signal adder configured to sum the number of up signals output from the filtering unit during a time corresponding to a period of the second clock signal and output a sum result; and

a downstream signal adder configured to sum the number of downstream signals output from the filtering unit during a time corresponding to a period of the second clock signal and output a sum result.

14. The clock and data recovery circuit of claim 13, wherein the up signal adder detects whether the up signal is output at each cycle of the first clock signal and outputs the number of up signals summed during a time corresponding to a cycle of the second clock signal as the multi-bit binary code.

15. The clock and data recovery circuit of claim 13, wherein the downstream signal adder detects whether the downstream signal is output at each cycle of the first clock signal, and outputs the number of downstream signals summed during a time corresponding to a cycle of the second clock signal as the multi-bit binary code.

16. A clock and data recovery circuit comprising:

a phase detection unit configured to receive a clock signal and data, generate an early phase detection signal when an edge of the clock signal leads a transition point of the data, and generate a late phase detection signal when the edge of the clock signal is after the transition point of the data;

a filtering unit configured to generate one of an up signal and a down signal when a difference between the number of generation times of the early phase detection signal and the number of generation times of the late phase detection signal reaches a predetermined value;

a phase information summing unit configured to sum the number of received uplink signals and the number of received downlink signals during a summing time and generate a first phase control signal and a second phase control signal; and

a phase interpolator configured to receive the first phase control signal and the second phase control signal and adjust a phase of the clock signal.

17. The clock and data recovery circuit of claim 16, wherein the phase interpolator is configured to synchronize points in time at which the first phase control signal and the second phase control signal are received.

18. The clock and data recovery circuit of claim 16, wherein the phase interpolator is configured to change the phase adjustment of the clock signal according to the first phase control signal and the second phase control signal.

19. The clock and data recovery circuit of claim 16, wherein the phase detection unit is configured to generate the early phase detection signal and the late phase detection signal at each cycle of the clock signal.

20. The clock and data recovery circuit of claim 16, wherein the filtering unit is configured to count the number of generation times of the early phase detection signal and the late phase detection signal generated at each cycle of the clock signal.

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