CN105677956B - A kind of insertion method of chip buffers - Google Patents
A kind of insertion method of chip buffers Download PDFInfo
- Publication number
- CN105677956B CN105677956B CN201511032830.3A CN201511032830A CN105677956B CN 105677956 B CN105677956 B CN 105677956B CN 201511032830 A CN201511032830 A CN 201511032830A CN 105677956 B CN105677956 B CN 105677956B
- Authority
- CN
- China
- Prior art keywords
- cell
- chip
- buffer
- door
- vertex
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Architecture (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The present invention relates to be related to technical field of integrated circuits more particularly to a kind of insertion method of chip buffers, which comprises chip described in blocking, to form the cell of several equalizations on the chip；Each in all doors being located on chip mobile range is determined respectively；Based on each mobile range, under conditions of meeting each cell and at most being covered by a door or a buffer, the quantity that may be inserted into the buffer in the chip is determined.The present invention is by by chip unit, after mobile range each of on determining chip, the quantity of pluggable buffer in the chip can be determined according to each mobile range, to, not only optimize the layout of chip, the quantity that can be inserted into the buffer area of buffer on chip is improved, the interconnection delay of chip is also reduced.
Description
Technical field
The present invention relates to technical field of integrated circuits more particularly to a kind of insertion methods of chip buffers.
Background technique
Gate on chip is the door of the control on metal-oxide-semiconductor (Metal Oxide Semiconductor).In general, core
Multiple doors can be distributed on piece, have certain distance between Men Yumen, when needs place buffer between two doors
(buffer), when still, not having enough positions between two doors, buffer can only be moved to other can accommodate the buffering
The region of device.As shown in Figure 1, it is assumed that need to be inserted into a buffer, still, gate7 and gate8 between gate7 and gate8
Between there is no sufficiently large position to place buffer, buffer can only be moved between gate2 and gate3 and be placed.So
And during mobile cushioning device, it will increase wire length, when wire length is excessive, will increase the interconnection delay on chip.
In conclusion according to above-mentioned Buffer Insertion method in the prior art, the buffer that not only can be inserted on chip
Limited amount, moreover, be easy to causeing total wire length of buffer area excessive during mobile cushioning device, thus increased core on piece
Interconnection delay, reduce the efficiency of Buffer Insertion.
Summary of the invention
The present invention solves what the prior art can be inserted on chip by providing a kind of insertion method of chip buffers
The limited amount of buffer, and the too long technology of the excessive caused chip interconnection delay of wire length is asked in buffer moving process
Topic.
The embodiment of the invention provides a kind of insertion methods of chip buffers, which comprises
Chip described in blocking, to form the cell of several equalizations on the chip；
Each in all doors being located on chip mobile range is determined respectively；
Based on each mobile range, meeting each cell at most by a door or one
Under conditions of buffer covering, the quantity that may be inserted into the buffer in the chip is determined.
Optionally, each mobile range is determined, specifically:
According to the height and width of each door initial position on the chip and the chip, each door is determined
The chip both vertically and horizontally on mobile range.
Optionally, the door on the chip or the buffer are distributed line by line.
Optionally, a door at least covers the cell, and a buffer at least covers an institute
State cell.
Optionally, when the cell described in the cell or one group is covered by the door, a cell
Vertex or one group described in the vertex of cell be overlapped with the vertex of the door；
When the cell described in the cell or one group is covered by the buffer, the top of a cell
The vertex of point or cell described in one group is overlapped with the vertex of the buffer.
Optionally, described based on each mobile range, meeting each cell at most by one
Under conditions of the door or a buffer covering, the quantity that may be inserted into the buffer in the chip is determined, specifically
Include:
According to integral linear programming, following equation group is constructed:
Objective function:
Wherein, γi,jFor indicating whether door is placed in the cell that apex coordinate is (i, j), βi,jFor indicating
Whether buffer is placed in the cell that apex coordinate is (i, j), when door is placed on the unit that apex coordinate is (i, j)
In lattice, then γi,jIt is 1, otherwise γi,jIt is 0, when buffer is placed in the cell that apex coordinate is (i, j), then βi,jFor
1, otherwise βi,jIt is the vertex of any cell on the chip for 0, P；
The equation group is solved, so that it is determined that may be inserted into the quantity of the buffer in the chip.
One or more technical solutions in the embodiment of the present invention, have at least the following technical effects or advantages:
The present invention is by by chip unit, after the mobile range each of on determining chip, according to every
A mobile range can determine the quantity of pluggable buffer in the chip, thus, not only optimize chip
Layout improves the quantity that can be inserted into the buffer area of buffer on chip, also reduces the interconnection delay of chip.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the schematic diagram of Buffer Insertion method in the prior art；
Fig. 2 is a kind of flow chart of the insertion method of chip buffers in the embodiment of the present invention；
Fig. 3 is the schematic diagram of a specific embodiment in the embodiment of the present invention.
Specific embodiment
For the limited amount for solving the buffer that the prior art can be inserted on chip, and wire length in buffer moving process
Chip caused by excessive interconnects the too long technical problem that is delayed, and the present invention provides a kind of insertion method of chip buffers.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of insertion method of chip buffers, as shown in Figure 2, which comprises
Step 101: blocking chip, to form the cell of several equalizations on chip.
In the specific implementation process, chip is subjected to blocking according to the size of a predefined unit first,
That is, chip is divided into several cells, the size of each unit lattice is identical.One door at least covers a cell, equally, one
A buffer at least covers a cell.Specifically, a door can cover a cell, a door can also cover more
A cell, when a door covers multiple cells, multiple cells become one group of cell.Equally, a buffer
A cell can be covered, a buffer can also cover multiple cells, when a buffer covers multiple cells
When, multiple cells become one group of cell.Wherein it is possible to using the lower left corner of each cell or every group of cell as should
The vertex of one cell or one group of cell, for example, the lower left corner of the cell is used as should for a cell
The vertex of cell, the lower left corner of a leftmost cell, which is used as, for one group of cell, in this group of cell is somebody's turn to do
The vertex of group cell.
Further, when a cell or one group of cell are covered by a door, the vertex of cell or one group of unit
The vertex of the top dotted or gate of lattice is overlapped, equally, when a cell or one group of cell are covered by buffer, a cell
Vertex or the vertex of one group of cell and the vertex of buffer be overlapped.For example, when door is covered on a cell, then, and door
Vertex be overlapped with the lower left corner of the cell, when door is covered on one group of cell, then, the vertex of door in this group of cell
The lower left corner of leftmost cell is overlapped, and buffer has same cover up rule, and details are not described herein again.
After executing the step 101, the application executes step 102: determining respectively every in all doors being located on chip
A mobile range.
In the specific implementation process, the height and width of the initial position and chip according to each door on chip, gives
Fixed each door chip both vertically and horizontally on mobile range, that is, each door is in the direction x of chip and the side y
Upward mobile range.For example, as shown in figure 3, in one embodiment, according to the length of the unit predefined
After chip unit, 6 cells are formed on a line chip, 2 doors, respectively door 1 are distributed on the chip
(gate1) and door 2 (gate2), the initial position of gate1 are located at second unit lattice, and the initial position of gate2 is located at Unit the 4th
The vertex of lattice, gate1 is overlapped with the vertex of second unit lattice, and the vertex of gate2 is overlapped with the vertex of the 4th cell.Given
The mobile range of gate1 is to move 1 cell to the left and to the right, then, gate1 can be placed on first unit lattice or second
In cell or third unit lattice.The mobile range of given gate2 is to move 2 cells to the left and to the right, then,
Gate2 can be placed in second unit lattice or third unit lattice or the 4th cell or the 5th cell or the 6th cell.
After executing the step 102, the application executes step 103: based on each mobile range, full
For each cell of foot at most by under conditions of a door or a buffer covering, determination may be inserted into the chip
The quantity of the interior buffer.
In the specific implementation process, according to integral linear programming (ILP, Integer Linear Programming), structure
Build following equation group:
Objective function:
Wherein, γi,jFor indicating whether door is placed in the cell that apex coordinate is (i, j), βi,jFor indicating
Whether buffer is placed in the cell that apex coordinate is (i, j), when door is placed on the unit that apex coordinate is (i, j)
In lattice, then γi,jIt is 1, otherwise γi,jIt is 0, when buffer is placed in the cell that apex coordinate is (i, j), then βi,jFor
1, otherwise βi,jIt is the vertex of any cell on the chip for 0, P.For example, γ1,1=1, that is, show that door can be placed
Apex coordinate is in the first unit lattice of (1,1).P is the vertex of any cell on chip.By solving above-mentioned equation group,
So that it is determined that can be inserted into the maximum quantity of buffer in the chip.
Specifically, in the Buffer insertion into chip, on the one hand should meet: all elements on chip divide line by line
Cloth, there is no any one element inter-bank distributions.On the other hand should meet: without superposition between the element on chip.The application benefit
The placement problem of buffer is solved with integral linear programming, that is, the maximum value for the buffer that can be inserted on chip is solved,
In, the quantity of buffer namely the quantity of buffer area.
In above-mentioned equation group, objective function are as follows:First constraint condition are as follows: It is all
Door, that is, all doors are necessarily distributed on chip.Second constraint condition are as follows:
All P
That is, without superposition between door and buffer on chip.Specifically,Indicate that all covering vertex are P
Cell βi,jSet, that is, buffer in moving process it is all cover vertex be P cell possible positions
Set.Indicate the γ for the cell that all covering vertex are Pi,jSet, that is, door in moving process own
Cover the set of the possible position for the cell that vertex is P.
Further, assume that buffer can be placed in any cell in solve system of equation.For example, above-mentioned specific
In embodiment, referring to Fig. 3, equation group can be listed below:
Finally, the linear programming can be solved by simplex algorithm (Simplex Method), obtain a result, in this example
The maximum value of pluggable buffer is 4.
Technical solution in above-mentioned the embodiment of the present application, at least have the following technical effects or advantages:
The present invention is by by chip unit, after the mobile range each of on determining chip, according to every
A mobile range can determine quantity and the position of pluggable buffer in the chip, thus, not only optimize
The layout of chip improves the quantity that can be inserted into the buffer area of buffer on chip, also reduces the interconnection delay of chip.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (5)
1. a kind of insertion method of chip buffers, which is characterized in that the described method includes:
Chip described in blocking, to form the cell of several equalizations on the chip；
Each in all doors being located on chip mobile range is determined respectively；
Based on each mobile range, at most buffered by a door or one meeting each cell
Under conditions of device covering, the quantity that may be inserted into the buffer in the chip is determined；
Wherein, described based on each mobile range, meeting each cell at most by a door
Or it under conditions of a buffer covering, determines the quantity that may be inserted into the buffer in the chip, specifically includes:
According to integral linear programming, following equation group is constructed:
Objective function:
Constraint condition:
Wherein, γi,jFor indicating whether door is placed in the cell that apex coordinate is (i, j), βi,jFor indicating to buffer
Whether device is placed in the cell that apex coordinate is (i, j), when door is placed on the cell that apex coordinate is (i, j)
It is interior, then γi,jIt is 1, otherwise γi,jIt is 0, when buffer is placed in the cell that apex coordinate is (i, j), then βi,jIt is 1,
Otherwise βi,jIt is the vertex of any cell on the chip for 0, P,Indicate the unit that all covering vertex are P
The β of latticei,jSet,Indicate the γ for the cell that all covering vertex are Pi,jSet；
The equation group is solved, so that it is determined that may be inserted into the quantity of the buffer in the chip.
2. the method as described in claim 1, which is characterized in that determine each mobile range, specifically:
According to the height and width of each door initial position on the chip and the chip, determine each door in institute
State chip both vertically and horizontally on mobile range.
3. the method as described in claim 1, which is characterized in that the door or the buffer on the chip divide line by line
Cloth.
4. the method as described in claim 1, which is characterized in that a door at least covers the cell, and one
The buffer at least covers the cell.
5. method as claimed in claim 4, which is characterized in that the cell described in the cell or one group is described
When door covering, the vertex of cell described in the vertex of cell or one group is overlapped with the vertex of the door；
When the cell described in the cell or one group is covered by the buffer, the vertex of cell or
The vertex of cell described in one group is overlapped with the vertex of the buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511032830.3A CN105677956B (en) | 2015-12-31 | 2015-12-31 | A kind of insertion method of chip buffers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511032830.3A CN105677956B (en) | 2015-12-31 | 2015-12-31 | A kind of insertion method of chip buffers |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105677956A CN105677956A (en) | 2016-06-15 |
| CN105677956B true CN105677956B (en) | 2019-04-02 |
Family
ID=56189984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511032830.3A Active CN105677956B (en) | 2015-12-31 | 2015-12-31 | A kind of insertion method of chip buffers |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105677956B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1547252A (en) * | 2003-11-28 | 2004-11-17 | 清华大学 | A Layout Method of Integrated Circuit Floorplanning and Buffer Planning |
| CN1732470A (en) * | 2002-12-17 | 2006-02-08 | 国际商业机器公司 | ASIC clock floor planning method and structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000222451A (en) * | 1999-02-02 | 2000-08-11 | Hitachi Ltd | Design support system for semiconductor integrated circuit |
| JP4801923B2 (en) * | 2005-03-31 | 2011-10-26 | 株式会社東芝 | Semiconductor integrated circuit design method |
-
2015
- 2015-12-31 CN CN201511032830.3A patent/CN105677956B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1732470A (en) * | 2002-12-17 | 2006-02-08 | 国际商业机器公司 | ASIC clock floor planning method and structure |
| CN1547252A (en) * | 2003-11-28 | 2004-11-17 | 清华大学 | A Layout Method of Integrated Circuit Floorplanning and Buffer Planning |
Non-Patent Citations (3)
| Title |
|---|
| 一种适用于标准单元设计的缓冲器插入及布线算法;任杰等;《微电子学》;20050630;第35卷(第3期);第286-289页 |
| 基于精确时延模型考虑缓冲器插入的互连线优化算法;张轶谦等;《电子学报》;20050531;第33卷(第5期);第783-787页 |
| 工艺变化条件下互连延时最小缓冲器插入方法;王新胜等;《北京邮电大学学报》;20140630;第37卷(第3期);第93-97、108页 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105677956A (en) | 2016-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Miclo et al. | Optimal epidemic suppression under an ICU constraint: An analytical solution | |
| US9530734B2 (en) | Enforcement of semiconductor structure regularity for localized transistors and interconnect | |
| CN104011800B (en) | Cyclic durability for the memory cell of nonvolatile memory array extends | |
| US20110167388A1 (en) | Electronic device and method of browsing images thereon | |
| CN109714264A (en) | The implementation method of sliding window current limliting based on buffer queue | |
| WO2006006084A8 (en) | Establishing command order in an out of order dma command queue | |
| US9715572B2 (en) | Hierarchical wire-pin co-optimization | |
| CN110032701A (en) | Image shows control method, device, storage medium and electronic equipment | |
| CN105677956B (en) | A kind of insertion method of chip buffers | |
| CN110389810A (en) | A kind of method, device and equipment for quickly putting UI control on virtual canvas | |
| CN103473013B (en) | The method of a kind of application interface regulation and mobile terminal | |
| US20160155427A1 (en) | Electronic device for displaying graphical user interface and method thereof | |
| CN110852503B (en) | Payment channel selection method and device and payment channel route | |
| CN104123027B (en) | Touch track smoothing method | |
| CN105578264B (en) | The processing method and processing device of animated menu based on smart television | |
| US9817936B2 (en) | Methods for minimizing layout area of IC | |
| CN107505981A (en) | A kind of control method and electronic equipment | |
| CN107820601A (en) | Display control method, display control program and display device | |
| WO2020181579A1 (en) | Coding and decoding methods and devices based on intra-frame prediction and filter | |
| CN103778595B (en) | Image shrinking processing method and device thereof | |
| CN102799576B (en) | The method and device of different ranks operation indicating is given in electrical form | |
| CN111814087B (en) | Dynamic layout method and device of Web window, electronic equipment and readable storage medium | |
| CN109298818A (en) | A kind of method, mobile terminal and computer readable storage medium that window is adjusted | |
| JP2010163272A (en) | Air conditioner for elevator | |
| US9286431B2 (en) | Oxide definition (OD) gradient reduced semiconductor device and method of making |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |