CN105676730A - Power supply power distribution management equipment override device for multipath electric load control - Google Patents
Power supply power distribution management equipment override device for multipath electric load control Download PDFInfo
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- CN105676730A CN105676730A CN201610023295.3A CN201610023295A CN105676730A CN 105676730 A CN105676730 A CN 105676730A CN 201610023295 A CN201610023295 A CN 201610023295A CN 105676730 A CN105676730 A CN 105676730A
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Abstract
The invention realizes read-write operation instructions of data of a corresponding address of a UFM inside a CPLD through SPI communication; instructions and design of configuration of a channel override switch are realized through the UFM of the CPLD; the CPLD is power on and automatically reads the data in the corresponding address of the UFM; configuration of an override is realized according to a data value in the corresponding address of the UFM; and all override strategies can cover the corresponding condition of all override signals and channels. Under the condition of not opening a product reburning process, override configurability is realized.
Description
Technical field
The present invention is the power supply distribution management equipment override based on a kind of multipath electric load controlDevice.
Background technology
For secondary power distribution product, each channel switch both can be controlled by external communication,By Communication Control master controller, master controller carries out passage break-make by discrete magnitude againControl. In the time that master controller lost efficacy, for normal control channel is opened shutoff, needAvoid the control of master controller, directly introduce override discrete magnitude signal by outside and directly controlChannel switch. The control signal of outside override signal and master controller is separate, all can be justNormal control channel break-make.
In general secondary power distribution product, the configuration of override control is all generally given,The given several passages of override signal controlling certain or certain, in this case, canBe configured by internal logic design. If need to change the configuration of override signal, mustMust carry out internal logic and redesign and new the designing program of burning, process more complicated.
Summary of the invention
The object of the present invention is to provide a kind of power supply distribution management of multipath electric load controlEquipment override device, the present invention is a kind of UFM override Strategy Design based on CPLD, can appointThe configuration of meaning change override.
To achieve these goals, technical scheme of the present invention is: a kind of multipath electric loadThe power supply distribution management equipment override device of controlling, is characterized in that override device comprises CPLDChip, comprises an override configuration module in described CPLD chip, and with override configuration moduleThe UFM connecting, the input of described override configuration module and outside input Wu road override signalConnect, the output of described override configuration module is connected with external channel, and described UFM is with outerPortion's communication connects, and the NCS port of described UFM is connected with outside NCS control signal, outsideCommunication reads and writes data in the inherent address of the UFM in CPLD, and outside NCS control signal is usedIn activating UFM, override configuration module is from reading out data in UFM inherent address, according to inherentlyData configuration 5 tunnel override signal controlling external channels in location.
Preferably, described CPLD chip is EPM1270GT144I5, the UFM in this CPLDHave 4 external interfaces, be respectively NCS interface, this NCS interface is that sheet selects interface, whenWhen NCS interface drags down, show that this UFM is selected, can carry out SPI communication; SI interface,Be connected with external communication input, in the time of the rising edge of clock signal, carry out data and read; SOInterface, is connected with external communication output, carries out data defeated in the time of the trailing edge of clock signalGo out; SCK interface, described SCK interface is serial clock interface.
Preferably, a kind of power supply distribution management equipment override device of multipath electric load controlOverride method, comprise the following steps: A, outside NCS control signal are chosen this NSC, outerPortion's communication writes enable command word, writing address and data writing respectively in UFM, willData write the inherent address of UFM; B, outside NCS control signal are chosen this NSC, outsideCommunication writes disable order, writing address and arbitrary data respectively in UFM, by numberBe moved to shift register according to the inherent address from UFM; C, override configuration module are posted from displacementStorage reading out data, according to the data configuration 5 tunnel override signal controlling external channels that read.
The invention provides a kind of UFM override Strategy Design based on CPLD, can change arbitrarilyOverride configuration. And this Strategy Design can be right in the situation that not changing internal logic designOnline updating is carried out in override configuration. This kind of override Strategy Design realized online change override and joinedPut, easy to operate simple, the change override signal demand having run into before having avoided redesignsThe complex operations problem of override logic burning logical program. Product model machine in chamber is tested by experimentDemonstrate,prove its feasibility. This UFM has power down hold function simultaneously, and its data storage operations existsThere is the very large space that utilizes data power down storage aspect. Outside can being used as in product designThe memory of portion's expansion, has reduced the use of components and parts in design, has improved the reliable of productProperty.
Figure of description
Fig. 1 is passage override control design frame chart.
Fig. 2 is SPI data transmission principle figure.
Fig. 3 is that UFM internal data reads principle automatically.
Fig. 4 is the automatic reading out data sequential of UFM internal data.
Fig. 5 is the UFM override Strategy Design block diagram based on SPI communication of the present invention.
Fig. 6 is the UFM override Strategy Design schematic diagram based on SPI communication.
Fig. 7 is the SPI communication of DSP and UFM.
Fig. 8 is the SPI communication schematic diagram of DSP and UFM.
Fig. 9 is the inner realization figure of the CPLD of SPI communication.
Figure 10 is that UFM internal data reads schematic diagram automatically.
Figure 11 is the automatic reading out data sequential of UFM internal data.
Figure 12 is that serial data turns realization figure also.
Figure 13 is the realization figure of single channel override configuration.
Detailed description of the invention
Described this paper of the present invention designs as an example of 5 override signal controlling 64 paths exampleExplanation. As Fig. 1, a kind of power supply distribution management equipment override device of multipath electric load control,It is characterized in that override device comprises CPLD chip, in described CPLD chip, comprise an overrideConfiguration module, and the UFM being connected with override configuration module, described UFM and override configuration mouldBetween piece, be also provided with string and turn and module, the input of described override configuration module is with outside defeatedRu five tunnel override signals connect, and the output of described override configuration module and external channel connectConnect, described UFM is connected with external communication, the NCS port of described UFM and outside NCS controlSignal processed connects, and external communication reads and writes data in the inherent address of the UFM in CPLD, outerPortion's NCS control signal is used for activating UFM, and override configuration module reads in UFM inherent addressData, according to the data configuration 5 tunnel override signal controlling external channels in inherent address.
The present invention will represent the external channel of required control by peripheral control unit in advanceData in advance leave in the register of UFM, then read by override configuration module,Control external channel according to the data that read.
The data that write command word, address and write by peripheral control unit writing fashionable. BehaviourIt is in the process powering on that control configuration information reads, and CPLD inside self is to UFM fixed addressThe empty data (as 0xFF) that write command word, address and the respective numbers of admittedly depositing, UFMAutomatically the data in appropriate address are exported to manipulation information analysis module. The UFM's writingData are actual is to control five tunnels manipulations signals whether to control respective channel, such as override 1 whetherControl first passage, controlled by the lowest order of the data that write, as Figure 13, if override1 need to control first passage, D_1[0]=1; Otherwise D_1[0]=0; Every like this road override isNo control respective channel is by D_1[0], D_2[0], D_3[0], D_4[0], D_4[0] comeDetermine.
According to specific embodiment, the present invention is described in detail below.
As Fig. 1, external communication reads and writes data in the inherent address of UFM in CPLD, writesData will be kept at (UFM has power down memory function) in this inherent address. In CPLDOverride configuration module can after each product powers on, read voluntarily in UFM inherent addressWhich road is data, specifically control according to the data configuration 5 tunnel override signals in inherent address logicalRoad, and every kind of control situation all can cover. The CPLD chip relating to is hereinEPM1270GT144I5. The UFM of this chip is divided into two kinds, and one is Basemode, basicPattern, the UFM of this pattern has 256 address spaces, and each address space can be stored oneByte, can store 256 bytes altogether. One is Extendedmode, mode of extension.The UFM of this pattern has 512 address spaces, point two sections, ground, 256 of each sectionsLocation. Each address space can be stored a word, and two sections can be stored 512 words altogether.
Can find out from overall framework figure, the UFM override strategy master-plan based on CPLD dividesBe three parts:
1. the data communication of UFM in peripheral control unit and CPLD;
2. in CPLD, read voluntarily the data inside of UFM;
3. control the configuration to passage control.
The first step that first the data external communication of UFM will be done is peripheral control unit and CPLDThe data communication of middle UFM, can know according to the databook of UFM in CPLD, UFM withThe data exchange mode of peripheral control unit has four kinds:
1, I2C communication mode (Inter-IntegratedCircuit);
2, SPI communication mode (SerialPeripheralInterface);
3, parallel communication pattern (ParallelInterface);
4, Serial Communication Mode (AlteraSerialInterface).
Herein in CPLD, the data of UFM read and mainly realize by SPI communication mode.
This UFM has 4 external interfaces, employing be the SPI interface of four-wire system, as table 1.
Table 1 interface specification
| Interface | Function declaration |
| SI | Data Input Interface |
| SO | Data output interface |
| SCK | Serial clock interface |
| NCS | Sheet selects interface |
As table 1, NCS is that sheet selects interface, in the time that NCS interface drags down, shows that this UFM is selectedIn, can carry out SPI communication; SI interface carries out data and reads in the time of the rising edge of clock signalGet; SO interface carries out data output in the time of the trailing edge of clock signal; The order of all transmissionThe all step-by-step transmission successively from highest order to lowest order of word, address and data.
In the time that NCS interface drags down, and then needing provides command word data to UFM, otherwiseUFM can think internal logic mistake and directly ignore the data that transmit. Obtaining of control command wordObject and the operation of informing the current communication of UFM. Table 2 is channel command word.
Table 2 channel command word
As seen in Table 2, WREN is that UFM writes enable command, when write this command word to UFMAfter can be to UFM data writing, WRDI writes disable order for UFM, when to UFMWriting cannot be to UFM data writing after this command word. RDSR is read states register command,WRSR is for writing status register order. READ is for reading UFM order, and WRITE is for writing UFM lifeOrder. SECTOR-ERASE is the command word of wiping certain section of UFM of Basemode,UFM-ERASE is the command word of wiping two sections of UFM of Extendedmode.
The SPI of two processors displacement when the SPI communication of UFM in peripheral control unit and CPLDRegister is equivalent to an end to end closed loop. Peripheral control unit when writing data in UFM,The shift register of peripheral control unit from one one of highest order toward the shift register of UFMLowest order in transmit data. Meanwhile, the shift register of UFM from highest order also at one oneGround, position transmits data by SO mouth to the highest order of peripheral control unit SPI shift register. AsShown in Fig. 2, because the input of, data and output are simultaneously, reading data procedures in UFMIn write behind OPCODE and address, UFM, just by the required DSR reading, also needs againWriting an arbitrary data byte can be by needed data from the shift register of UFMMany ground shift out.
If desired read the data in the 0x00 of address in UFM, first choose this UFM, i.e. UFMNCS drag down. Secondly in UFM, write OPCODE, i.e. 0x03. Again, write needsThe address of sense data, the data that need to read address 0x00 the inside write 0x00. ThisTime UFM by the DSR of 0x00 the inside, finally also need to write in UFMEnter any one byte data ready data be shifted out from the shift register of UFM,As write 0xFF. Therefore after UFM sheet is chosen, needing to send data 0300FF canBy the data reading in the 0x00 of address. This 0x00 address is initial address, if continue to UFMIn write the data of any one byte, UFM is by the data in output 0x01 address, successivelyAnalogize.
The method that the method that data write reads with data is identical, is also first to write OPCODECommand word 0x02, then write the address of wanting data writing, as 0x00 (0x00 address), lastData writing. In the process writing in data, it should be noted that: UFM internal data only withWrite as " 0 " by " 1 ", cannot be write as " 1 " by " 0 ", therefore at data write operationNeed the content of this address to wipe before. In data erase operation, it should be noted that:Data erase is to the wiping of whole section, and therefore before erase operation, will confirm to wipeSection is without important data.
After override configuration data writes the UFM of CPLD by peripheral control unit, CPLD needsDepart from the control of peripheral control unit completely, the value reading in UFM by inside is carried out overrideStrategy is realized. According to the principle of UFM reading and writing data in CPLD, can be according to the read-write of UFMSequential chart carries out reading and writing data.
The data that read in UFM inside are always divided into two large modules: 1) frequency clock module;2) order (read write command) generation module.
Utilizing UFM in CPLD to carry the frequency clock that frequency clock output solves read-write needsAsk, provide clock frequency by frequency division and the time delay of this clock frequency to UFM. According to timeClock frequency generates the reading and writing data order of fixed address. UFM internal data automatically read principle asShown in Fig. 3. The OSC port of UFM is connected with clock frequency division module, clock frequency division module and timeClock time delay module connects, and clock delay module is connected with order output module, and with UFM'sSCK port connects, and order output module is connected with the SI port of UFM.
UFM, by OSC port one output frequency clock, can make UFM according to chip dataThe clock cycle of normal work is not less than 2.8us, and the maximum cycle of UFM output waveform is0.208us, carries out clock division by clock frequency division module 2, and being met UFM communication needsThe clock frequency of asking.
Because duty and the Interface status of UFM in power up are indefinite. If on oneElectricity UFM is with regard to clock signal, and to UFM input read write command, UFM may output errorData. Therefore need time delay a period of time again to UFM input read write command. By clock delayAfter 3 time delay a period of times of module, continuing provides clock frequency to UFM. After clock frequency realizesJust need to write read write command according to clock frequency to UFM.
Passage override configuration information is definite in product power up, and product powered onIn journey, reading out data in the fixed address from UFM is determined override configuration information by CPLD. CauseThis, in power up, order output module 5 can directly be read in the fixed address of UFMFetch data, reading order and address all exist in order output module 5 admittedly, and are to power onOnly read and carry out once.
As the data of reading in the 0x11 of address need to input data 0311FF, 0x03 is for readingCommand word, 0x11 is address, when 0x03 and 0x11, admittedly exists in order output module 5,0xFF is in order to shift out the data in 0x11 address. In power up, when clock comes on oneRise edge, order output module will be exported a data, start transmission from the highest order of 0x03.Clock 4 frequencies and phase place that same this clock reads with UFM data are all identical, so just canEnough ensure that data UFM of the every output of module 5 just reads these data. Simultaneously in this timeSection UFM is that sheet selects selected state.
Read data manipulation in 0x11 address reading each signal waveform in the time period as figureShown in 4.
In the situation that SCK exists, continue to write any one byte number in UFMAccording to rear, UFM is by the data in output 0x12 address. Continue again to write any one in UFMAfter data, by the data in OPADD 0x13, by that analogy. Until chip selection signal is got back toAfter high level, then continue to wait for next chip selection signal and command word.
A specific embodiment according to the present invention is to the UFM override based on SPI communication belowStrategy Design is analyzed. Fig. 5 is the UFM override Strategy Design block diagram based on SPI communication.
DSP can be by SPI mouth to CPLD after receiving outside RS485 or CAN communication commandUFM in read and write data, the data that write be saved in an inherent address in UFM (GuThere is address to write fashionable providing by DSP). Write rear override configuration module and can read voluntarily UFMData in inherent address. Concrete according to the data configuration 5 tunnel override signals in inherent addressControl which paths, and every kind of control situation all can cover.
UFM override strategy master-plan based on SPI communication is divided into three parts:
1. the exchanges data of UFM (SPI communication) in board DSP and CPLD;
2. in CPLD, read voluntarily the data inside of UFM;
3. the configuration of override to passage control;
The data of UFM that read DSP in data in UFM and CPLD read voluntarily passes through DSPAn IO mouth select, as Fig. 5 " ★ " locates.
UFM override Strategy Design schematic diagram based on SPI communication as shown in Figure 6. In figure, wrapDraw together UFM, the SI mouth of described UFM with first with door AND1 output is connected, first withThe first input end of AND1 is connected with first or the output of door OR1, and first or OR1First input end and external control NSC_EN end is connected, and first or the second input of an OR1Be connected with the SI port of external communication, first with door AND1 the second input and the 4th orDoor OR4 output connect, the 4th or door OR4 first input end and the first phase inverter D1Output connect, the input of the first phase inverter D1 and external control NSC_EN hold and are connected,The 4th or the SI_in of the second input and the order output module 5 of door hold and be connected, described UFMSCK mouth is connected with the output of door AND2 with second, the second first defeated with AND2Enter end and be connected with second or the output of door OR2, second or the first input end of OR2 andExternal control NSC_EN holds connection, and second or door the second input of OR2 and external communicationSCK port connects, second with the second input of door AND2 and the 5th or the output of OR5End connect, the 5th or door OR5 first input end be connected with the output of the first phase inverter D1,The 5th or the second input of door OR5 be connected with the 7th or the output of OR7, described UFMNCS mouth is connected with the output of door AND3 with the 3rd, the 3rd first defeated with AND3Enter end and be connected with the 3rd or the output of door OR3, the 3rd or the first input end of OR3 andExternal control NSC holds connection, and the 3rd or door the second input of OR3 and external communicationNCS_EN port connects, the 3rd with the second input of door AND3 and the 6th or OR6 defeatedGo out end and connect, the 6th or the door first input end of OR6 and the output of the first phase inverter D2 companyConnect, the 6th or the second input of door OR6 be connected with osc_stop port, the 7th or OR7First input end is connected with the 9th or the output of door OR9, the 7th or OR7 secondInput is connected with osc_stop port, and osc_stop port is by outside inst58'sThe output of osc_stop port, as Fig. 6. Read the manipulation configuration of 1 fixed address when powering onAfter information, osc_stop exports high level, prevents in course of normal operation order output mouldPiece 5 continues to send crystal oscillator signal to UFM. The OSC_in end of order sending module with the 8th orThe output of door OR8 connects, and the 8th or the first input end of door OR8 and the 9th or OR9Output connect, the 8th or door OR8 the second input and the 6th or door OR6 secondInput connect, the 9th or door OR9 first input end with the 5th with output be connected,The 5th with the first input end of door AND5 be connected with external control NSC_EN end, the 5th andDoor the second input of AND5 and the clk_out port of clock frequency division module 2 are connected, clockThe clk_in port of frequency division module 5 is connected with the OSC port of UFM, the 5th with door an AND5Output is also connected with the first input end of door AND6 with the 6th, the 6th with AND6'sThe second input is connected with the delay_out port of clock delay module 3, the 6th with door an AND6Output is also connected with the 9th or the first input end of door OR9, the 6th defeated with AND6Go out end and be connected with the osc1_in port of clock delay module 3, clock delay module 3Delay_out port with the 9th or door OR9 the second input be connected, the SO port of UFM(triple gate TR1, in the time enabling, output is identical with input, when disable with triple gate TR1Be output as high resistant) input connect, the SO of the output termination of triple gate TR1 output DSPOutput port, the control end of TR1 is connected with the output of the second phase inverter D2, and second is anti-phaseThe input termination external control NSC_EN end of device D2, the SO port of UFM also with the 4th with doorThe second input of AND4 connects, and the 4th connects external control with the first input end of door AND4NSC_EN end, the 4th turns the also SO_IN port of module with the output of door AND4 with string is connected.
Comprise following part in the UFM override Strategy Design principle based on SPI communication:
1. the exchanges data of UFM (SPI communication) in board DSP and CPLD;
2. in CPLD, read voluntarily the data inside of UFM;
3. the configuration of override to passage control;
In Fig. 6, " ★ " locates IO mouth control DSP the data of UFM read with CPLD UFMRead voluntarily.
1. the SPI communication of UFM in board DSP and CPLD
In DSP and CPLD, the SPI communication of UFM as shown in Figure 7 and Figure 8.
Fig. 9 is that schematic diagram is realized in the SPI communication inside of UFM in DSP and CPLD. Due to UFMWhen override passage control configuration, UFM reading and writing data is divided into two parts, and one is that DSP is to UFMThe read-write of appropriate address, one is the voluntarily read-write of CPLD inside to UFM appropriate address. ?When DSP read-write, need, by inside read-write capability shielding voluntarily, when same inside is read and write voluntarily, needDSP read-write capability is shielded. Therefore use an IO mouth of DSP to select UFM hereDSP read-write or CPLD inside read and write voluntarily. As in Fig. 9 1., in the time 1. locating to drag down,Select the reading and writing data of DSP to UFM.
2. the internal data of the UFM based on SPI communication reads
After override configuration data writes the UFM of CPLD by DSP, CPLD need to be completely de-From the control of DSP, the value reading in UFM by inside is carried out the realization of override strategy. RootAccording to the principle of UFM reading and writing data in CPLD, can be according to the read-write sequence figure number of UFMAccording to read-write.
The data that read in UFM inside are always divided into two large modules: 1) frequency clock module;2) order (read write command) generation module.
Utilizing UFM in CPLD to carry the frequency clock that frequency clock output solves read-write needsAsk, provide clock frequency by frequency division and the time delay of this clock frequency to UFM. According to timeClock frequency generates the reading and writing data order of fixed address. Figure 10 is that UFM internal data is read automaticallyGet principle.
The UFM frequency clock of OSC port one output, can make UFM normal according to chip dataThe clock cycle of work is not less than 2.8us, and the maximum cycle of UFM output waveform is0.208us, carries out clock division by clock frequency division module 2, obtains the clock cycle and is4.45us, meets the clock cycle demand of UFM.
Because the duty of UFM in power up is indefinite, if once powering on to UFMInput read write command, UFM may output error data. Therefore need time delay a period of time againTo UFM input read write command. Clock delay module 3, continued to UFM after time delay a period of timeClock frequency is provided. Clock frequency just needs to write and study in to UFM according to clock frequency after realizingWrite order.
In order output module 5, the order 0300FF that reads address 00 interior data is ready to,When carrying out a rising edge, clock will export a data, since 03 highest order transmission. WithClock frequency 4 and phase place that this clock of sample reads with UFM data are all identical, so just canEnsure that data UFM of order output module 5 every transmission just reads these data. Simultaneously at thisIndividual time period UFM is that sheet selects selected state.
Because this part is the voluntarily read-write of CPLD to data in UFM appropriate address, at this moment needShield the reading and writing data of DSP to UFM, therefore VCC need to draw high to shield the behaviour of DSPDo.
If read the data in 0x11 address, it reads each signal waveform in the time period as figure11。
Read the data of 0x11 address: first send read command word 0x03 to UFM, next is givenUFM sends the address 0x11 of reading out data, finally sends the data of any one byteData in address 0x11 in UFM are shifted out. Situation about existing at SCKUnder, continuing to write after any one byte data in UFM, UFM will export 0x12 groundData in location.
3. the configuration of the override based on SPI communication to passage control
For override design, need to process the data that read. Here utilize string to turnAnd data transmission module, after serial data, be converted into parallel data receiving.
As being converted into parallel data after this module, the data of Figure 12 serial input spread out of,64 passages of five override control need 40 byte datas. 40 byte datas transformBe 320 bit data, the override of utilizing 320 parallel bit data to be used as each passage enables.
As Figure 13, the first place of data D_1 is equivalent to enabling of this override signal, if this overrideSignal can be controlled T1_1 passage, and the first place of D_1 is 1, otherwise is 0. Therefore, rootEach that can determine 320 according to corresponding data in UFM is one " 0 " or " 1 ",Can complete like this 5 overrides the passage of required control is controlled, and 5 superControl signal is to the control combination of 64 paths for arbitrarily, and any override combination all can coverArrive.
The SPI of UFM and master controller and the integrated communication of SCI, i.e. master controller application SCIThe SPI communication interface of communication interface and UFM carries out communication, and this communication mainly completes two kindsThe coupling of Frame and communication clock, and understanding to communication principle and communication succession shouldWith.
Below only expressed embodiments of the present invention, it describes comparatively concrete and detailed, butCan not therefore be construed as limiting the scope of the patent. It should be pointed out that forThose of ordinary skill in the art, without departing from the inventive concept of the premise, also canTo make some distortion and improvement, these all belong to protection scope of the present invention. Therefore, originallyThe protection domain of patent of invention should be as the criterion with claims.
Claims (4)
1. the power supply distribution management equipment override device of a multipath electric load control, it is characterized in that override device comprises CPLD chip, in described CPLD chip, comprise an override configuration module, and the UFM being connected with override configuration module, the input of described override configuration module is connected with outside input Wu road override signal, the output of described override configuration module is connected with external channel, described UFM is connected with master controller, the NCS port of described UFM is connected with outside NCS control signal, external communication reads and writes data in the inherent address of the UFM in CPLD, outside NCS control signal is used for activating UFM, override configuration module is from reading out data in UFM inherent address, according to the data configuration 5 tunnel override signal controlling external channels in inherent address.
2. power supply distribution management equipment override device as claimed in claim 1, it is characterized in that described CPLD chip is EPM1270GT144I5, UFM in this CPLD has 4 external interfaces, be respectively NCS interface, this NCS interface is that sheet selects interface, in the time that NCS interface drags down, show that this UFM is selected, can carry out SPI communication; SI interface, is connected with external communication input, carries out data and read in the time of the rising edge of clock signal; SO interface, is connected with external communication output, carries out data output in the time of the trailing edge of clock signal; SCK interface, described SCK interface is serial clock interface.
3. power supply distribution management equipment override device as claimed in claim 1, it is characterized in that described CPLD chip comprises UFM, the SI mouth of described UFM is connected with the output of door with first, first with door first input end with first or output be connected, first or door first input end be connected with external control end, first or door the second input be connected with the port of external communication, first with door the second input with the 4th or output be connected, the 4th or door first input end be connected with the output of the first phase inverter, the input of the first phase inverter is connected with external control end, the 4th or the SI_in of the second input and the order output module of door hold and be connected, the SCK mouth of described UFM is connected with the output of door with second, second with door first input end with second or output be connected, second or door first input end be connected with external control end, second or door the second input be connected with the SCK port of external communication, second with door the second input with the 5th or output be connected, the 5th or door first input end be connected with the output of the first phase inverter, the 5th or door the second input with the 7th or output be connected, the NCS mouth of described UFM is connected with the output of door with the 3rd, the 3rd with door first input end with the 3rd or output be connected, the 3rd or door first input end be connected with external control end, the 3rd or door the second input be connected with the NCS_EN port of external communication, the 3rd with door the second input with the 6th or output be connected, the 6th or door first input end be connected with the output of the first phase inverter, the 6th or door the second input be connected with osc_stop port, the 7th or door first input end with the 9th or output be connected, the 7th or door the second input be connected with osc_stop port, osc_stop port is exported by the osc_stop port of outside inst58.
4. the override method of power supply distribution management equipment override device as claimed in claim 1, it is characterized in that comprising the following steps: A, outside NCS control signal are chosen this NSC, external communication writes enable command word, writing address and data writing respectively in UFM, data is write to the inherent address of UFM; B, outside NCS control signal are chosen this NSC, and external communication writes disable order, writing address and arbitrary data respectively in UFM, and data are moved to shift register from the inherent address of UFM; C, override configuration module are from shift register reading out data, according to the data configuration 5 tunnel override signal controlling external channels that read.
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