CN105674871A

CN105674871A - Film thickness detection device

Info

Publication number: CN105674871A
Application number: CN201610203870.8A
Authority: CN
Inventors: 林永辉; 戴朋飞; 韩晓伟
Original assignee: Weihai Hualing Opto Electronics Co Ltd
Current assignee: Weihai Hualing Opto Electronics Co Ltd
Priority date: 2016-04-01
Filing date: 2016-04-01
Publication date: 2016-06-15
Also published as: WO2017166737A1

Abstract

The invention provides a film thickness detection device. The detection device comprises at least one common electrode and at least one detection chip. Each detection chip comprises a detection electrode array, comprising a plurality of detection electrodes and opposite to and arranged at intervals with the common electrode in the first direction; a reset unit, electrically connected with each detection electrode in the detection electrode array and used for resetting the electrical signals of the detection electrode; an initial amplification unit, electrically connected with each detection electrode and used for amplifying the electrical signals; a displacement control unit, electrically connected with the initial amplification unit and used for controlling output sequence of the electrical signals; a scanning bit bus, comprising a plurality of scanning connection points, wherein one scanning connection point is electrically connected with the displacement control unit; and a logic control unit, used for receiving external input signals, generating a control signal for controlling the detection chip and outputting detection signals. The detection device is high in detection precision.

Description

The detecting device of thickness

Technical field

The application relates to the detection field of thickness, in particular to the detecting device of a kind of thickness.

Background technology

In financial field, the true and false of bank note is differentiated by various modes and screens by cash inspecting machine, ATM and cleaning-sorting machine, wherein, is all much the true and false by the detection of the thickness of bank note distinguishes bank note. And the detection of banknote thickness all adopts the detection mode of pinch roller mostly, when namely bank note is by pinch roller, measures the gap of pinch roller, and then judged the thickness of bank note by gap. There is a lot of shortcoming in this detection mode, high speed not high including detection huge structure, resolution easily causes card paper money when sending into bank note, and accuracy of detection is relatively low, for instance, when bank note posts less foreign body, it is not easy to detect.

Summary of the invention

The main purpose of the application is in that to provide the detecting device of a kind of thickness, to solve the problem that detecting device of the prior art is huge and accuracy of detection is relatively low.

To achieve these goals, an aspect according to the application, provide the detecting device of a kind of thickness, this detecting device includes at least one public electrode and at least one detection chip, wherein, each above-mentioned detection chip includes: detecting electrode array, and above-mentioned public electrode is relative in a first direction and interval is arranged, interval between above-mentioned public electrode and above-mentioned detecting electrode array constitutes the transmission channel of film to be measured, and above-mentioned detecting electrode array includes multiple detecting electrode; Reset unit, electrically connects with each above-mentioned detecting electrode in above-mentioned detecting electrode array, for being resetted by the signal of telecommunication of each above-mentioned detecting electrode; Initial amplifying unit, electrically connects with each above-mentioned detecting electrode in above-mentioned detecting electrode array, and above-mentioned initial amplifying unit is for amplifying the signal of telecommunication of each above-mentioned detecting electrode; Displacement control unit, electrically connects with above-mentioned initial amplifying unit, and above-mentioned displacement control unit is for controlling the output order of the multiple above-said current signal after amplifying; Scanning BITBUS network, including multiple scanning junction points, an above-mentioned scanning junction point electrically connects with above-mentioned displacement control unit; Logic control element, for receiving the input signal in the external world, producing the control signal controlling above-mentioned detection chip and output detections signal.

Further, above-mentioned detection chip also includes: multi-gain amplification unit, including first input end and the second input, above-mentioned first input end and an above-mentioned scanning junction point electrical connection.

Further, above-mentioned initial amplifying unit is initial amplifier array, above-mentioned initial amplifier array includes multiple initial amplifier, above-mentioned initial amplifier and above-mentioned detecting electrode one_to_one corresponding, and the input of each above-mentioned initial amplifier electrically connects with corresponding detecting electrode.

Further, above-mentioned reset unit is reset switch array, above-mentioned reset switch array includes multiple reset switch, above-mentioned reset switch and above-mentioned detecting electrode one_to_one corresponding, each above-mentioned reset switch includes reset switch the first end, reset switch the second end and reset switch the 3rd end, each above-mentioned reset switch first terminates into fixed voltage, on respectively state reset switch second and terminate into reset signal, each above-mentioned reset switch the 3rd end electrically connects with corresponding detecting electrode, above-mentioned reset signal controls above-mentioned reset switch and connects, the signal of telecommunication of corresponding above-mentioned detecting electrode is resetted.

Further, above-mentioned displacement control unit includes: shift switching array, including multiple shift switchings, above-mentioned shift switching and above-mentioned initial amplifier one_to_one corresponding, each above-mentioned shift switching includes shift switching the first end, shift switching the second end and shift switching the 3rd end, and each above-mentioned shift switching the first end electrically connects with the outfan of corresponding initial amplifier; Shift control circuit electrically connects with each above-mentioned shift switching the second end, and above-mentioned shift control circuit is for controlling the on and off of each above-mentioned shift switching.

Further, above-mentioned detection chip also includes: scanning storage switch array, including multiple scanning storage switchs, above-mentioned scanning storage switch and above-mentioned initial amplifier one_to_one corresponding, each above-mentioned scanning storage switch includes scanning storage switch the first end, scanning storage switch the second end and scanning storage switch the 3rd end, each above-mentioned scanning storage switch the first end electrically connects with the outfan of corresponding initial amplifier, and each above-mentioned scanning storage switch second terminates into scanning switch signal; Scanning storage capacitor array, including multiple scanning storage electric capacity, above-mentioned scanning storage electric capacity includes scanning capacitance the first end and scanning capacitance the second end, above-mentioned scanning storage electric capacity and above-mentioned scanning storage switch one_to_one corresponding, each above-mentioned scanning capacitance the first end is connected electrically between scanning storage switch the 3rd end and corresponding shift switching first end of correspondence, each above-mentioned scanning capacitance the second end ground connection, each above-mentioned scanning storage electric capacity is for storing the corresponding initial amplifier output signal of telecommunication when the detecting electrode that scanning is corresponding.

Further, above-mentioned detection chip also includes: scanning BITBUS network clamp switch, including scanning clamp switch the first end, scanning clamp switch the second end and scanning clamp switch the 3rd end, above-mentioned scanning clamp switch the first end is connected electrically between above-mentioned scanning BITBUS network and above-mentioned first input end, above-mentioned scanning clamp switch second terminates into clamp switch signal, above-mentioned scanning clamp switch the 3rd terminates into fixed voltage Vc, before the signal of telecommunication reading each above-mentioned scanning storage electric capacity, above-mentioned clamp switch signal controls above-mentioned scanning BITBUS network clamp switch and connects, by the voltage clamp of above-mentioned scanning BITBUS network to voltage Vc.

Further, above-mentioned multi-gain amplification unit includes: gain amplifier, and including two inputs and an outfan, two input corresponding above-mentioned first input ends respectively and above-mentioned second input, above-mentioned first input end electrically connects with above-mentioned scanning BITBUS network; Reference voltage sample circuit, electrically connects with above-mentioned second input, and said reference voltage sample circuit is for regulating the output signal of telecommunication of above-mentioned gain amplifier; Output buffer, the input of above-mentioned output buffer electrically connects with the above-mentioned outfan of above-mentioned gain amplifier, for increasing the driving force of the output signal of above-mentioned gain amplifier.

Further, above-mentioned shift switching array includes multipair shift switching, multipair above-mentioned shift switching and multiple above-mentioned initial amplifier one_to_one corresponding, every pair of shift switching includes two shift switchings, being the first shift switching and the second shift switching respectively, each above-mentioned first shift switching includes first shift switching the first end, first shift switching the second end and the first shift switching the 3rd end;Each above-mentioned second shift switching includes second shift switching the first end, second shift switching the second end and the second shift switching the 3rd end, wherein, each above-mentioned first shift switching the first end electrically connects with corresponding scanning capacitance the first end, each above-mentioned first shift switching the 3rd end electrically connects with above-mentioned scanning BITBUS network, each above-mentioned first shift switching the second end electrically connects with above-mentioned shift control circuit, and above-mentioned detection chip also includes: reset storage switch array, including multiple reset storage switchs, above-mentioned reset storage switch and above-mentioned initial amplifier one_to_one corresponding, each above-mentioned reset storage switch includes reset storage switch the first end, reset storage switch the second end and reset storage switch the 3rd end, each above-mentioned reset storage switch the first end electrically connects with the outfan of corresponding initial amplifier, each above-mentioned reset storage switch second terminates into reset switch signal, reset storage capacitor array, including multiple storage electric capacity that reset, above-mentioned reset storage electric capacity and above-mentioned reset storage switch one_to_one corresponding, each above-mentioned reset storage electric capacity includes reset capacitance the first end and reset capacitance the second end, each above-mentioned reset capacitance the first end is connected electrically between reset storage switch the 3rd end and second corresponding shift switching first end of correspondence, each above-mentioned reset capacitance the second end ground connection, each above-mentioned reset storage electric capacity is for storing the corresponding initial amplifier output signal of telecommunication when resetting corresponding detecting electrode, reset BITBUS network, including multiple reset junction points, one above-mentioned reset junction point is connected electrically in each above-mentioned second shift switching the 3rd end and above-mentioned second input, or an above-mentioned reset junction point electrically connects with each above-mentioned second shift switching the 3rd end, and another above-mentioned reset junction point electrically connects with above-mentioned second input.

Further, above-mentioned detection chip also includes: reset BITBUS network clamp switch, including reduction forceps bit switch the first end, reduction forceps bit switch the second end and reduction forceps bit switch the 3rd end, above-mentioned reduction forceps bit switch the first end is connected electrically between above-mentioned reset BITBUS network and above-mentioned second input, above-mentioned reduction forceps bit switch second terminates into above-mentioned clamp switch signal, above-mentioned reduction forceps bit switch the 3rd terminates into fixed voltage Vc, before the signal of telecommunication reading each above-mentioned reset storage electric capacity, above-mentioned clamp switch signal controls above-mentioned reset BITBUS network clamp switch and connects, by the voltage clamp of above-mentioned reset BITBUS network to voltage Vc.

Further, above-mentioned multi-gain amplification unit includes: gain amplifier, including two inputs and an outfan, two input corresponding above-mentioned first input ends respectively and above-mentioned second input, above-mentioned first input end electrically connects with above-mentioned scanning BITBUS network, and above-mentioned second input electrically connects with above-mentioned reset BITBUS network; Reference voltage sample circuit, for regulating the output signal of telecommunication of above-mentioned gain amplifier; Output buffer, an input of above-mentioned output buffer electrically connects with the above-mentioned outfan of above-mentioned gain amplifier, for increasing the driving force of the output signal of above-mentioned gain amplifier.

Further, the reference electrical signal of said reference voltage sample circuit is reference voltage, and above-mentioned Vc is identical with said reference voltage.

Further, above-mentioned logic control element includes input pin and output pin, wherein, above-mentioned output pin is end of scan signal pins, when the end of scan, for output pulse signal, above-mentioned input pin includes: Clock Signal pin, for providing a stable frequency signal for above-mentioned logic control element;Scan start signal pin, is used for inputting scan start signal; First chip selects pin, is controlled by the above-mentioned displacement control unit in same above-mentioned detection chip or controlled by the above-mentioned output pin of another the above-mentioned detection chip being connected with above-mentioned detection chip for controlling the startup of the detection signal output of above-mentioned detection chip; Resolution selects pin, for controlling the Thickness sensitivity resolution of above-mentioned detection chip.

Further, above-mentioned detection chip is formed by layer, and said structure rete includes: substrate; And dielectric film, it is arranged on the surface of aforesaid substrate, above-mentioned dielectric film includes contacting the first insulating barrier arranged with aforesaid substrate, and above-mentioned first insulating barrier is oxidation insulating layer, above-mentioned detecting electrode array be arranged on above-mentioned dielectric film away from the surface of aforesaid substrate.

Further, above-mentioned detecting electrode is narrow strip electrode, above-mentioned narrow strip electrode Breadth Maximum in a second direction is less than the Breadth Maximum on third direction, above-mentioned second direction is all vertical with above-mentioned first direction with above-mentioned third direction, and the moving direction that above-mentioned third direction is above-mentioned film to be measured.

Further, at least one above-mentioned detecting electrode includes multiple top electrode and hearth electrode region, above-mentioned hearth electrode region is arranged in above-mentioned dielectric film, above-mentioned hearth electrode region does not contact setting with aforesaid substrate, the surface away from aforesaid substrate of above-mentioned dielectric film offers multiple via, above-mentioned top electrode and above-mentioned via one_to_one corresponding, each above-mentioned top electrode is electrically connected by corresponding via with above-mentioned hearth electrode region.

Further, above-mentioned dielectric film includes: the second insulating barrier, be arranged on above-mentioned first insulating barrier away from the surface of aforesaid substrate; And the 3rd insulating barrier, it is arranged on the surface away from above-mentioned first insulating barrier of above-mentioned second insulating barrier.

Further, above-mentioned hearth electrode region is arranged in above-mentioned 3rd insulating barrier, and multiple above-mentioned vias are opened in the surface away from above-mentioned second insulating barrier of above-mentioned 3rd insulating barrier.

Further, said structure rete also includes: protective layer, covers the exposed surface of each above-mentioned detecting electrode and the exposed surface of above-mentioned dielectric film.

The technical scheme of application the application, detecting device is by detecting electrode array, reset unit, initial amplifying unit, displacement control unit, scanning BITBUS network is integrated in a detection chip with logic control element, the detecting device volume making thickness is less, the problem avoiding the huge detection inconvenience caused of detecting device volume of the prior art, and, this detection chip includes reset unit, before carrying out paper currency detection, namely before detecting the signal of telecommunication of each detecting electrode, the signal of telecommunication of each detecting electrode is resetted by this reset switch array, before avoiding detection, the signal of telecommunication on detecting electrode can affect detected value, and then avoid testing result inaccuracy, improve the accuracy of detection of detecting device.

Accompanying drawing explanation

The Figure of description constituting the part of the application is used for providing further understanding of the present application, and the schematic description and description of the application is used for explaining the application, is not intended that the improper restriction to the application. In the accompanying drawings:

Fig. 1 illustrates the partial structurtes block diagram of the detecting device of a kind of embodiment offer of the application;

Fig. 2 illustrates the local circuit structural representation of the detecting device that the embodiment of the present application 1 provides;

Fig. 3 illustrates the local circuit structural representation of the detecting device that the embodiment of the present application 2 provides;

Fig. 4 illustrates the local circuit structural representation of the detecting device that the embodiment of the present application 3 provides;

Fig. 5 illustrates the part section structural representation of the detection chip of a kind of embodiment offer of the application;

Fig. 6 illustrates the part section structural representation of the detection chip that another embodiment of the application provides;

Fig. 7 illustrates the partial top view of the detection chip that the application another kind embodiment provides;

Fig. 8 illustrates the part section structural representation of the detection chip shown in Fig. 7;

Fig. 9 illustrates the partial top view of the detection chip that the application another embodiment provides;

Figure 10 illustrates the part section structural representation of the detection chip shown in Fig. 9;

Figure 11 illustrates the partial top view of the detection chip that another embodiment of the application provides; And

Figure 12 illustrates the part section structural representation of the detection chip shown in Figure 11.

Wherein, above-mentioned accompanying drawing includes the following drawings labelling:

01, scanning BITBUS network; 011, scanning BITBUS network clamp switch; 02, reset BITBUS network; 021, reset BITBUS network clamp switch; 1, detecting electrode array; 2, the first assembled unit; 3, the second assembled unit; 4, displacement control unit; 11, detecting electrode; 12, dielectric film; 20, reset switch; 30, initial amplifier; 40, shift switching; 41, shift control circuit; 42, the first shift switching; 43, the second shift switching; 50, scanning storage switch; 60, scanning storage electric capacity; 70, reset storage switch; 80, reset storage electric capacity; 91, gain amplifier; 92, reference voltage sample circuit; 93, output buffer; 100, public electrode; 101, substrate; 102, the first insulating barrier; 103, the second insulating barrier; 104, the 3rd insulating barrier; 105, hearth electrode region; 106, via; 107, top electrode; 108, protective layer.

Detailed description of the invention

It it is noted that described further below is all exemplary, it is intended to provide further instruction to the application. Unless otherwise, all technology used herein and scientific terminology have the identical meanings being generally understood that with the application person of an ordinary skill in the technical field.

It should be noted that term used herein above merely to describe detailed description of the invention, and be not intended to the restricted root illustrative embodiments according to the application. As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to include plural form, in addition, it is to be further understood that, when using term " comprising " and/or " including " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.

Introducing as background technology, the detecting device volume of thickness of the prior art is huge and accuracy of detection is relatively low, in order to solve technical problem as above, present applicant proposes the detecting device of a kind of thickness.

In a kind of typical embodiment of the application, provide the detecting device of a kind of thickness, this detecting device includes at least one public electrode 100 and at least one detection chip, this detection chip includes detecting electrode array 1, reset unit, initial amplifying unit, displacement control unit 4, scanning BITBUS network 01 and logic control element, Fig. 1 is the block diagram of local detection chip, this figure merely illustrates detecting electrode array 1, first assembled unit 2, second assembled unit 3 and displacement control unit 4, wherein, first assembled unit 2 includes reset unit and initial amplifying unit, second assembled unit 3 includes logic control element.

Public electrode 100 in this detecting device is for providing a steady electric field when scanning, quantity can be one or more, detection chip can also be one or more, and when public electrode 100 is one, detection chip can be one can also be the multiple of cascade; When public electrode 100 is multiple, detection chip can be the multiple of cascade can also be one. Being no matter one or multiple, all of public electrode 100 need to cover all of detecting electrode array 1. Those skilled in the art can determine the number of detection chip and public electrode 100 according to practical situation.

Wherein, and above-mentioned public electrode 100 is relative in a first direction and interval is arranged for detecting electrode array 1, interval between above-mentioned public electrode 100 and above-mentioned detecting electrode array 1 constitutes the transmission channel of film to be measured, and above-mentioned detecting electrode array 1 includes multiple detecting electrode 11 being arranged in order; Reset unit electrically connects with each above-mentioned detecting electrode 11 in above-mentioned detecting electrode array 1, for being resetted by the signal of telecommunication of each above-mentioned detecting electrode 11; Initial amplifying unit electrically connects with each above-mentioned detecting electrode in above-mentioned detecting electrode array, and above-mentioned initial amplifying unit is for amplifying the signal of telecommunication of each above-mentioned detecting electrode; Displacement control unit 4 electrically connects with above-mentioned initial amplifying unit, and above-mentioned displacement control unit 4 is for controlling the output order of the multiple above-said current signal after amplifying; Scanning BITBUS network 01 includes multiple scanning junction point, and an above-mentioned scanning junction point electrically connects with above-mentioned displacement control unit. Logic control element is for receiving the input signal in the external world, producing the control signal controlling above-mentioned detection chip and output detections signal.

The control signal of public electrode 100 is electrode pulse signal, when scan start signal arrives, (i.e. a high level pulse signal), detection chip is started working, electrode pulse signal is low level, reset unit initializes the voltage (namely resetting) on the detecting electrode 11 that correspondence connects, reset after continuing several clock signals, electrode pulse signal is high level, detecting electrode array 1 starts detection external electrical field change in real time, when bank note is by chip surface, the difference of banknote thickness can affect to the electric field between pulsed electrode and chip detection electrod-array 1, and then cause that detecting electrode 11 power on signal of detecting electrode array 1 changes. the signal of telecommunication on each detecting electrode 11 exports in real time after corresponding primary amplifying unit amplifies, the output valve of each primary amplifier is fed sequentially into scanning BITBUS network 01 by displacement control unit 4, scanning BITBUS network 01 export a line and represent the signal of telecommunication of banknote thickness. detection chip is the signal of telecommunication on high-velocity scanning a line detecting electrode array 1 under the control of logic control element, and scanning multirow can complete the detection of view picture banknote thickness continuously.

Above-mentioned detecting device is by detecting electrode array 1, reset unit, initial amplifying unit, displacement control unit 4, scanning BITBUS network 01 is integrated in a detection chip with logic control element, the detecting device volume making thickness is less, the problem avoiding the huge detection inconvenience caused of detecting device volume of the prior art, and, this detection chip includes reset unit, before carrying out paper currency detection, namely before detecting the signal of telecommunication of each detecting electrode 11, the signal of telecommunication of each detecting electrode 11 is resetted by this reset switch array, before avoiding detection, the signal of telecommunication on detecting electrode 11 can affect detected value, and then avoid testing result inaccuracy, improve the accuracy of detection of detecting device.

In order to amplify by the signal of telecommunication of scanning BITBUS network output further, improve the capacity of resisting disturbance of this signal of telecommunication, the preferred detection chip of the application also includes multi-gain amplification unit, multi-gain amplification unit includes first input end and the second input, above-mentioned first input end scanning junction point above-mentioned with of above-mentioned scanning BITBUS network 01 electrically connects, and also includes multi-gain amplification unit in the second assembled unit 3 in above-mentioned Fig. 1.

In a kind of embodiment of the application, above-mentioned initial amplifying unit is initial amplifier array, above-mentioned initial amplifier array includes multiple initial amplifier 30, above-mentioned initial amplifier 30 and above-mentioned detecting electrode 11 one_to_one corresponding, the input of each above-mentioned initial amplifier 30 electrically connects with corresponding detecting electrode 11. The signal of telecommunication on each detecting electrode 11 exports in real time after corresponding primary amplifier amplifies.

Fig. 2 illustrates the partial structurtes schematic diagram of detecting device, represents the circuit unit being connected with a detecting electrode 11 in rectangular broken line frame, in actual detection chip, including multiple same circuit units. This circuit unit has illustrated an initial amplifier 30 electrically connected with detecting electrode 11.

In the another kind of embodiment of the application, above-mentioned reset unit is reset switch array, above-mentioned reset switch array includes multiple reset switch 20, above-mentioned reset switch 20 and above-mentioned detecting electrode 11 one_to_one corresponding, each above-mentioned reset switch 20 includes reset switch the first end, reset switch the second end and reset switch the 3rd end, each above-mentioned reset switch first terminates fixed voltage (i.e. Vreset in corresponding diagram 2), each above-mentioned reset switch second terminates into reset signal (also referred to as Sr signal), each above-mentioned reset switch the 3rd end electrically connects with corresponding above-mentioned detecting electrode 11, above-mentioned reset signal controls above-mentioned reset switch 20 and connects, the signal of telecommunication of corresponding detecting electrode 11 is resetted.

The control signal of public electrode 100 is electrode pulse signal, when scan start signal arrives, (i.e. a high level pulse signal), detection chip is started working, electrode pulse signal is low level, when reset signal is high level, each reset switch 20 is connected, initialize the signal of telecommunication on the detecting electrode 11 that correspondence connects (namely resetting), reset after continuing several clock signals, electrode pulse signal is high level, when reset signal is low level, each reset switch 20 turns off, detecting electrode array 1 starts detection external electrical field change in real time, when bank note is by chip surface, the difference of banknote thickness can affect to the electric field between pulsed electrode and chip detection electrod-array 1, and then cause that detecting electrode 11 power on signal of detecting electrode array 1 changes. the output valve of each primary amplifier is fed sequentially into scanning BITBUS network 01 by displacement control unit 4, is amplified then through multi-gain amplification unit, and output a line represents the signal of telecommunication of banknote thickness. detection chip is the signal of telecommunication on high-velocity scanning a line detecting electrode array 1 under the control of logic control element, and scanning multirow can complete the detection of view picture banknote thickness continuously.

In the another embodiment of the application, above-mentioned displacement control unit 4 includes: shift switching array and shift control circuit, wherein, shift switching array includes multiple shift switching 40, as shown in Figure 2, above-mentioned shift switching 40 and above-mentioned initial amplifier 30 one_to_one corresponding, each above-mentioned shift switching 40 includes shift switching the first end, shift switching the second end and shift switching the 3rd end, and each above-mentioned shift switching the first end electrically connects with the outfan of corresponding initial amplifier 30;Shift control circuit 41 electrically connects with above-mentioned shift switching second end of each above-mentioned shift switching 40, and above-mentioned shift control circuit 41 is for controlling the on and off of each above-mentioned shift switching 40.

When detecting electrode array 1 starts detection external electrical field change in real time, bank note passes through chip surface, the difference of banknote thickness can affect to the electric field between pulsed electrode and chip detection electrod-array 1, and then causes that detecting electrode 11 power on signal of detecting electrode array 1 changes. Shift control circuit 41 controls each shift switching 40 and in turn switches on, and the output valve of each primary amplifier is fed sequentially into scanning BITBUS network 01, is amplified then through multi-gain amplification unit and carries out follow-up work.

" above-mentioned reset switch 20 and above-mentioned detecting electrode 11 one_to_one corresponding " mentioned above represents that the number of reset switch 20 in reset switch array is identical with the number of detecting electrode 11, and reset switch 20 connects one to one with detecting electrode 11. The every similar statement of the application, all represents that the number of the two is identical, and one_to_one corresponding.

Further, shift switching 40 mentioned above is all MOSFET with reset switch 20, and other switch mentioned in the application, when not having specified otherwise, is all MOSFET. But above-mentioned all of switch is not limited to MOSFET, those skilled in the art can select suitable switch according to practical situation.

In a kind of embodiment of the application, above-mentioned detection chip also includes scanning storage switch array and scanning storage capacitor array, wherein, scanning storage switch array includes multiple scanning storage switch 50, above-mentioned scanning storage switch 50 and above-mentioned initial amplifier 30 one_to_one corresponding, each above-mentioned scanning storage switch 50 includes scanning storage switch the first end, scanning storage switch the second end and scanning storage switch the 3rd end, each above-mentioned scanning storage switch the first end electrically connects with the outfan of corresponding initial amplifier 30, each above-mentioned scanning storage switch second terminates into scanning switch signal (also referred to as St signal), scanning storage capacitor array includes multiple scanning storage electric capacity 60, each above-mentioned scanning storage electric capacity 60 includes scanning capacitance the first end and scanning capacitance the second end, above-mentioned scanning storage electric capacity 60 and above-mentioned scanning storage switch 50 one_to_one corresponding, each above-mentioned scanning capacitance the first end is connected electrically between scanning storage switch the 3rd end and above-mentioned shift switching first end of corresponding shift switching 40 of correspondence, each above-mentioned scanning capacitance the second end ground connection, each above-mentioned scanning storage electric capacity 60 is for storing the corresponding initial amplifier 30 output signal of telecommunication when the detecting electrode 11 that scanning is corresponding. Fig. 3 illustrates the partial structurtes schematic diagram of this detecting device, represents the circuit unit being connected with a detecting electrode 11 in rectangular broken line frame, in actual detecting device, including multiple same circuit units.

After voltage amplitude on detecting electrode 11, electrode pulse signal is high level, reset signal is low level, when scanning switch signal is high level, each reset switch 20 turns off, and detecting electrode array 1 starts detection external electrical field change in real time, when bank note is by chip surface, the difference of banknote thickness can affect to the electric field between pulsed electrode and chip detection electrod-array 1, and then causes that detecting electrode 11 power on signal of detecting electrode array 1 changes. The signal of telecommunication on each detecting electrode 11 exports in real time after corresponding primary amplifier amplifies, after the voltage of output being stored to corresponding scanning storage electric capacity 60, scanning switch signal is low level, namely scanning storage switch array disconnects, shift control circuit 41 controls each shift switching 40 and in turn switches on, storage value in each scanning storage electric capacity 60 is fed sequentially into scanning BITBUS network 01, is amplified then through multi-gain amplification unit.Detection chip arranges scanning storage capacitor array and scanning storage switch array, sequential read out again after the signal of telecommunication detected on each detecting electrode 11 can be stored simultaneously, avoid the deviation that scanning limit, limit reading manner produces, further increase the accuracy of detection of detecting device.

In order to before the storage voltage reading scanning storage electric capacity 60 every time, current potential clamper to one fixed value by scanning BITBUS network 01, avoid scanning BITBUS network 01 parasitic capacitance impact on accuracy of detection, and then improve the accuracy of detection of detecting device further, the preferred detection chip of the application also includes scanning BITBUS network clamp switch 011, it includes scanning clamp switch the first end, scanning clamp switch the second end and scanning clamp switch the 3rd end, each above-mentioned scanning clamp switch the first end is connected electrically between above-mentioned scanning BITBUS network 01 and the above-mentioned first input end of above-mentioned multi-gain amplification unit, each above-mentioned scanning clamp switch the 3rd terminates into fixed voltage Vc, each above-mentioned scanning clamp switch second terminates into clamp switch signal (also referred to as Sc signal), before the signal of telecommunication reading each above-mentioned scanning storage electric capacity 60, above-mentioned clamp switch signal controls above-mentioned scanning BITBUS network clamp switch 011 and connects, by the voltage clamp of above-mentioned scanning BITBUS network 01 to voltage Vc. further, clamp switch signal is contrary with the signal of shift control circuit 41, and namely when clamp switch signal control scanning BITBUS network clamp switch 011 is connected, shift control circuit 41 controls each shift switching 40 and turns off.

In the another embodiment of the application, as, in Fig. 2 and Fig. 3, above-mentioned multi-gain amplification unit includes gain amplifier 91, reference voltage sample circuit 92 and output buffer 93. Wherein, gain amplifier 91 includes two inputs and an outfan, two inputs corresponding above-mentioned first input ends and above-mentioned second inputs respectively, and above-mentioned first input end electrically connects with above-mentioned scanning BITBUS network 01; Reference voltage sample circuit 92 electrically connects with above-mentioned second input, and said reference voltage sample circuit 92 is for regulating the output signal of telecommunication of above-mentioned gain amplifier 91; The input of above-mentioned output buffer 93 electrically connects with the above-mentioned outfan of above-mentioned gain amplifier 91, for increasing the driving force of the output signal of above-mentioned gain amplifier 91, the detection signal (i.e. SIG signal) of its outfan output detections chip. Output valve on scanning BITBUS network 01 can be amplified by this multi-gain amplification unit, and regulates the benchmark of output valve, and the scope making the output signal of gain amplifier 91 is more adjustable, facilitates the reading of follow-up multiple read module. Such as, testing jobbie, the reference voltage being applied to gain amplifier 91 is 1V, and the output area of gain amplifier 91 is 1 to 1.5V, tests same object, is applied to the reference voltage of gain amplifier 91 when being 2V, and amplifier output area is 2 to 2.5V.

In the another embodiment of the application, above-mentioned shift switching array includes multipair shift switching, multipair above-mentioned shift switching and multiple above-mentioned initial amplifier 30 one_to_one corresponding, every pair of shift switching includes two shift switchings, being the first shift switching 42 and the second shift switching 43 respectively, each above-mentioned first shift switching 42 includes first shift switching the first end, first shift switching the second end and the first shift switching the 3rd end; Each above-mentioned second shift switching 43 includes second shift switching the first end, second shift switching the second end and the second shift switching the 3rd end, wherein, each above-mentioned first shift switching the first end electrically connects with corresponding scanning capacitance the first end, each above-mentioned first shift switching the 3rd end electrically connects with above-mentioned scanning BITBUS network 01, and each above-mentioned first shift switching the second end electrically connects with above-mentioned shift control circuit 41.Fig. 4 illustrates the partial structurtes schematic diagram of this detecting device, represents the circuit unit being connected with a detecting electrode 11 in rectangular broken line frame, in actual detecting device, including multiple same circuit units.

And above-mentioned detection chip also includes reset storage switch array, reset storage capacitor array and reset BITBUS network 02. Wherein, reset storage switch array includes multiple reset storage switch 70, above-mentioned reset storage switch 70 and above-mentioned initial amplifier 30 one_to_one corresponding, each above-mentioned reset storage switch 70 includes reset storage switch the first end, reset storage switch the second end and reset storage switch the 3rd end, each above-mentioned reset storage switch the first end electrically connects with the outfan of above-mentioned initial amplifier 30, and each above-mentioned reset storage switch second terminates into reset switch signal (also referred to as Sd signal); The storage capacitor array that resets includes multiple storage electric capacity 80 that resets, above-mentioned reset storage electric capacity 80 and above-mentioned reset storage switch 70 one_to_one corresponding, each above-mentioned reset storage electric capacity 80 includes reset capacitance the first end and reset capacitance the second end, above-mentioned reset capacitance the first end is connected electrically between reset storage switch the 3rd end and second corresponding shift switching first end of correspondence, above-mentioned reset capacitance the second end ground connection, each above-mentioned reset storage electric capacity 80 is for storing the corresponding initial amplifier 30 output signal of telecommunication when resetting corresponding detecting electrode 11; Reset BITBUS network 02 includes multiple reset junction point, one above-mentioned reset junction point is connected electrically in the 3rd end of each above-mentioned second shift switching and above-mentioned second input of above-mentioned multi-gain amplification unit, or an above-mentioned reset junction point electrically connects with each above-mentioned second shift switching the 3rd end, and another above-mentioned reset junction point electrically connects with above-mentioned second input of above-mentioned multi-gain amplification unit.

Electrode pulse signal is low level, when reset signal is high level, several clock cycle connected by each reset switch 20, the signal of telecommunication on detecting electrode 11 is resetted, when reset switch signal high level, reset storage switch 70 disconnects after connecting several clock cycle, the output signal of each initial amplifier 30 stores to corresponding reset storage electric capacity 80, reset signal is low level, electrode pulse signal is high level, when scanning switch signal is high level, each reset switch 20 turns off, detecting electrode array 1 starts to detect external electrical field change, after some clock cycle, scanning switch signal high level, the scanning voltage of initial amplifier 30 output stores in scanning storage electric capacity 60, shift control circuit 41 controls a pair shift switching successively and connects, voltage in scanning storage electric capacity 60 is electrically connected with the first input end of multi-gain amplification unit, electrically connected with the second input of multi-gain amplification unit by the signal of telecommunication resetted in storage electric capacity 80 simultaneously, therefore, each scanning storage electric capacity 60 voltage is amplified after deducting corresponding each storage electric capacity 80 signal of telecommunication that resets, eliminate the discreteness between each unit circuit, improve Thickness sensitivity precision further.

In order to before the storage voltage reading the storage electric capacity 80 that resets every time, by the current potential clamper of reset BITBUS network 02 to fixed value, avoid the impact on accuracy of detection of reset BITBUS network 02 parasitic capacitance, and then improve the accuracy of detection of detecting device further, the preferred above-mentioned detection chip of the application also includes reset BITBUS network clamp switch 021, this reset BITBUS network clamp switch 021 includes reduction forceps bit switch the first end, reduction forceps bit switch the second end and reduction forceps bit switch the 3rd end, above-mentioned reduction forceps bit switch the first end is connected electrically between above-mentioned reset BITBUS network 02 and above-mentioned second input of above-mentioned multi-gain amplification unit, above-mentioned reduction forceps bit switch the 3rd terminates into fixed voltage Vc, above-mentioned reduction forceps bit switch second terminates into above-mentioned clamp switch signal, before the signal of telecommunication reading each above-mentioned reset storage electric capacity 80, above-mentioned clamp switch signal controls above-mentioned reset BITBUS network clamp switch 021 and connects, by the voltage clamp of above-mentioned reset BITBUS network 02 to voltage Vc.

In another embodiment of the application, as shown in Figures 2 to 4, above-mentioned multi-gain amplification unit includes: gain amplifier 91, reference voltage sample circuit 92 and output buffer 93. Wherein, gain amplifier 91 includes two inputs and an outfan, two input corresponding above-mentioned first input ends respectively and above-mentioned second input, above-mentioned first input end electrically connects with above-mentioned scanning BITBUS network 01, and above-mentioned second input electrically connects with above-mentioned reset BITBUS network 02; Reference voltage sample circuit 92 is for regulating the output signal of telecommunication of above-mentioned gain amplifier 91; The input of above-mentioned output buffer 93 electrically connects with the above-mentioned outfan of above-mentioned gain amplifier 91, for increasing the driving force of the output signal of above-mentioned gain amplifier 91.

The reference electrical signal of said reference voltage sample circuit is reference voltage, and above-mentioned Vc can be identical with said reference voltage, it is also possible to differs with it. In order to initialize gain amplifier 91, the output voltage of balancing gain amplifier 91, it is preferable that above-mentioned Vc is generally identical with the reference voltage in said reference voltage sample circuit 92.

In the another kind of embodiment of the application, above-mentioned logic control element includes input pin and output pin, and wherein, above-mentioned output pin is end of scan signal pins, when the end of scan, for output pulse signal. Above-mentioned input pin includes: Clock Signal pin, scan start signal pin, the first chip select pin to select pin with resolution.

Wherein, Clock Signal pin, for providing a stable frequency signal for above-mentioned logic control element, is the clock benchmark of above-mentioned detection chip offer work, and half clock signal period is the least unit of each signalizing activity in logic control element.

Scan start signal pin is used for inputting scan start signal, inputs the high level pulse signal of a clock cycle, can start detection chip and start the scanning of a line on scan start signal pin; first chip selects pin to be controlled by the above-mentioned displacement control unit in same above-mentioned detection chip or controlled by the above-mentioned output pin of another the above-mentioned detection chip being connected with above-mentioned detection chip for controlling the startup of the detection signal output of above-mentioned detection chip, when above-mentioned detection device only includes an above-mentioned detection chip, above-mentioned detection signal exports immediately under the control of displacement control unit, when above-mentioned detection device includes multiple above-mentioned detection chip, first chip detection pin of second detection chip and later detection chip is connected with the end of scan signal pins of a upper detection chip, the output of the detection signal of second detection chip and later detection chip starts the end of scan signal by a upper detection chip and controls, namely after the detection signal end of output of first detection chip, end of scan signal pins occurring, a high level pulse selects pin to the first chip of second detection chip, second detection chip starts output detections signal, the like, until the detection signal of all chips has exported. resolution selects pin for controlling the Thickness sensitivity resolution of above-mentioned detection chip.

The signal of telecommunication of the application does not have specified otherwise to refer both to voltage signal. But be not restricted to that voltage signal, in different situations, this voltage signal can also be current signal etc. The above-mentioned signal of telecommunication can be set to concrete voltage or current signal by those skilled in the art according to specific circumstances.

In another embodiment of the application, as shown in figs. 5 and 6, above-mentioned detection chip is formed by layer, said structure rete includes substrate 101 and dielectric film 12, wherein, dielectric film 12 is arranged on the surface of aforesaid substrate 101, and above-mentioned dielectric film 12 includes contacting the first insulating barrier 102 arranged with aforesaid substrate 101, above-mentioned first insulating barrier 102 is oxidation insulating layer, and above-mentioned detecting electrode array 1 is arranged on the surface away from aforesaid substrate 101 of above-mentioned dielectric film 12.

Above-mentioned detecting electrode is also one layer in layer, the integrated testing circuit in detection chip is also formed by layer, the layer forming testing circuit not only includes substrate and dielectric film, also include the layer that other those skilled in the art know, just no longer elaborate here.

In order to reduce the area of this detecting electrode 11 further, and then reduce its acceptable capacity, voltage reset speed on detecting electrode 11 during raising scanning, and then improve the response speed of whole detecting device, as illustrated in figs. 7 and 8, the preferred above-mentioned detecting electrode 11 of the application is narrow strip electrode. And Breadth Maximum that above-mentioned narrow strip electrode is in a second direction is all vertical with above-mentioned first direction less than the Breadth Maximum on third direction, above-mentioned second direction and above-mentioned third direction, and the moving direction that above-mentioned third direction is above-mentioned film to be measured.

In the another kind of embodiment of the application, as shown in Fig. 9 to Figure 12, at least one above-mentioned detecting electrode 11 includes multiple top electrode 107 and hearth electrode region 105, above-mentioned hearth electrode region 105 is arranged in above-mentioned dielectric film 12, above-mentioned hearth electrode region 105 does not contact setting with aforesaid substrate 101, the surface away from aforesaid substrate 101 of above-mentioned dielectric film 12 offers multiple via 106, above-mentioned top electrode 107 and above-mentioned via 106 one_to_one corresponding, each above-mentioned top electrode 107 is electrically connected by corresponding via 106 with above-mentioned hearth electrode region 105. The top electrode 107 of this structure is equivalent to a big top electrode 107 and is divided into strip (cuboid) or square (square) array, add the contact area of detecting electrode and external electrical field, improve detecting electrode 11 sensitivity further.

Shown in Fig. 7, Fig. 9 or Figure 11, detecting electrode 11 or hearth electrode region 105 are not strict cuboid or square, but have a kick in one side, kick is beneficial to charge concentration, it is simple to carry out being electrically connected with other structure. This kick can also not have, and those skilled in the art can arrange detecting electrode or the shape in hearth electrode region according to practical situation.

In order to be further ensured that the detecting electrode 11 Yi Zhixing in producing preparation, as shown in Fig. 6, Fig. 8, Figure 10 and Figure 12, the preferred above-mentioned dielectric film 12 of the application includes the second insulating barrier 103 and the 3rd insulating barrier 104, wherein, the second insulating barrier 103 is arranged on the surface away from aforesaid substrate 101 of above-mentioned first insulating barrier 102; 3rd insulating barrier 104 is arranged on the surface away from above-mentioned first insulating barrier 102 of above-mentioned second insulating barrier 103.

In the another embodiment of the application, such as Figure 10 or Figure 12, (structure of the detection chip of Figure 10 and Figure 12 differs itself, but, sectional structure chart is identical) shown in, above-mentioned hearth electrode region 105 is arranged in above-mentioned 3rd insulating barrier 104, and multiple above-mentioned vias 106 are opened on the surface away from above-mentioned second insulating barrier 103 of above-mentioned 3rd insulating barrier 104.

In order to protect detecting electrode 11 not affected by extraneous factor; as shown in Fig. 6, Fig. 8, Figure 10 and Figure 12; the preferred above-mentioned detection chip of the application also includes protective layer 108, and this protective layer 108 covers the exposed surface of each above-mentioned top electrode 107 and the exposed surface of above-mentioned dielectric film 12.

The structure of each above-mentioned detecting electrode 11 may apply in above-mentioned different detection chip. Detecting electrode 11 in detection chip according to specific circumstances, can be set to suitable structure by those skilled in the art.

In this detecting device, detection chip is IC chip, and its preparation can be realized by integrated circuit technology, just repeats no more herein.

So that those skilled in the art can clearly understand the technical scheme of the application, below with reference to specific embodiment, the technical scheme of the application is illustrated.

Embodiment 1

This detecting device includes a public electrode 100 and a detection chip. Wherein, detection chip includes detecting electrode array 1, reset switch array, initial amplifier array, shift switching array, shift control circuit 41, scanning BITBUS network 01, multi-gain amplification unit and logic control element. The rectangular broken line frame of Fig. 2 illustrate only the element circuit corresponding with a detecting electrode 11, total these type of element circuits multiple in detection chip.

Wherein, and above-mentioned public electrode 100 is relative and interval is arranged for detecting electrode array 1, interval between above-mentioned public electrode 100 and each above-mentioned detecting electrode array 1 constitutes the transmission channel of film to be measured, and detecting electrode array 1 includes multiple same detection electrodes 11 of equidistant a line arrangement; A corresponding reset switch 30, the shift switching 40 of 20, initial amplifier of each detecting electrode 11 shown in Fig. 2, shift control circuit 41, multi-gain amplification unit and logic control element. Shift control circuit 41 controls each shift switching 40 and opens successively and shutoff; Multi-gain amplification unit is made up of with output buffer 93 gain amplifier 91, reference voltage sample circuit 92.

The input pin of logic control circuit has clock signal CLK pin (also referred to as CLK pin), scan start signal FS pin (also referred to as FS pin), the first chip to select SI pin (also referred to as SI pin) to select MODE pin (also referred to as MODE pin) with resolution. wherein, SI pin is for controlling the startup of the detection signal output of above-mentioned detection chip, when above-mentioned detection device only includes an above-mentioned detection chip, SI pin connects high level, above-mentioned detection signal exports immediately under the control of shift control circuit 41, when above-mentioned detection device includes multiple above-mentioned detection chip, SI pin connects the SO pin of a detection chip, the output of the detection signal of second detection chip and later detection chip starts the end of scan signal by a upper detection chip and controls, namely after the detection signal end of output of first detection chip, end of scan signal pins occurring, a high level pulse selects pin to the first chip of second detection chip, second detection chip starts output detections signal, the like, until the detection signal of all chips has exported. MODE pin is that resolution selects pin, this pin low and high level or pulse input can select the mode of operation of detecting electrode array 1, during highest resolution, all detecting electrodes 11 work alone, during low resolution, adjacent detecting electrode 11 is by rule merging work, and the Thickness resolution of this detection chip can reach 200DPI at present. CLK signal is clock input pin, outside provide clock signal to this detection chip. one pulse signal of the output SO pin of logic control circuit represents that a line scanning output procedure completes.

The sampling benchmark of reference voltage sample circuit 92 is provided by VREF pin, VREF voltage is also the second input of gain amplifier 91 simultaneously, as the benchmark comparing amplification, multi-gain amplification unit eventually passes through output buffer 93 by output signal SIG pin output.

This detecting device a line scanning work sequential is as follows, the high level pulse (scan start signal) of scan start signal FS pin one clock cycle of input, detection chip work can be started, electrode pulse signal is low level, and reset signal (Sr signal) for high level time, reset switch array is connected several clock cycle, disconnects after initializing the voltage on detecting electrode array 1, electrode pulse signal is high level, when Sr signal is low level, detecting electrode array 1 starts detection external electrical field change in real time, when now bank note is by chip surface, the difference of banknote thickness can affect to the electric field between each detecting electrode 11 in public electrode 100 and detecting electrode array 1, and then cause the change of voltage on each detecting electrode 11, on each detecting electrode 11, the change of voltage exports in real time after corresponding primary amplifier amplifies, shift control circuit 41 controls shift switching array and in turn switches on, the output of primary amplifier array is fed sequentially into scanning BITBUS network 01, differential amplification is carried out with reference voltage successively then through gain amplifier 91, finally, export a line through output buffer 93 and represent the magnitude of voltage of banknote thickness. detection chip is the voltage on high-velocity scanning a line detecting electrode array 1 under the driving of clock signal, and scanning multirow can complete the detection of view picture banknote thickness continuously. it is capable of the high resolution detection to banknote thickness by this example, and volume is little, less costly.

Embodiment 2

Detecting device is on the basis of the detecting device of embodiment 1. Detection chip adds scanning storage switch array, scanning storage capacitor array, scanning BITBUS network clamp switch 011, the rectangular broken line frame of Fig. 3 illustrate only the element circuit being connected with a detecting electrode 11, compare with Fig. 2, this circuit increase only a scanning storage switch 50, scanning storage electric capacity 60 and scanning BITBUS network clamp switch 011, total these type of element circuits multiple in this detection chip; Before reading each scanning storage electric capacity 60, scanning BITBUS network clamp switch 011 is connected, and to Vc, Vc and reference voltage, the voltage clamp of scanning BITBUS network 01 is drawn VREF foot isoelectric level.

The sequential of this detecting device a line scanning work is as follows, the high level pulse (i.e. scan start signal) of scan start signal FS pin one clock cycle of input starts detection chip work, when electrode pulse signal is low level, when reset signal (Sr signal) is for high level, several clock signal periods connected by each reset switch 20, disconnect after the voltage on the initial each detecting electrode 11 of correspondenceization; Electrode pulse signal is high level, and Sr signal is low level, and when scanning switch signal is high level, each detecting electrode 11 starts detection external electrical field change in real time, and the detection voltage on each detecting electrode 11 is amplified by corresponding initial amplifier 30 array in real time; After some clock signal periods, scanning switch signal (St signal) controls scanning storage switch array and connects, being stored by the voltage that initial amplifier 30 array amplifies in the scanning storage electric capacity 60 of correspondence, then, St signal controls scanning storage switch 50 and turns off. Shift control circuit 41 controls each shift switching 40 and in turn switches on, voltage on scanning storage electric capacity 60 is fed sequentially into scanning BITBUS network 01, voltage on scanning BITBUS network 01 is sequentially carried out differential amplification through gain amplifier 91 and reference voltage, eventually passes output buffer 93 and exports a line voltage signal.This embodiment adopts scanning storage capacitor array, detection chip a line is detected after voltage stores simultaneously and sequential reads out again, avoid the deviation that scanning limit, limit reading manner produces, and before reading scanning capacitance voltage every time, clamp switch signal (Sc signal) controls scanning BITBUS network clamp switch 011 and connects, make scanning BITBUS network 01 be clamped to Vc, reduce the impact that BITBUS network parasitic capacitance causes, improve scanning accuracy.

Embodiment 3

With the detecting device of embodiment 2 the difference is that, detection chip adds reset storage switch array, reset storage capacitor array, reset BITBUS network 02 and reset BITBUS network clamp switch 021, the rectangular broken line frame of Fig. 4 illustrate only the element circuit being connected with a detecting electrode 11, total these type of element circuits multiple in detection chip; Compared with Fig. 3, adding 43, reset storage switch of second shift switching 70, reset storage electric capacity 80, reset BITBUS network 02 and reset BITBUS network clamp switch 021 in this figure, reset BITBUS network 02 is connected to the second input of gain amplifier 91. Reset BITBUS network clamp switch 021, for before reading each storage electric capacity 80 that resets by reset BITBUS network 02 clamper to Vc, clamp switch signal (Sc signal) controls break-make while of reset BITBUS network clamp switch 021 and scanning BITBUS network clamp switch 011. The first shift switching 42 and the second shift switching 43 in the present embodiment are also turned on by shift control circuit 41, are disconnected, for the voltage of the voltage of scanning storage electric capacity 60 and the storage electric capacity 80 that resets being sent to scanning BITBUS network 01 and reset BITBUS network 02 simultaneously.

Its a line scanning work sequential is as follows, the high level pulse (i.e. scan start signal) of scan start signal FS pin one clock cycle of input, can work by bootrom, electrode pulse signal is low level, and Sr signal is high level, reset switch array connects several clock signal periods, initialize the voltage on corresponding each detecting electrode 11, Sd signal controls reset storage switch array and connects, the storage capacitor array that resets stores the amplification voltage of now each initial amplifier 30, reset storage switch 70 disconnects subsequently, and each reset switch 20 disconnects. Electrode pulse signal is high level, and Sr signal is low level, and St signal is high level, and detecting electrode array 1 starts detection external electrical field change in real time, and the detection voltage on each detecting electrode 11 is amplified by initial amplifier 30 array in real time; After some clock pulse signals, scanning storage switch array is connected, and the voltage now amplified by each initial amplifier 30 is stored along in corresponding each scanning storage electric capacity 60, and scanning storage switch array turns off.

When now scanning storage capacitor array storage electrode pulse signal is high level, the scanning voltage of initial amplifier 30 array output, when the storage capacitor array storage electrode pulse signal that resets is low level, the resetting voltage of the initial amplifier 30 array output of electricity. Shift control circuit 41 controls shift switching array and in turn switches on, and is delivered concurrently on scanning BITBUS network 01 and reset BITBUS network 02 by the voltage on scanning storage electric capacity 60 and the voltage resetted on storage electric capacity 80 successively; Before every pair of shift switching 40 is connected, Sc signal can be controlled by logic control circuit, and then control clamp switch and connect, will scanning BITBUS network 01 and reset BITBUS network 02 voltage clamper simultaneously to Vc. Voltage on scanning BITBUS network 01 is sequentially carried out differential amplification with the voltage on reset BITBUS network 02 through gain amplifier 91, finally, exports a line voltage signal through output buffer 93.

This embodiment adopts the storage capacitor array that resets, initial amplifier 30 voltage under each unit circuit storage reset state, when subsequent gain is amplified, scanning storage electric capacity 60 voltage of each unit circuit is amplified after deducting reset storage electric capacity 80 voltage, eliminate the discreteness between each unit circuit, improve Thickness sensitivity further.

As can be seen from the above description, the application the above embodiments achieve following technique effect:

The detecting device of the application is by detecting electrode array, reset unit, initial amplifying unit, displacement control unit, scanning BITBUS network is integrated in a detection chip with logic control element, the detecting device volume making thickness is less, the problem avoiding the huge detection inconvenience caused of detecting device volume of the prior art, and, this detection chip includes reset unit, before carrying out paper currency detection, namely before detecting the signal of telecommunication of each detecting electrode, the signal of telecommunication of each detecting electrode is resetted by this reset switch array, before avoiding detection, the signal of telecommunication on detecting electrode can affect detected value, and then avoid testing result inaccuracy, improve the accuracy of detection of detecting device.

The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations. All within spirit herein and principle, any amendment of making, equivalent replacement, improvement etc., should be included within the protection domain of the application.

Claims

1. the detecting device of a thickness, it is characterised in that described detecting device includes at least one public electrode and at least one detection chip, and wherein, each described detection chip includes:

Detecting electrode array, and described public electrode is relative in a first direction and interval is arranged, and the interval between described public electrode and described detecting electrode array constitutes the transmission channel of film to be measured, and described detecting electrode array includes multiple detecting electrode;

Reset unit, electrically connects with each described detecting electrode in described detecting electrode array, for being resetted by the signal of telecommunication of each described detecting electrode;

Initial amplifying unit, electrically connects with each described detecting electrode in described detecting electrode array, and described initial amplifying unit is for amplifying the signal of telecommunication of each described detecting electrode;

Displacement control unit, electrically connects with described initial amplifying unit, and described displacement control unit is for controlling the output order of the multiple described signal of telecommunication after amplifying;

Scanning BITBUS network, including multiple scanning junction points, a described scanning junction point electrically connects with described displacement control unit; And

Logic control element, for receiving the input signal in the external world, producing the control signal controlling described detection chip and output detections signal.

2. detecting device according to claim 1, it is characterised in that each described detection chip also includes:

Multi-gain amplification unit, including first input end and the second input, described first input end and a described scanning junction point electrical connection.

3. detecting device according to claim 2, it is characterized in that, described initial amplifying unit is initial amplifier array, described initial amplifier array includes multiple initial amplifier, described initial amplifier and described detecting electrode one_to_one corresponding, the input of each described initial amplifier electrically connects with corresponding detecting electrode.

4. detecting device according to claim 3, it is characterized in that, described reset unit is reset switch array, described reset switch array includes multiple reset switch, described reset switch and described detecting electrode one_to_one corresponding, each described reset switch includes reset switch the first end, reset switch the second end and reset switch the 3rd end, each described reset switch first terminates into fixed voltage, each described reset switch second terminates into reset signal, each described reset switch the 3rd end electrically connects with corresponding detecting electrode, described reset signal controls described reset switch and connects, the signal of telecommunication of corresponding described detecting electrode is resetted.

5. detecting device according to claim 4, it is characterised in that described displacement control unit includes:

Shift switching array, including multiple shift switchings, described shift switching and described initial amplifier one_to_one corresponding, each described shift switching includes shift switching the first end, shift switching the second end and shift switching the 3rd end, and each described shift switching the first end electrically connects with the outfan of corresponding initial amplifier;And

Shift control circuit, electrically connects with each described shift switching the second end, and described shift control circuit is for controlling the on and off of each described shift switching.

6. detecting device according to claim 5, it is characterised in that described detection chip also includes:

Scanning storage switch array, including multiple scanning storage switchs, described scanning storage switch and described initial amplifier one_to_one corresponding, each described scanning storage switch includes scanning storage switch the first end, scanning storage switch the second end and scanning storage switch the 3rd end, each described scanning storage switch the first end electrically connects with the outfan of corresponding initial amplifier, and each described scanning storage switch second terminates into scanning switch signal; And

Scanning storage capacitor array, including multiple scanning storage electric capacity, described scanning storage electric capacity includes scanning capacitance the first end and scanning capacitance the second end, described scanning storage electric capacity and described scanning storage switch one_to_one corresponding, each described scanning capacitance the first end is connected electrically between scanning storage switch the 3rd end and corresponding shift switching first end of correspondence, each described scanning capacitance the second end ground connection, each described scanning storage electric capacity is for storing the corresponding initial amplifier output signal of telecommunication when the detecting electrode that scanning is corresponding.

7. detecting device according to claim 6, it is characterised in that described detection chip also includes:

Scanning BITBUS network clamp switch, including scanning clamp switch the first end, scanning clamp switch the second end and scanning clamp switch the 3rd end, described scanning clamp switch the first end is connected electrically between described scanning BITBUS network and described first input end, described scanning clamp switch second terminates into clamp switch signal, described scanning clamp switch the 3rd terminates into fixed voltage Vc, before the signal of telecommunication reading each described scanning storage electric capacity, described clamp switch signal controls described scanning BITBUS network clamp switch and connects, by the voltage clamp of described scanning BITBUS network to voltage Vc.

8. the detecting device according to any one of claim 2 to 7, it is characterised in that described multi-gain amplification unit includes:

Gain amplifier, including two inputs and an outfan, two input corresponding described first input ends respectively and described second input, described first input end electrically connects with described scanning BITBUS network;

Reference voltage sample circuit, electrically connects with described second input, and described reference voltage sample circuit is for regulating the output signal of telecommunication of described gain amplifier; And

Output buffer, the input of described output buffer electrically connects with the described outfan of described gain amplifier, for increasing the driving force of the output signal of described gain amplifier.

9. detecting device according to claim 7, it is characterized in that, described shift switching array includes multipair shift switching, multipair described shift switching and multiple described initial amplifier one_to_one corresponding, every pair of shift switching includes two shift switchings, being the first shift switching and the second shift switching respectively, each described first shift switching includes first shift switching the first end, first shift switching the second end and the first shift switching the 3rd end; Each described second shift switching includes second shift switching the first end, second shift switching the second end and the second shift switching the 3rd end, wherein, each described first shift switching the first end electrically connects with corresponding scanning capacitance the first end, each described first shift switching the 3rd end electrically connects with described scanning BITBUS network, each described first shift switching the second end electrically connects with described shift control circuit, and described detection chip also includes:

Reset storage switch array, including multiple reset storage switchs, described reset storage switch and described initial amplifier one_to_one corresponding, each described reset storage switch includes reset storage switch the first end, reset storage switch the second end and reset storage switch the 3rd end, each described reset storage switch the first end electrically connects with the outfan of corresponding initial amplifier, and each described reset storage switch second terminates into reset switch signal;

Reset storage capacitor array, including multiple storage electric capacity that reset, described storage electric capacity and the described reset storage switch one_to_one corresponding of resetting, each described storage electric capacity that resets includes reset capacitance the first end and reset capacitance the second end, each described reset capacitance the first end is connected electrically between reset storage switch the 3rd end and second corresponding shift switching first end of correspondence, each described reset capacitance the second end ground connection, each described storage electric capacity that resets is for storing the corresponding initial amplifier output signal of telecommunication when resetting corresponding detecting electrode; And

Reset BITBUS network, including multiple reset junction points, a described reset junction point is connected electrically in each described second shift switching the 3rd end and described second input, or

One described reset junction point electrically connects with each described second shift switching the 3rd end, and another described reset junction point electrically connects with described second input.

10. detecting device according to claim 9, it is characterised in that described detection chip also includes:

Reset BITBUS network clamp switch, including reduction forceps bit switch the first end, reduction forceps bit switch the second end and reduction forceps bit switch the 3rd end, described reduction forceps bit switch the first end is connected electrically between described reset BITBUS network and described second input, described reduction forceps bit switch second terminates into described clamp switch signal, described reduction forceps bit switch the 3rd terminates into fixed voltage Vc, before the signal of telecommunication reading each described storage electric capacity that resets, described clamp switch signal controls described reset BITBUS network clamp switch and connects, by the voltage clamp of described reset BITBUS network to voltage Vc.

11. detecting device according to claim 10, it is characterised in that described multi-gain amplification unit includes:

Gain amplifier, including two inputs and an outfan, two input corresponding described first input ends respectively and described second input, described first input end electrically connects with described scanning BITBUS network, and described second input electrically connects with described reset BITBUS network;

Reference voltage sample circuit, for regulating the output signal of telecommunication of described gain amplifier; And

12. detecting device according to claim 11, it is characterised in that the reference electrical signal of described reference voltage sample circuit is reference voltage, and described Vc is identical with described reference voltage.

13. detecting device according to claim 1, it is characterised in that described logic control element includes input pin and output pin, wherein, described output pin is end of scan signal pins, when the end of scan, for output pulse signal, described input pin includes:

Clock Signal pin, for providing a stable frequency signal for described logic control element;

Scan start signal pin, is used for inputting scan start signal;

First chip selects pin, is controlled by the described displacement control unit in same described detection chip or controlled by the described output pin of another the described detection chip being connected with described detection chip for controlling the startup of the detection signal output of described detection chip; And

Resolution selects pin, for controlling the Thickness sensitivity resolution of described detection chip.

14. detecting device according to claim 1, it is characterised in that described detection chip is formed by layer, described layer includes:

Substrate;And

Dielectric film, it is arranged on the surface of described substrate, described dielectric film includes contacting the first insulating barrier arranged with described substrate, and described first insulating barrier is oxidation insulating layer, and described detecting electrode array is arranged on the surface away from described substrate of described dielectric film.

15. detecting device according to claim 14, it is characterized in that, described detecting electrode is narrow strip electrode, described narrow strip electrode Breadth Maximum in a second direction is less than the Breadth Maximum on third direction, described second direction is all vertical with described first direction with described third direction, and the moving direction that described third direction is described film to be measured.

16. detecting device according to claim 14, it is characterized in that, at least one described detecting electrode includes multiple top electrode and hearth electrode region, described hearth electrode region is arranged in described dielectric film, described hearth electrode region does not contact setting with described substrate, the surface away from described substrate of described dielectric film offers multiple via, described top electrode and described via one_to_one corresponding, and each described top electrode is electrically connected by corresponding via with described hearth electrode region.

17. the detecting device according to claim 16, it is characterised in that described dielectric film includes:

Second insulating barrier, is arranged on the surface away from described substrate of described first insulating barrier; And

3rd insulating barrier, is arranged on the surface away from described first insulating barrier of described second insulating barrier.

18. detecting device according to claim 17, it is characterised in that described hearth electrode region is arranged in described 3rd insulating barrier, and multiple described vias are opened in the surface away from described second insulating barrier of described 3rd insulating barrier.

19. the detecting device according to any one of claim 14 to 18, it is characterised in that described layer also includes:

Protective layer, covers the exposed surface of each described detecting electrode and the exposed surface of described dielectric film.