CN105655268B - The recycling method of DRAM bad crystal grains - Google Patents
The recycling method of DRAM bad crystal grains Download PDFInfo
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- CN105655268B CN105655268B CN201610015283.6A CN201610015283A CN105655268B CN 105655268 B CN105655268 B CN 105655268B CN 201610015283 A CN201610015283 A CN 201610015283A CN 105655268 B CN105655268 B CN 105655268B
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000004064 recycling Methods 0.000 title claims abstract description 11
- 239000013078 crystal Substances 0.000 title abstract description 5
- 238000012360 testing method Methods 0.000 claims abstract description 17
- 238000005259 measurement Methods 0.000 claims abstract description 4
- 238000012986 modification Methods 0.000 claims description 8
- 230000004048 modification Effects 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 238000005538 encapsulation Methods 0.000 claims description 6
- 230000002950 deficient Effects 0.000 abstract description 3
- 238000011990 functional testing Methods 0.000 abstract description 2
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 239000002245 particle Substances 0.000 abstract 1
- 239000002699 waste material Substances 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 13
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 102220030763 rs1385129 Human genes 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67282—Marking devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67271—Sorting devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67294—Apparatus for monitoring, sorting or marking using identification means, e.g. labels on substrates or labels on containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Abstract
A kind of recycling method of DRAM bad crystal grains, to basic unit of storage functional test during On-Wafer Measurement, the distribution situation of defective region is recorded, screens identical bad type B in advance, half capacity crystal grain of corresponding types is only picked out when encapsulating, avoids useless crystal grain from being packaged.Special nation's line mode is used simultaneously（Wire Bonding）, and change ATE test program and packaged chip particle is targetedly tested.Its advantage is that cost is low, compatible strong, meanwhile, by recycling half capacity chip, product output rate can be improved, increases enterprise income.Reduce the waste of the packaging cost of half, only need to be tested for a kind of half capacity model in test, save testing cost and be up to 75%.
Description
Technical field
The present invention relates to DRAM dynamic RAMs, the recycling method of the bad chips of more particularly to DRAM.
Background technology
DRAM（Dynamic Random Access Memory dynamic RAMs）Memory chip is by DRAM wafers
On chip package form, several different types of chips are usually contained in single-wafer（die）--- non-defective unit chip, technique prison
Control chip and bad chip.Under normal circumstances, non-defective unit chip can be cut encapsulation and carry out follow-up chip testing, process monitoring
Chip and bad chip can then go out of use and do harmless treatment.Bad chip refers to be unable to base because of partial circuit existing defects
This meets the chip (circuit unit) of the feature of device or design specification book.But the damage circuit of most bad chips only accounts for
The very small part of whole circuit area, this then to be screened for the progress functional test of partial circuit block with regard to screening out half
The available product of memory capacity provides possibility.
Bad chip proportion can reach 10% ~ 20% or so in ripe DRAM products wafer, with DDR3 4Gb
Exemplified by DRAM products, by analysis the bad chip on wafer have more than half ratio still have the unit of 2Gb capacity be it is available,
Therefore it will be that enterprise brings considerable income to recycle this segment chip.
The content of the invention
For the missing of prior art, it is an object of the invention to provide a kind of recycling side of the bad chips of DRAM
Method.
The technical solution adopted for the present invention to solve the technical problems is：The recovery for providing a kind of bad chips of DRAM is sharp again
With method, it is characterised in that comprise the following steps：
1) during On-Wafer Measurement, the address realm to fail is occurred according to normal full capacity test process, to every core
Piece makes preliminary classification, and in Wafer alignment figure（Wafer Mapping）Every chips are made a mark；
2) in chip paster（Die Bond）When the crawl of the chip of the capacity of same type half is attached to by Wafer alignment figure
On same substrate, and different classes of chip is placed respectively；
3) each type of half capacity chip is directed to, particularly customized corresponding special nation's line mode, allows corresponding address line to exist
Chip internal is forced to be connected to low level or high level；
4) the capacity chip development test program of all kinds half, the definition of modification test program pin, address realm, survey are directed to
Vectorial access profile is tried, control test program fixes the access of half capacity to chip；
5) chip after encapsulation is completed, final chip testing is completed by customizing test program, filters out real half capacity
Parameter, function, speed chip up to standard are as final finished.
The beneficial effects of the invention are as follows：Cost is low, compatible strong, meanwhile, by recycling half capacity chip, can improve
Product output rate, increase enterprise income.
Brief description of the drawings
Fig. 1 is DRAM memory cell addressing scheme；
Fig. 2 is traditional standard DRAM nations line schematic diagram；
Fig. 3 is the address wire nation line modification schematic diagram that capacity halves；
Fig. 4 is traditional DRAM production methods schematic flow sheet；
The recycling method flow schematic diagram of the bad chips of Fig. 5 DRAM of the present invention.
Embodiment
A kind of recycling embodiment of the method for the bad chips of DRAM of the present invention, it is characterised in that comprise the following steps：
1) during upper wafer factory On-Wafer Measurement, there is the address failed according in normal full capacity test process
Scope, every chips are made with preliminary classification, half good chip of a Bin left sides：A15=0 half capacity is qualified, half good chip of the Bin right sides：
A15=1 half capacity is qualified ... in Wafer alignment figure（Wafer Mapping）Every chips are made a mark；
2) factory is encapsulated in chip paster（Die Bond）When the chip of the capacity of same type half is grabbed by Wafer alignment figure
Take and be attached on same substrate, different classes of chip is placed respectively；
3) each type of half capacity chip is directed to, particularly customized corresponding special nation's line mode, allows corresponding address line to exist
Chip internal is forced to be connected to the grounding pin of substrate or is connected to the power pins of substrate；
4) be directed to the capacity chip development test program of all kinds half, the definition of modification test program pin, address realm,
Test vector access profile, so as to control test program to fix the access of half capacity to chip；
5) chip after encapsulation is completed, final chip testing is completed by customizing test program, filters out real half capacity
Parameter, function, speed chip up to standard are as final finished.
The capacity PCB of standard half is used on memory modules, for example, if half capacity chip is 2Gb, then uses 2Gb pairs of standard
The pcb board answered, for final module and system, use and the general memory of the internal memory are no different.
The present invention is tested for the original packing forms of holding, multiple combinations that industry is commonly used, modification module PCB way is deposited
The defects of, propose for chip package test improved method, chip package mode is made an amendment, and pass through method of testing
Adjustment, the capacity using dram chip needed for very inexpensive completion halve recycling.
According to the definition of JEDEC standard, DRAM addressing is conducted interviews by appropriate address pin input address information.Such as
Shown in Fig. 1, by taking DDR3 4Gb chips as an example, address pin includes the Bank addresses of BA0 ~ BA2 controls and the row of A0 ~ A15 controls
Column address, therefore the nation's line mode for encapsulating Plays is by said function interface corresponding to substrate and wafer by metal lead wire
Bonding wire point（bond pad）Link together.
The method of the present invention has broken conventional standard practice, nation's line mode of self-defined address wire change addressing system so as to
Realize chip capacity control.As shown in Figure 2 left half good chip can be produced for different address nation line modification modes（H1 it is), right
Half good chip (H2), the good chip (H5) of upper half, good chip (H6) the various combination Bin of lower half half capacity chip.It is good for a left side half
Chip, it is always low level that A15 nations line point is changed to be directly grounded VSS to limit A15 from substrate A15 inputs, therefore is controlled
Chip can only conduct interviews to left half of memory block；Right half good chip is then that A15 meets voltage source VDD and then realized right half part is visited
Ask；For the good chip of Bin upper half/good chip of Bin lower half, then be by BA2 nations line point no longer connect input and be directly grounded VSS and
Power vd D, so as to realize access limitation of the chip to the first half and lower half.As long as in upper wafer supplier's wafer sort
During realize half capacity chip of respective classes at selection markers, can targetedly chooses various cores in encapsulation process
Piece completes encapsulation.
First, the method for testing of modification makes test program supporting for left half good chip/right side with corresponding special nation's line product
For half good chip, because signal input part has been no longer attached on chip on substrate, so must in chip testing program
Must be by A15 pin input signal by original address input end（ADDRESS pin）It is adjusted to be not connected to hold（NC pin）.Together
When be fixed to 0 by the A15 row addresses controlled, therefore maximum addressable row（X）Address must halve, such as with
DDR3 4Gb are changed to 0x7FFF from original 0xFFFF.
2nd, halve for the Bank numbers of the good chip actual access of the good chip/lower half of upper half, except modification BA2 pins
Test condition is by original address input end（ADDRESS pin）Reset to and be not connected to hold（NC pin）, will also be to test vector
（pattern）The bank accessed modifies, and the bank that shielding half will not be accessed, avoids same bank by continuous 2
The read-write of secondary complementary logic causes to test the situation of logic error.
Claims (1)
- A kind of 1. recycling method of the bad chips of DRAM, it is characterised in that comprise the following steps：1) during On-Wafer Measurement, the address realm to fail is occurred according to normal full capacity test process, every chips are done Go out preliminary classification, and every chips are made a mark in Wafer alignment figure；2) the chip crawl of the capacity of same type half is attached on same substrate by Wafer alignment figure in chip paster, and Different classes of chip is placed respectively；3) each type of half capacity chip is directed to, special nation's line mode corresponding to customization, allows corresponding address line in chip internal Pressure is connected to low level or high level;Special nation's line mode, it can be produced for different address nation line modification modes Half good chip of a raw left side（H1), right half good chip (H2), the good chip (H5) of upper half, the half of good chip (H6) the various combination Bin of lower half Capacity chip；For left half good chip, by the good chip of upper half（A15）Nation's line point from its（A15）Input is changed to be directly grounded VSS；Right half good chip is then（A15）Meet voltage source VDD；Then it is by it for the good chip of Bin upper half/good chip of Bin lower half （BA2）Nation's line point no longer connects input and is directly grounded VSS and power vd D；4) include for the left half good good chip in chip/right side half, by it（A15 pin）Input signal is by original address input end （ADDRESS pin）It is adjusted to be not connected to hold（NC pin）；It is then changed for the good chip of the good chip/lower half of upper half（BA2）Draw The test condition of pin is by original address input end（ADDRESS pin）Reset to and be not connected to hold（NC pin）, to test vector （pattern）The bank accessed modifies, the bank that shielding half will not be accessed；5) complete the chip after encapsulation, final chip testing completed by customizing test program, filter out real half capacity parameter, Function, speed chip up to standard are as final finished.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610015283.6A CN105655268B (en) | 2016-01-08 | 2016-01-08 | The recycling method of DRAM bad crystal grains |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610015283.6A CN105655268B (en) | 2016-01-08 | 2016-01-08 | The recycling method of DRAM bad crystal grains |
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| Publication Number | Publication Date |
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| CN105655268A CN105655268A (en) | 2016-06-08 |
| CN105655268B true CN105655268B (en) | 2018-03-27 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110993522A (en) * | 2019-12-19 | 2020-04-10 | 华天科技（西安）有限公司 | A method for derating of inferior 3D NAND |
| EP4084052A4 (en) * | 2020-01-19 | 2022-11-30 | Huawei Technologies Co., Ltd. | Wafer to wafer structure and test method therefor, and high bandwidth memory and manufacturing method therefor |
| CN114121117B (en) * | 2021-11-30 | 2025-04-15 | 深圳市嘉合劲威电子科技有限公司 | A method, device and equipment for repairing single crystal memory |
| CN114121123B (en) * | 2021-11-30 | 2025-05-06 | 深圳市嘉合劲威电子科技有限公司 | A method and device for repairing dual-crystal memory using single-crystal memory |
Citations (3)
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|---|---|---|---|---|
| CN1577630A (en) * | 2003-07-30 | 2005-02-09 | 因芬尼昂技术股份公司 | Semiconductor circuit and method for testing, monitoring and application-near setting of a semiconductor circuit |
| CN1763863A (en) * | 2004-10-20 | 2006-04-26 | 杨朝雨 | Method and device for utilizing defective memory |
| CN101246741A (en) * | 2007-02-16 | 2008-08-20 | 深圳市芯邦微电子有限公司 | System, device, method and packaging structure using flaw memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7120513B1 (en) * | 1997-06-06 | 2006-10-10 | Micron Technology, Inc. | Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as repairs, to select procedures the ICS will undergo, such as additional repairs |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1577630A (en) * | 2003-07-30 | 2005-02-09 | 因芬尼昂技术股份公司 | Semiconductor circuit and method for testing, monitoring and application-near setting of a semiconductor circuit |
| CN1763863A (en) * | 2004-10-20 | 2006-04-26 | 杨朝雨 | Method and device for utilizing defective memory |
| CN101246741A (en) * | 2007-02-16 | 2008-08-20 | 深圳市芯邦微电子有限公司 | System, device, method and packaging structure using flaw memory |
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| CN105655268A (en) | 2016-06-08 |
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