CN105645348A - Production method for MEMS silicon film - Google Patents
Production method for MEMS silicon film Download PDFInfo
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- CN105645348A CN105645348A CN201410693991.6A CN201410693991A CN105645348A CN 105645348 A CN105645348 A CN 105645348A CN 201410693991 A CN201410693991 A CN 201410693991A CN 105645348 A CN105645348 A CN 105645348A
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- etching
- silicon fiml
- dioxide layer
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- mems
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 95
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 95
- 239000010703 silicon Substances 0.000 title claims abstract description 95
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 90
- 238000005530 etching Methods 0.000 claims abstract description 54
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 45
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 45
- 238000001039 wet etching Methods 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims description 38
- 238000001020 plasma etching Methods 0.000 claims description 32
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 14
- 238000009616 inductively coupled plasma Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000001035 drying Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 238000013517 stratification Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- Micromachines (AREA)
- Pressure Sensors (AREA)
Abstract
The invention discloses a production method for an MEMS silicon film. According to the production method, a silicon dioxide layer is used as an auto-stopping layer, and a method combining drying etching with wet etching is used, thus the silicon film with accurate thickness and size can be produced, and meanwhile the size of the device is also greatly reduced.
Description
Technical field
The present invention relates to technical field of semiconductor device, particularly to the manufacture method of a kind of MEMS silicon fiml.
Background technology
A lot of MEMS are required for using silicon fiml. Such as, MEMS Piezoresistive Pressure Sensor is made up of the stress sensitive pressure drag on silicon fiml and silicon fiml, changes pressure drag resistance when silicon fiml deforms under pressure, can be obtained the change of pressure by bridge measurement change in resistance. The size of silicon fiml and thickness directly determine the sensitivity of device. How to prepare size and the accurate silicon fiml of thickness has become one of MEMS exploitation and practical key technology, thus develop the technology of preparing of multiple silicon fiml. Preparing the simplest technology of silicon fiml is that the silicon chip being directly hundreds of microns by thickness carries out KOH or TMAH and etches, and deducts the degree of depth of etching with silicon wafer thickness and just can obtain the thickness of silicon fiml. When etching into required thickness, silicon chip is taken out from etching liquid. Though this technology is very simple, but has disadvantages that. Such as, initiate the in uneven thickness of silicon chip, thus the thickness of gained silicon fiml will be had a huge impact. If silicon chip exists impurity gradient or defect, the zones of different at silicon chip also can be caused to have different etch rates, also result in size and the thickness inaccuracy of silicon fiml. Meanwhile, there is very big error in silicon wafer thickness and measuring of etching depth. So using this technology, it is difficult to obtain thickness and the accurate silicon fiml of size. In addition, the etch chamber that KOH etching or TMAH etch out is inverted trapezoidal, and making an equal amount of silicon fiml needs the extra space increasing device.
Summary of the invention
Based on this, it is necessary to provide the manufacture method of a kind of MEMS silicon fiml, the manufacture method of this MEMS silicon fiml can be effectively improved the thickness of silicon fiml and the precision of size.
A kind of manufacture method of MEMS silicon fiml, including step:
Substrate and substrate are provided;
Silicon dioxide layer is deposited in substrate face;
By substrate by described silicon dioxide layer and substrate bonding;
Substrate is carried out front thinning;
Plasma etching is carried out to make etched area at substrate back;
Described etched area is carried out wet etching, and stops etching at silicon dioxide layer, thus obtaining MEMS silicon fiml.
Wherein in an embodiment, described at substrate face deposit silicon dioxide layer, including: deposit silicon dioxide layer in substrate face by chemical vapor deposition method.
Wherein in an embodiment, the thickness of described silicon dioxide layer is 100nm��2000nm.
Wherein in an embodiment, described plasma etching includes: inductively coupled plasma etching.
Wherein in an embodiment, described wet etching includes: utilize KOH or TMAH to carry out wet etching.
Wherein in an embodiment, described described etched area is carried out wet etching, and stop etching at silicon dioxide layer, thus the step obtaining MEMS silicon fiml includes: described etched area is carried out wet etching, and time in the bottom surface etching into silicon dioxide layer or silicon dioxide layer, stop etching, thus obtaining MEMS silicon fiml.
Wherein in an embodiment, described silicon fiml and described etched area are all squares, and the silicon fiml length of side is L1, and the etched area length of side is L2, and substrate thickness is D;
Then depth H 2=(the L2-L1) �� tan (180 �� of-��) of described wet etching, the depth H 1=D-H2 of plasma etching, wherein obtuse angle alpha is by angled by sidewall and the bottom of wet etching inverted trapezoidal structure etch chamber out.
Wherein in an embodiment, obtuse angle alpha is 124 degree��128 degree.
Wherein in an embodiment, obtuse angle alpha is 126 degree.
The manufacture method of above-mentioned MEMS silicon fiml, the method that using plasma etching and wet etching combine, first with plasma etching etching, substrate back is performed etching, because the etch chamber that plasma etching is etched out is vertical stratification, and can ratio more uniform and be accurately controlled etching depth, so so that thickness and the size of silicon fiml can both control comparatively accurate, and size of devices can be reduced in subsequent etching.
If but using plasma etching etches into silicon dioxide layer always, then due to plasma etching etch into silicon dioxide layer time, due to the silicon dioxide layer effect of reflection to etching ion, the etching sidewall bottom of ion bom bardment etch chamber of reflection also forms recess, and the rotten phenomenon ratio in side is more serious.
Therefore after plasma etching certain depth, before etching into silicon dioxide layer, then employing wet etching is changed, then owing to wet etching is slow to the etch rate of silicon dioxide layer, without corruption phenomenon in side occurs, it is possible to produce the accurate silicon fiml of size. Owing to above already by a plasma etching etching part, although now adopting wet etching also to there will be inverted trapezoidal structure again, but now the impact of device having been lacked many compared with traditional method, size of devices is less than traditional method. Further, the etch rate of wet etching can be slow, and etching depth is controlled can be relatively good, thus under the etched surface etching uniform ground through above plasma etching, it is possible to well control the thickness of silicon fiml, improve the precision of silicon film thickness. And, silicon dioxide layer is as the self-stopping technology layer of subsequent etching (wet etching), when being so possible to prevent follow-up silicon etching, occurs that overetch causes final silicon film thickness to change.
Accompanying drawing explanation
Fig. 1 is the flow chart of the manufacture method of an embodiment MEMS silicon fiml;
Fig. 2 be substrate is carried out front thinning after schematic diagram;
Fig. 3 carries out plasma etching with the schematic diagram after making etched area at substrate back;
Etched area is carried out wet etching the schematic diagram after silicon dioxide layer stops etching by Fig. 4.
Detailed description of the invention
For the ease of understanding the present invention, below with reference to relevant drawings, the present invention is described more fully. Accompanying drawing gives presently preferred embodiments of the present invention. But, the present invention can realize in many different forms, however it is not limited to embodiment described herein. On the contrary, the purpose providing these embodiments is to make the understanding to the disclosure more thorough comprehensively.
Unless otherwise defined, all of technology used herein is identical with the implication that the those skilled in the art belonging to the present invention are generally understood that with scientific terminology. The term used in the description of the invention herein is intended merely to the purpose describing specific embodiment, it is not intended that the restriction present invention.Term as used herein "and/or" includes the arbitrary and all of combination of one or more relevant Listed Items.
MEMS (MicroElectroMechanicalSystems, microelectromechanical systems) utilizes ic manufacturing technology and micro-processing technology that micro structure, microsensor, microactrator, control are processed circuit even interface, communicates and power supply etc. manufactures the miniature integrated system on one or more chip. Along with the development of MEMS technology, the pressure transducer that MEMS technology makes is utilized to be widely used in the various fields such as auto industry, biomedicine, Industry Control, the energy and semi-conductor industry.
A lot of MEMS are required for using silicon fiml. Such as, MEMS Piezoresistive Pressure Sensor is made up of the stress sensitive pressure drag on silicon fiml and silicon fiml, changes pressure drag resistance when silicon fiml deforms under pressure, can be obtained the change of pressure by bridge measurement change in resistance. The size of silicon fiml and thickness directly determine the sensitivity of device. How to prepare size and the accurate silicon fiml of thickness has become one of MEMS exploitation and practical key technology, thus develop the technology of preparing of multiple silicon fiml. Preparing the simplest technology of silicon fiml is that the silicon chip being directly hundreds of microns by thickness carries out KOH or TMAH and etches, and deducts the degree of depth of etching with silicon wafer thickness and just can obtain the thickness of silicon fiml. When etching into required thickness, silicon chip is taken out from etching liquid. Though this technology is very simple, but has disadvantages that. Such as, initiate the in uneven thickness of silicon chip, thus the thickness of gained silicon fiml will be had a huge impact. If silicon chip exists impurity gradient or defect, the zones of different at silicon chip also can be caused to have different etch rates, also result in size and the thickness inaccuracy of silicon fiml. Meanwhile, there is very big error in silicon wafer thickness and measuring of etching depth. So using this technology, it is difficult to obtain thickness and the accurate silicon fiml of size. In addition, the etch chamber that KOH etching or TMAH etch out is inverted trapezoidal, and making an equal amount of silicon fiml needs the extra space increasing device.
At present, plasma etching is also widely used in the preparation of silicon fiml. Plasma etching can save the space of device, for instance the area of chip. But when plasma etching to oxide layer, due to the oxide layer reflection to etching ion, cause that the rotten ratio in side is more serious, thus affecting the size of silicon fiml. And when wet etching etches into oxide layer, owing to wet etching is slow to the etch rate of silicon dioxide layer, then do not have side corruption phenomenon. The present invention adopts the method that silicon dioxide layer combines as self-stopping technology layer, dry etching and wet etching, it is possible to prepares thickness and the accurate silicon fiml of size, also significantly reduces the size of device simultaneously, for instance reduce the area of chip.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 1 is the flow chart of the manufacture method of an embodiment MEMS silicon fiml.
A kind of manufacture method of MEMS silicon fiml, including step:
Step S100: substrate 100 and substrate 300 are provided. Substrate 100 and substrate 300 are silicon material.
Step S200: deposit silicon dioxide layer 200 in substrate 100 front. In substrate 100 front by chemical vapor deposition (CVD, ChemicalVaporDeposition) technique deposit layer of silicon dioxide layer 200. The thickness of silicon dioxide layer 200 is 100nm��2000nm, and for as self-stopping technology layer, last wet etching will stop at this silicon dioxide layer 200.
Step S300: substrate 100 is bonded by silicon dioxide layer 200 and substrate 300.
Step S400: substrate 300 is carried out front thinning. See Fig. 2, Fig. 2 be substrate is carried out front thinning after schematic diagram.
Step S500: carry out plasma etching at substrate 100 back side to make etched area 110. See that Fig. 3, Fig. 3 carry out plasma etching with the schematic diagram after making etched area at substrate back. The shape of etched area 110 can be square can also be rectangle, is square in the present embodiment, it is assumed that the length of side of etched area 110 is L2. The silicon fiml made is also for square, and the silicon fiml length of side is L1, sees Fig. 4. Plasma etching can adopt inductively coupled plasma etching technique (ICP, InductivelyCoupledPlasma).
Step S600: etched area 110 is carried out wet etching, and stops etching at silicon dioxide layer 200, thus obtaining MEMS silicon fiml. Specifically, utilize KOH or TMAH to carry out wet etching, and time in the bottom surface etching into silicon dioxide layer 200 or silicon dioxide layer 200, stop etching, thus obtaining MEMS silicon fiml. Generally, just stop by accurately calculating the bottom surface that can etch into silicon dioxide layer 200, but just stop etching when being not excluded for calculating inaccuracy and etching in silicon dioxide layer 200. Etched area is carried out wet etching the schematic diagram after silicon dioxide layer stops etching by Fig. 4.
To those skilled in the art, it is easy to know that the etch chamber that wet etching etches out is inverted trapezoidal structure, the sidewall of this inverted trapezoidal structure and bottom are the obtuse angle alpha of about 126 degree. In various wet etchings, the change of this obtuse angle alpha is little, substantially all between 124 degree��128 degree, for instance 124 degree, 125 degree, 126 degree, 127 degree or 128 degree, generally at about 126 degree. Therefore, when the foursquare silicon fiml needing one length of side of making to be L1, the length of side L2 of foursquare etched area 110 is determined by practical situation, just can calculate the desired depth H2 of wet etching according to this obtuse angle alpha, thus the depth H 1 needed for plasma etching can also be calculated according to the thickness D of substrate.
Such as, H2=(L2-L1) �� tan (180 �� of-��) �� (L2-L1)/1.414. Obtuse angle alpha presses 126 degree of calculating, calculates in order to convenient, it is possible to directly take formula H2=(L2-L1)/1.414, it is allowed to there is rational error. Thus, the depth H 1=D-H2 needed for plasma etching. Assume to need to make the foursquare silicon fiml that the length of side is 500 microns, the length of side of foursquare etched area 110 is 600 microns, substrate thickness D is 400 microns, obtuse angle alpha presses 126 degree of calculating, then desired depth H2=(600-5001) �� tan (180 �� of-��) �� (600-500)/1.414 �� 70 microns, the depth H 1=D-H2 �� needed for plasma etching 330 microns of wet etching.
Certainly, can also by computed as above for a length of side when silicon fiml and etched area are rectangle.
The manufacture method of above-mentioned MEMS silicon fiml, the method that using plasma etching and wet etching combine, first with plasma etching etching, substrate back is performed etching, because the etch chamber that plasma etching is etched out is vertical stratification, and can ratio more uniform and be accurately controlled etching depth, so so that thickness and the size of silicon fiml can both control comparatively accurate, and size of devices can be reduced in subsequent etching.
If but using plasma etching etches into silicon dioxide layer always, then due to plasma etching etch into silicon dioxide layer time, due to the silicon dioxide layer effect of reflection to etching ion, the etching sidewall bottom of ion bom bardment etch chamber of reflection also forms recess, and the rotten phenomenon ratio in side is more serious.
Therefore after plasma etching certain depth, before etching into silicon dioxide layer, then employing wet etching is changed, then owing to wet etching is slow to the etch rate of silicon dioxide layer, without corruption phenomenon in side occurs, it is possible to produce the accurate silicon fiml of size.Owing to above already by a plasma etching etching part, although now adopting wet etching also to there will be inverted trapezoidal structure again, but now the impact of device having been lacked many compared with traditional method, size of devices is less than traditional method. Further, the etch rate of wet etching can be slow, and etching depth is controlled can be relatively good, thus under the etched surface etching uniform ground through above plasma etching, it is possible to well control the thickness of silicon fiml, improve the precision of silicon film thickness. And, silicon dioxide layer is as the self-stopping technology layer of subsequent etching (wet etching), when being so possible to prevent follow-up silicon etching, occurs that overetch causes final silicon film thickness to change.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention. It should be pointed out that, for the person of ordinary skill of the art, without departing from the inventive concept of the premise, it is also possible to making some deformation and improvement, these broadly fall into protection scope of the present invention. Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (9)
1. the manufacture method of a MEMS silicon fiml, it is characterised in that include step:
Substrate and substrate are provided;
Silicon dioxide layer is deposited in substrate face;
By substrate by described silicon dioxide layer and substrate bonding;
Substrate is carried out front thinning;
Plasma etching is carried out to make etched area at substrate back;
Described etched area is carried out wet etching, and stops etching at silicon dioxide layer, thus obtaining MEMS silicon fiml.
2. the manufacture method of MEMS silicon fiml according to claim 1, it is characterised in that described at substrate face deposit silicon dioxide layer, including: deposit silicon dioxide layer in substrate face by chemical vapor deposition method.
3. the manufacture method of MEMS silicon fiml according to claim 1, it is characterised in that the thickness of described silicon dioxide layer is 100nm��2000nm.
4. the manufacture method of MEMS silicon fiml according to claim 1, it is characterised in that described plasma etching includes: inductively coupled plasma etching.
5. the manufacture method of MEMS silicon fiml according to claim 1, it is characterised in that described wet etching includes: utilize KOH or TMAH to carry out wet etching.
6. the manufacture method of MEMS silicon fiml according to claim 1, it is characterized in that, described described etched area is carried out wet etching, and stop etching at silicon dioxide layer, thus the step obtaining MEMS silicon fiml includes: described etched area is carried out wet etching, and time in the bottom surface etching into silicon dioxide layer or silicon dioxide layer, stop etching, thus obtaining MEMS silicon fiml.
7. the manufacture method of MEMS silicon fiml according to claim 1, it is characterized in that, described silicon fiml and described etched area are all squares, the silicon fiml length of side is L1, the etched area length of side is L2, and substrate thickness is D, then depth H 2=(the L2-L1) �� tan (180 �� of-��) of described wet etching, the depth H 1=D-H2 of plasma etching, wherein obtuse angle alpha is by angled by sidewall and the bottom of wet etching inverted trapezoidal structure etch chamber out.
8. the manufacture method of MEMS silicon fiml according to claim 7, it is characterised in that obtuse angle alpha is 124 degree��128 degree.
9. the manufacture method of MEMS silicon fiml according to claim 8, it is characterised in that obtuse angle alpha is 126 degree.
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| CN201410693991.6A CN105645348A (en) | 2014-11-26 | 2014-11-26 | Production method for MEMS silicon film |
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| CN201410693991.6A CN105645348A (en) | 2014-11-26 | 2014-11-26 | Production method for MEMS silicon film |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108128749A (en) * | 2017-12-21 | 2018-06-08 | 中国电子科技集团公司第四十八研究所 | Diaphragm for current vortex micro-pressure sensor and preparation method thereof |
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