CN105633268A - Superconducting circuit structure and preparation method thereof - Google Patents

Abstract

The invention provides a superconducting circuit structure and a preparation method thereof. The preparation method comprises steps of 1) providing a substrate, and forming a stress pattern structure in a position, in which a Josephson junction is going to be formed, corresponding to the surface of the substrate, wherein the size of the stress pattern structure is larger than that of the Josephson junction; 2) successively forming three layers of thin film structures including a first superconducting material layer, a first insulation material layer and a second superconducting layer on the surface of the substrate; 3) etching the three layers of the thin film structures so as to form a bottom electrode and the Josephson junction; 4) forming a second insulation material layer on the surface of a structure obtained in the step 3) and forming a first opening in a position corresponding to the Josephson junction of the second insulation material layer; and 5) depositing and etching the third superconducting material layer so as to form a wire distributing layer. By forming the stress pattern structure under the Josephson junction, wherein the size of the stress patter structure is larger than that of the Josephson junction, effective releasing of stress in the Josephson junction is facilitated, so leakage current is avoided and performance and stability of the superconducting circuit structure are improved.

Description

A kind of superconducting circuit structure and preparation method thereof

technical field

The invention relates to the technical field of superconducting circuit design, in particular to a superconducting circuit structure and a preparation method thereof.

Background technique

Superconducting circuit structures include superconducting quantum interference devices (SQUIDs), single flux quantum devices (SFQs) and other circuits using superconducting Josephson junctions.

Superconducting quantum interference device (superconducting quantum interference device, SQUID) is a superconducting quantum device based on the Josephson effect and the principle of magnetic flux quantization. Its basic structure is to insert two Josephson junctions in a superconducting ring. SQUID is the most Sensitive magnetic flux detection sensor, the magnetic flux noise of a typical SQUID device is on the order of μΦ ₀ /Hz ^1/2 (1Φ ₀ =2.07×10 ^-15 Wb), and its magnetic field noise is on the order of fT/Hz ^1/2 ( 1fT=1×10 ^-15 T), because of its extremely high sensitivity, it can be widely used in various aspects such as medical cardiology and brain magnetism, material detection, earth's magnetic field, military affairs, earthquake and archaeology, and the magnetic flux microscope prepared with it Can be engaged in basic research.

Single Flux Quantum (Single Flux Quantum, SFQ) is a superconducting circuit technology that uses a single flux quantum in a Josephson junction to represent logic "1" and "0". The clock frequency of the superconducting digital circuit based on this can reach 770GHz, which can be used in ultra-wideband analog-to-digital/digital-to-analog converters for radar and communication systems, broadband network switches, digital autocorrelators for radio astronomy, and superconducting computers, etc. . Because of its advantages of fast speed and low power consumption, the United States and Japan have invested heavily in strategic research.

In the concept of quantum mechanics, when two metals are separated by a thin layer of insulator, a current can flow between the metals. Usually, this "metal-insulator-metal" stack is called a tunnel junction. The flowing current is called tunneling current. If, in this laminated sandwich structure, one or two metals are superconductors, it is called a superconducting tunnel junction. According to the Josephson effect, in a superconducting tunnel junction, the insulating layer has some properties of a superconductor, but has weaker superconductivity compared with conventional superconductors, and is called a "weakly connected superconductor".

As shown in Figure 1, it is a schematic structural diagram of a Josephson junction (JosephsonJunction) 11, including a first superconducting material layer 111, a second superconducting material layer 113, and a junction between the first superconducting material layer 111 and the second The first insulating material layer 112 between the superconducting material layers 113, wherein the thickness of the first insulating material layer 112 is very thin, usually a few to ten nanometers thick.

The superconducting circuit structure is generally composed of Josephson junctions 11 and some resistors, inductors, etc., with three or more layers of superconducting material and more than two layers of insulating material. Partial structural schematic diagrams of existing superconducting circuit structures are shown in Figures 2 to 3, wherein Figure 2 is a partial top view structural schematic diagram of a superconducting circuit structure, and Figure 3 is a cross-sectional structural schematic diagram of Figure 2; from Figure 2 to Figure 3 3, it can be seen that the Josephson junction 11 is connected to devices such as inductors through the wiring layer 14 and the conductive via 13. Due to the integration of superconducting physics and microelectronics technology, the design of superconducting circuits is more complicated, and the influence of small variables needs to be considered, including inductance size matching, resistance size and resistance value, thickness of each layer of film, and metal-insulated metal. capacitance etc. The performance of the Josephson junction composed of superconducting insulating superconducting is very critical. If the process is not well controlled, leakage current is more likely to occur. Leakage currents usually originate from interlayer and side edges. The side leakage current can be solved by covering with insulating layer. The leakage current between layers comes from the holes, compactness and stress of the insulating layer in the Josephson junction. Its porosity and compactness can be resolved by adjusting the deposition conditions of the insulating layer. The stress part has always been the direction of research efforts. Most researchers focus on how to reduce the stress of the film itself.

The preparation method of a typical superconducting device is as follows: first, a three-layer thin film of superconductor-insulating material layer-superconductor structure is prepared on the substrate; then, the bottom electrode is etched on the three-layer film; then, in the design of the Josephson junction position to prepare a Josephson junction; then deposit SiO or SiO ₂ insulating material layer on the surface of the device and prepare holes on the insulating material layer for the deposition of the next superconducting film, or use the lift-off method on the Josephson junction Holes are prepared; the shunt resistance of the Josephson junction in the SQUID device is deposited again; finally, the wiring layer is deposited and an etching process is performed to lead out the top electrode of the Josephson junction. When applying the lift-off process (lift-off) to prepare Josephson junctions or when applying the drilling process, first make the bottom electrode and then define the junction area. Usually, a larger Josephson junction is used to connect the interlayer channel, because the larger junction has higher critical current. As shown in Fig. 2 and Fig. 3, it is respectively the top view structure schematic diagram and the cross-sectional structure schematic diagram of the single-channel superconducting connection structure prepared by the above method, and the superconducting circuit structure includes: a substrate 10; Forest junction 11, the Josephson junction 11 includes a bottom electrode 114 located on the surface of the substrate 10, a first insulating material layer 112 located on the surface of the bottom electrode 114, and a layer of insulating material located on the surface of the first insulating material layer 112. Top electrode 115; the second insulating material layer 12 located on the surface of the substrate 10 and the Josephson junction 11, an opening is formed in the second insulating material layer 12, and the opening exposes the Josephson junction 11 the top electrode 115; the wiring layer 14 located on the surface of the second insulating material layer 12 and the opening, the wiring layer 14 located in the opening is in contact with the top electrode 115 to form the Conductive vias are used to electrically lead out the top electrode 115 .

However, the stress of the Josephson junction in the existing superconducting circuit structure is difficult to control, and there is a large stress. The existence of large stress can easily cause the leakage current of the Josephson junction, which in turn affects the performance and stability of the superconducting circuit structure. .

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a superconducting circuit structure and a preparation method thereof, which are used to solve the problems in the prior art due to the relatively large stress of the Josephson junction in the superconducting circuit structure. The resulting Josephson junction leakage current is likely to be caused, thereby affecting the performance and stability of the superconducting circuit structure.

In order to achieve the above purpose and other related purposes, the present invention provides a method for preparing a superconducting circuit structure, the method for preparing a superconducting circuit structure at least includes the following steps:

1) providing a substrate, forming a stress pattern structure on the surface of the substrate corresponding to the position where the Josephson junction will be formed later, and the size of the stress pattern structure is larger than the size of the Josephson junction to be formed subsequently;

2) sequentially forming a three-layer film structure of a first superconducting material layer, a first insulating material layer and a second superconducting material layer on the surface of the substrate, the three-layer film structure covering the stress pattern structure;

3) etching the three-layer film structure to form a bottom electrode and a Josephson junction;

4) Form a second insulating material layer on the surface of the structure obtained in step 3), and form a first opening at a position corresponding to the Josephson junction in the second insulating material layer, and the first opening exposes the Josephson junction. Mori knot;

5) Depositing a third superconducting material layer, and etching the third superconducting material layer to form a wiring layer.

As a preferred solution of the preparation method of the superconducting circuit structure of the present invention, in the step 1), part of the substrate is removed by etching, so as to form the stress pattern structure on the surface of the substrate.

As a preferred solution of the preparation method of the superconducting circuit structure of the present invention, in the step 1), a third layer of insulating material is formed on the surface of the substrate, and the third layer of insulating material is etched, so that The stress pattern structure is formed on the surface of the substrate.

As a preferred solution of the preparation method of the superconducting circuit structure of the present invention, in the step 1), a metal layer is formed on the surface of the substrate, and the metal layer is etched to form a metal layer on the surface of the substrate. The stress pattern structure.

As a preferred solution of the preparation method of the superconducting circuit structure of the present invention, in the step 1), the metal layer is etched, and the stress pattern structure and bypass resistors are simultaneously formed on the surface of the substrate, so The bypass resistor is separated from the stress pattern structure by a certain distance.

As a preferred solution of the preparation method of the superconducting circuit structure of the present invention, in the step 1), after forming the stress pattern structure on the surface of the substrate, it also includes forming a stress pattern structure on and around the stress pattern structure. In the step of a fourth insulating material layer, the fourth insulating material layer covers the stress pattern structure.

As a preferred solution of the preparation method of the superconducting circuit structure of the present invention, the step 3) includes the following steps:

31) etching the second superconducting material layer to form the Josephson junction;

32) Etching the first insulating material layer and the first superconducting material layer in sequence to form the bottom electrode.

As a preferred solution of the preparation method of the superconducting circuit structure of the present invention, the step 3) includes the following steps:

31) sequentially etching the second superconducting material layer, the first insulating material layer and the first superconducting material layer to form the bottom electrode;

32) Continue to etch the second superconducting material layer to form the Josephson junction.

As a preferred solution of the preparation method of the superconducting circuit structure of the present invention, between the step 4) and the step 5), it also includes depositing a shunt resistance material layer, and etching the shunt resistance material layer to Steps to form shunt resistors.

As a preferred solution of the preparation method of the superconducting circuit structure of the present invention, after forming the shunt resistance, it also includes depositing a fifth insulating material layer, and after the fifth insulating material layer corresponds to the shunt resistance A second opening is formed at a position where the bypass resistor is exposed.

The present invention also provides a superconducting circuit structure, the superconducting circuit structure comprising:

Substrate;

a stress pattern structure located on the surface of the substrate;

Josephson junction, the Josephson junction includes a bottom electrode, a first insulating material layer and a top electrode, the bottom electrode is located on the top and both sides of the stress pattern structure, and the first insulating material layer is located on the bottom electrode The top electrode is located on the surface of the first insulating material layer above the stress pattern structure, and the size of the top electrode is smaller than the size of the stress pattern structure.

As a preferred solution of the superconducting circuit structure of the present invention, the stress pattern structure is a single-layer, double-layer or multi-layer semiconductor material layer, insulating material layer or metal material layer.

As a preferred solution of the superconducting circuit structure of the present invention, when the material of the stress pattern structure is a single-layer, double-layer or multi-layer metal material layer or a semiconductor material layer, the superconducting circuit structure also includes a first insulating An isolation layer, the first insulating isolation layer covers the stress pattern structure.

As a preferred solution of the superconducting circuit structure of the present invention, the superconducting circuit structure further includes:

The second insulating material layer covers the surface of the substrate and the first insulating material layer, the second insulating material layer is provided with a first opening corresponding to the position of the top electrode, and the first opening exposes the top electrode;

The wiring layer is located on the surface of the second insulating material layer and in the first opening, and is in contact with the top electrode.

As a preferred solution of the superconducting circuit structure of the present invention, the superconducting circuit structure further includes a shunt resistor, the shunt resistor is located between the bottom electrode and the substrate, and is connected to the stress pattern The structures are spaced apart by a certain spacing.

As a preferred solution of the superconducting circuit structure of the present invention, the superconducting circuit structure further includes a shunt resistor, and the shunt resistor is located on the surface of the first insulating material layer or the first The surface of the superconducting material layer is separated from the stress pattern structure by a certain distance; the upper surface of the shunt resistor is in contact with the wiring layer.

As a preferred solution of the superconducting circuit structure of the present invention, the superconducting circuit structure further includes a second insulating isolation layer, the second insulating isolation layer is located on the surface of the shunt resistor, and the second insulating The isolation layer is provided with a second opening corresponding to a position in contact with the wiring layer, and the second opening exposes the shunt resistor.

As mentioned above, the superconducting circuit structure and its preparation method of the present invention have the following beneficial effects:

The superconducting circuit structure and its preparation method of the present invention form a stress pattern structure with a size larger than that of the Josephson junction on the substrate surface below the Josephson junction, which is conducive to the effective release of stress in the Josephson junction, and finally achieves the goal of reducing stress role, thereby solving the Josephson junction leakage current caused by stress, and improving the performance and stability of the superconducting circuit structure.

Description of drawings

FIG. 1 is a schematic diagram showing the structure of a Josephson junction in the prior art.

FIG. 2 is a partial top view structural schematic diagram of a superconducting circuit structure in the prior art.

FIG. 3 is a schematic diagram of a partial cross-sectional structure of a superconducting circuit structure in the prior art.

FIG. 4 is a schematic diagram showing the preparation process of the superconducting circuit structure of the present invention.

FIG. 5 to FIG. 12 show the cross-sectional structure schematic diagrams presented in each step of the method for preparing the superconducting circuit structure of the present invention.

FIG. 13 is a partial top view structural schematic diagram of the superconducting circuit structure of the present invention.

Component designation description

10 substrates

11 Josephson knot

111 first superconducting material layer

112 first insulating material layer

113 second superconducting material layer

114 bottom electrode

115 top electrode

12 second insulating material layer

13 Conductive vias

14 wiring layer

20 substrates

21 Stress Pattern Structure

22 Josephson knot

221 first superconducting material layer

222 first insulating material layer

223 second superconducting material layer

224 bottom electrode

225 top electrode

23 second insulating material layer

24 first opening

25 wiring layer

Steps S1～S5

detailed description

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figure 4 to Figure 13. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic concept of the present invention, although only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

Embodiment one

Please refer to FIG. 4, the present invention provides a method for preparing a superconducting circuit structure, the method for preparing a superconducting circuit structure at least includes the following steps:

1) providing a substrate, forming a stress pattern structure on the surface of the substrate corresponding to the position where the Josephson junction will be formed later, and the size of the stress pattern structure is larger than the size of the Josephson junction to be formed subsequently;

2) sequentially forming a three-layer film structure of a first superconducting material layer, a first insulating material layer and a second superconducting material layer on the surface of the substrate, the three-layer film structure covering the stress pattern structure;

3) etching the three-layer film structure to form a bottom electrode and a Josephson junction;

4) Form a second insulating material layer on the surface of the structure obtained in step 3), and form a first opening at a position corresponding to the Josephson junction in the second insulating material layer, and the first opening exposes the Josephson junction. Mori knot;

5) Depositing a third superconducting material layer, and etching the third superconducting material layer to form a wiring layer.

In step 1), referring to step S1 in FIG. 4 and FIG. 5, a substrate 20 is provided, and a stress pattern structure 21 is formed on the surface of the substrate 20 corresponding to the position where the Josephson junction is to be formed subsequently. The stress pattern The size of the structure 21 is larger than the size of the Josephson junction to be formed later.

As an example, the thickness of the substrate 20 may be, but not limited to, 0.2 mm to 0.8 mm. In this embodiment, the substrate 20 may be silicon dioxide on monocrystalline silicon, wherein the thickness of the monocrystalline silicon wafer is 0.625mm, the silicon dioxide thickness above is 300nm. The material of the substrate 20 is not limited to the materials listed in this embodiment, and may also include but not limited to single crystal silicon, sapphire, silicon carbide, magnesium oxide, and magnesium fluoride.

As an example, the shape of the stress pattern structure 21 can be set according to actual needs. In this embodiment, the cross-sectional shape of the stress pattern structure 21 is a square as an example, but it is not limited thereto. The stress The cross-sectional shape of the pattern structure 21 may also be a rectangle, a circle, an ellipse, and the like.

As an example, the center of the stress pattern structure 21 corresponds up and down to the center of the Josephson junction to be formed later, and the size and area of the stress pattern structure 21 are larger than the size and area of the Josephson junction to be formed later. It should be noted that, as can be seen from the subsequent preparation steps, the size of the Josephson junction is determined by the size of the top electrode to be formed later, therefore, the center of the stress pattern structure 21 corresponds up and down to the center of the top electrode to be formed later, Moreover, the size and area of the stress pattern structure 21 are larger than the size and area of the top electrode to be formed later.

In an example, part of the substrate 20 is removed by etching to form the stress pattern structure 21 on the surface of the substrate 20 .

In another example, a layer of third insulating material layer (not shown) is first formed on the surface of the substrate 20, and then the third insulating material layer is etched by photolithography and etching processes, so that the The stress pattern structure 21 is formed on the surface of the substrate 20 .

In yet another example, a metal layer (not shown) is first formed on the surface of the substrate 20, and then the metal layer is etched by photolithography and etching processes to form the metal layer on the surface of the substrate 20. The stress pattern structure 21 described above. The metal layer can be a superconducting metal layer or a non-superconducting metal layer.

As an example, when the stress pattern structure 21 is a structure formed by etching a metal layer, after forming the stress pattern structure on the surface of the substrate 20, it also includes forming Step of a fourth insulating material layer (not shown), the fourth insulating material layer covers the stress pattern structure 21 .

In step 2), referring to step S2 in FIG. 4 and FIG. 6, the first superconducting material layer 221, the first insulating material layer 222 and the second superconducting material layer 223 are sequentially formed on the surface of the substrate 20. A three-layer film structure, the three-layer film structure covers the stress pattern structure 21 .

As an example, the first superconducting material layer 221 is subsequently used to form a bottom electrode, and the second superconducting material layer 223 is subsequently used to form a top electrode, forming a superconducting tunnel junction with the first insulating material layer 222, The thickness of the first superconducting material layer 221 may be 50nm-200nm, the thickness of the first insulating material layer 222 may be 1nm-15nm, and the thickness of the second superconducting material layer 223 may be 50nm-200nm, The material of the first superconducting material layer 221 and the second superconducting material layer 223 includes but not limited to niobium or niobium nitride, and the material of the first insulating material layer 222 includes but not limited to aluminum oxide or niobium nitride. aluminum. In this embodiment, the thickness of the first superconducting material layer 221 and the second superconducting material layer 223 is 150 nm, and the material is niobium (niobium, Nb); the thickness of the first insulating material layer 222 is 10nm, the material is alumina. The three-layer film structure is sequentially prepared by magnetron sputtering.

In step 3), referring to step S3 in FIG. 4 and FIGS. 7 to 10 , the three-layer film structure is etched to form the bottom electrode 224 and the Josephson junction 22 .

In an example, the step 3) includes the following steps:

31) Etching the second superconducting material layer 223 to form the Josephson junction 22; specifically, first define the pattern of the top electrode 225 through a photolithography process, and then etch the second superconducting material layer through an etching process. conductive material layer 223 to form the top electrode 225, the top electrode 225 forms a Josephson junction 22 with the first insulating material layer 222 and the first superconducting material layer 221, as shown in FIG. 7;

32) sequentially etching the first insulating material layer 222 and the first superconducting material layer 221 to form the bottom electrode 224; specifically, first define the pattern of the bottom electrode 224 through a photolithography process, and then The first insulating material layer 222 and the first superconducting material layer 221 are sequentially etched by an etching process to form the bottom electrode 224 , as shown in FIG. 8 .

In another example, said step 3) includes the following steps:

31) Etching the second superconducting material layer 223, the first insulating material layer 222 and the first superconducting material layer 221 in sequence to form the bottom electrode 224; Figure out the pattern of the bottom electrode 224, and then sequentially etch the second superconducting material layer 223, the first insulating material layer 222 and the first superconducting material layer 221 through an etching process to form the bottom electrode 224. Electrode 224, as shown in Figure 9;

32) Continue to etch the second superconducting material layer 223 to form the Josephson junction 22; specifically, first define the pattern of the top electrode 225 through a photolithography process, and then etch the second superconducting material layer through an etching process. The superconducting material layer 223 is used to form the top electrode 225 , and the top electrode 225 forms a Josephson junction 22 with the first insulating material layer 222 and the bottom electrode 224 , as shown in FIG. 10 .

In step 4), referring to step S4 in FIG. 4 and FIG. 11, a second insulating material layer 23 is formed on the surface of the structure obtained in step 3), and the second insulating material layer 23 corresponds to the Josephson The location of the junction 22 forms a first opening 24 exposing the Josephson junction 22 .

As an example, methods such as plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition or resistance evaporation can be used to form the second insulating material layer 23 on the surface of the structure obtained in step 3).

As an example, the first opening 24 is formed at the position of the second insulating material layer 23 corresponding to the Josephson junction 22 through a photolithography process; specifically, the first opening 24 is first defined through a photolithography process. The position and pattern of the opening 24, and then the second insulating material layer 23 is etched by an etching process to form the first opening 24.

As an example, the first opening 24 may also be formed above the Josephson junction 22 using a lift-off method.

As an example, after the step 4), a step of depositing a shunt resistance material layer (not shown) and etching the shunt resistance material layer to form a shunt resistance (not shown) is also included. The shunt resistor is located on the surface of the first insulating material layer 222 or the first superconducting material layer 221 on one side of the substrate 20 , and is separated from the stress pattern structure 21 by a certain distance.

As an example, after forming the shunt resistor, it also includes depositing a fifth insulating material layer (not shown), and forming a second opening (not shown) at the position of the fifth insulating material layer corresponding to the shunt resistor. Out), the second opening exposes the shunt resistor.

In step 5), please refer to step S5 in FIG. 4 and FIG. 12 to FIG. 13. FIG. 12 is a schematic diagram of a cross-sectional structure presented in this step, and FIG. 13 is a schematic diagram of a top view structure of a structure obtained in this step. conducting material layer (not shown), and etching the third superconducting material layer to form the wiring layer 25 .

As an example, the thickness of the third superconducting material layer may be 300-500 nm. In this embodiment, the material of the third superconducting material layer is niobium, and the thickness thereof is 400 nm. The wiring layer 5 is located on the surface of the second insulating material layer 23, the surface of the top electrode 225 in the first opening 24, and the surface of the shunt resistor, and is suitable for connecting the top electrode 225 And the bypass resistor is electrically drawn out.

It should be noted that in the actual process, each structure in FIG. 13 is an opaque structure. In order to facilitate the display of each structure and the positional relationship between them, FIG. 13 is intentionally shown as a transparent structure.

Embodiment two

In this embodiment, a method for preparing a superconducting circuit structure is also provided. The method for preparing the superconducting circuit structure in this embodiment is roughly the same as the method for preparing the superconducting circuit structure described in Embodiment 1. The difference is: in the first embodiment, after step 4), a shunt resistor is formed on the surface of the first insulating material layer 222 on the side of the substrate 20; while in this embodiment, in step 1), a bypass resistor is formed. Simultaneously with the stress pattern 21, a bypass resistor is formed on the surface of the substrate 20, the bypass resistor is located between the bottom electrode 224 and the substrate 20, and is separated from the stress pattern structure 21 by a certain distance. Pitch.

Embodiment Three

Please continue to refer to Figure 12 and Figure 13, the present invention also provides a superconducting circuit structure, the superconducting circuit structure is prepared by the preparation method described in Example 1 or Example 2, the superconducting circuit structure Including: substrate 20; stress pattern structure 21, the stress pattern structure 21 is located on the surface of the substrate 20; Josephson junction 22, the Josephson junction 22 includes a bottom electrode 224, a first insulating material layer 222 and a top electrode 225, the bottom electrode 224 is located on the top and both sides of the stress pattern structure 21, the first insulating material layer 222 is located on the surface of the bottom electrode 224, and the top electrode 225 is located above the stress pattern structure 21 The surface of the first insulating material layer 222 , and the size of the top electrode 225 is smaller than the size of the stress pattern structure 21 .

As an example, the shape of the stress pattern structure 21 and the top electrode 225 can be set according to actual needs. In this embodiment, the cross-sectional shape of the stress pattern structure 21 and the top electrode 225 is a square as an example. , but not limited thereto, the cross-sectional shape of the stress pattern structure 21 and the top electrode 225 can also be rectangular, circular, oval, etc.

As an example, the center of the top electrode 225 corresponds up and down to the center of the stress pattern structure 21 , and the size and area of the top electrode 225 are smaller than the size and area of the stress pattern structure 21 .

As an example, the material of the stress pattern structure 21 is a single layer, double or multiple layers of semiconductor material, insulating material or metal material.

As an example, when the stress pattern structure 21 is a single-layer, double-layer or multi-layer metal material layer or semiconductor material layer, the superconducting circuit structure further includes a first insulating isolation layer (not shown), and the first The insulating isolation layer covers the stress pattern structure 21 . The first insulating isolation layer corresponds to the fourth insulating material layer described in the first embodiment or the second embodiment.

As an example, the superconducting circuit structure further includes: a second insulating material layer 23, the second insulating material layer 23 covers the surface of the substrate 20 and the first insulating material layer 222, the second insulating The material layer 23 is provided with a first opening 24 corresponding to the position of the top electrode 225, and the first opening 24 exposes the top electrode 225; a wiring layer 25, and the wiring layer 25 is located in the second insulation The surface of the material layer 23 and the inside of the first opening 24 are in contact with the top electrode 225 .

In an example, the superconducting circuit structure further includes a shunt resistor (not shown), the shunt resistor is located between the bottom electrode 224 and the substrate 20, and is connected to the stress pattern structure 21 separated by a certain distance.

In another example, the superconducting circuit structure further includes a shunt resistor (not shown), and the shunt resistor is located on the surface of the first insulating material layer 222 on the side of the substrate 20 or the first superconducting The surface of the conductive material layer is separated from the stress pattern structure 21 by a certain distance; the upper surface of the shunt resistor is in contact with the wiring layer 25 .

As an example, the superconducting circuit structure further includes a second insulating isolation layer (not shown), the second insulating isolation layer is located on the surface of the shunt resistor, and the second insulating isolation layer corresponds to the A second opening (not shown) is provided at the position where the wiring layer 25 contacts, and the second opening exposes the shunt resistor. The second insulating isolation layer is the fifth insulating material layer described in Embodiment 1 or Embodiment 2.

In summary, the present invention provides a superconducting circuit structure and its preparation method, the preparation method of the superconducting circuit structure at least includes the following steps: 1) providing a substrate, on the surface of the substrate corresponding to the following to be formed The position of the Josephson junction forms a stress pattern structure, and the size of the stress pattern structure is larger than the size of the Josephson junction to be formed subsequently; 2) sequentially forming a first superconducting material layer and a first insulating material layer on the surface of the substrate and a three-layer film structure of the second superconducting material layer, the three-layer film structure covers the stress pattern structure; 3) etching the three-layer film structure to form a bottom electrode and a Josephson junction; 4) in the step 3) forming a second insulating material layer on the surface of the obtained structure, and forming a first opening at a position of the second insulating material layer corresponding to the Josephson junction, the first opening exposing the Josephson junction; 5 ) depositing a third superconducting material layer, and etching the third superconducting material layer to form a wiring layer. The superconducting circuit structure and its preparation method of the present invention form a stress pattern structure with a size larger than that of the Josephson junction on the substrate surface below the Josephson junction, which is conducive to the effective release of stress in the Josephson junction, and finally achieves the goal of reducing stress role, thereby solving the Josephson junction leakage current caused by stress, and improving the performance and stability of the superconducting circuit structure.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (17)

1. the preparation method of a superconducting circuit structure, it is characterised in that the preparation method of described superconducting circuit structure comprises the following steps:

1) provide substrate, form stress pattern structure, the size being sized larger than the follow-up Josephson junction to be formed of described stress pattern structure at described substrate surface corresponding to the follow-up position forming Josephson junction;

2) sequentially form the three-layer thin-film structure of the first superconducting material, the first insulation material layer and the second superconducting material at described substrate surface, described three-layer thin-film structure is coated with described stress pattern structure;

3) described three-layer thin-film structure is etched to form hearth electrode and Josephson junction;

4) in step 3) body structure surface that obtains forms the second insulation material layer, and form the first opening at described second insulation material layer corresponding to the position of described Josephson junction, described first opening exposes described Josephson junction;

5) deposition the 3rd superconducting material, and etch described 3rd superconducting material formation wiring layer.

2. the preparation method of superconducting circuit structure according to claim 1, it is characterised in that: described step 1) in, etching removes the described substrate of part, to form described stress pattern structure at described substrate surface.

3. the preparation method of superconducting circuit structure according to claim 1, it is characterized in that: described step 1) in, form the 3rd insulation material layer at described substrate surface, and etch described 3rd insulation material layer, to form described stress pattern structure at described substrate surface.

4. the preparation method of superconducting circuit structure according to claim 1, it is characterised in that: described step 1) in, form metal level at described substrate surface, and etch described metal level, to form described stress pattern structure at described substrate surface.

5. the preparation method of superconducting circuit structure according to claim 4, it is characterized in that: described step 1) in, etch described metal level, concurrently form described stress pattern structure and bypass resistance at described substrate surface, described bypass resistance and described stress pattern structure are separated by certain spacing.

6. the preparation method of superconducting circuit structure according to claim 4, it is characterized in that: described step 1) in, after described substrate surface forms described stress pattern structure, being additionally included in described stress pattern body structure surface and around form the step of the 4th insulation material layer, described 4th insulation material layer is coated with described stress pattern structure.

7. the preparation method of superconducting circuit structure according to claim 1, it is characterised in that: described step 3) comprise the following steps:

31) described second superconducting material is etched to form described Josephson junction;

32) described first insulation material layer and described first superconducting material it are sequentially etched to form described hearth electrode.

8. the preparation method of superconducting circuit structure according to claim 1, it is characterised in that: described step 3) comprise the following steps:

31) described second superconducting material, described first insulation material layer and described first superconducting material it are sequentially etched to form described hearth electrode;

32) continue to etch described second superconducting material to form described Josephson junction.

9. the preparation method of the superconducting circuit structure according to claim 1,2,3,4,6,7 or 8, it is characterized in that: described step 4) and described step 5) between also include deposition bypass resistance material layer, and etch described bypass resistance material layer to form the step of bypass resistance.

10. the preparation method of superconducting circuit structure according to claim 9, it is characterized in that: after forming described bypass resistance, also include deposition the 5th insulation material layer, and forming the second opening at described 5th insulation material layer corresponding to the position of described bypass resistance, described second opening exposes described bypass resistance.

11. a superconducting circuit structure, it is characterised in that described superconducting circuit structure includes:

Substrate;

Stress pattern structure, is positioned at described substrate surface;

Josephson junction, described Josephson junction includes hearth electrode, the first insulation material layer and top electrode, described hearth electrode is positioned at top and the both sides of described stress pattern structure, described first insulation material layer is positioned at described hearth electrode surface, described top electrode is positioned at the described first insulation material layer surface of the top of described stress pattern structure and the size being smaller in size than described stress pattern structure of described top electrode.

12. superconducting circuit structure according to claim 11, it is characterised in that: described stress pattern structure is monolayer, bilayer or multi-lager semiconductor material layer, insulation material layer or metal material layer.

13. superconducting circuit structure according to claim 12, it is characterized in that: when the material of described stress pattern structure is monolayer, bilayer or multiple layer metal material layer or semiconductor material layer, described superconducting circuit structure also includes the first dielectric isolation layer, and described first dielectric isolation layer is coated with described stress pattern structure.

14. superconducting circuit structure according to claim 11, it is characterised in that: described superconducting circuit structure also includes:

Second insulation material layer, is covered in described substrate and described first insulation material layer surface, and described second insulation material layer is provided with the first opening corresponding to the position of described top electrode, and described first opening exposes described top electrode;

Wiring layer, is positioned at described second insulation material layer surface and described first opening, and contacts with described top electrode.

15. superconducting circuit structure according to claim 14, it is characterised in that: described superconducting circuit structure also includes bypass resistance, and described bypass resistance is between described hearth electrode and described substrate, and is separated by certain spacing with described stress pattern structure.

16. superconducting circuit structure according to claim 14, it is characterized in that: described superconducting circuit structure also includes bypass resistance, described bypass resistance is positioned at described first insulation material layer of described substrate side or described first superconducting material surface, and is separated by certain spacing with described stress pattern structure; The upper surface of described bypass resistance contacts with described wiring layer.

17. superconducting circuit structure according to claim 16, it is characterized in that: described superconducting circuit structure also includes the second dielectric isolation layer, described second dielectric isolation layer is positioned at the surface of described bypass resistance, and described second dielectric isolation layer is provided with the second opening corresponding to the position contacted with described wiring layer, described second opening exposes described bypass resistance.