CN105630067A - A high-precision clock detection method based on FPGA - Google Patents

Abstract

The invention discloses a high-precision clock detection method based on FPGA (field programmable gate array), and relates to a clock detection method. The invention can obviously improve the time control precision of realizing the 1588 function in the FPGA.

Description

A high-precision clock detection method based on FPGA

technical field

The invention relates to a clock detection method, in particular to an FPGA-based high-precision clock detection method.

Background technique

1588 has nanosecond-level accuracy, short information, less bandwidth resources, low overall cost, and high reliability. Therefore, the society is currently actively promoting the development and application of the 1588 protocol.

At present, the FPGA-based 1588 clock solution mainly has the following characteristics:

1. Directly use the local clock to directly detect clock events (message arrival or departure);

2. The clock (Timer) is maintained by simple counter logic;

Disadvantages of existing technology:

1. The accuracy of detecting clock time (message arrival or departure) is low, which directly affects the accuracy of time synchronization;

2. The clock is maintained by simple technical logic, with low control precision and large errors.

Contents of the invention

In view of the above-mentioned defects in the prior art, the technical problem to be solved by the present invention is to provide a method for improving the detection accuracy of clock events.

In order to achieve the above object, the present invention provides a high-precision clock detection method based on FPGA, which generates multiple clock signals with different phases in one clock cycle, and determines the phase relationship between the measured signal and each clock signal by judging the phase relationship between the measured signal and each clock signal. signal occurrence time;

The system master clock generates n phase clock signals, n is a positive integer; the arrival of the clock event is represented by a rising edge pulse; the clock input terminal of the D flip-flop receives the clock signal as the data input signal of the D flip-flop; the clock The signal divides a system clock cycle into n regions, and then determines the occurrence region of the clock event.

Preferably, the determination of the occurrence area of the clock event is carried out according to the following steps: when the clock event signal arrives, the D flip-flop will latch and output each phase clock signal, and output a 4-bit encoded value; according to the decoding mapping table, determine the occurrence of the event area.

The beneficial effect of the present invention is: the present invention can obviously improve the time control precision of realizing 1588 function in FPGA.

Description of drawings

Fig. 1 is the structural block diagram of polyphase detection of the present invention;

Figure 2 is a schematic diagram of multi-phase detection.

detailed description

Below in conjunction with accompanying drawing and embodiment the present invention will be further described:

As shown in Figure 1 and Figure 2, an FPGA-based high-precision clock detection method is characterized in that: multiple clock signals with different phases are generated within one clock cycle, and the phase relationship between the measured signal and each clock signal is judged , to determine the occurrence time of the signal under test;

The system master clock generates n phase clock signals, where n is a positive integer. In this embodiment, four phase clock signals are generated with a phase interval of 90 degrees. The arrival of the time event is represented by a rising edge pulse (if it is represented by the rising edge signal of the SOF signal of the message, this signal will be used as the clock signal of the D flip-flop), which will be sent to the clock input of the D flip-flop; 4 The clock signal of the phase is used as the data input signal of the D flip-flop. The four-phase clock signal divides a system clock cycle into four regions, and since the present invention can judge the occurrence region of an event, the accuracy of event detection will theoretically be increased by four times.

The occurrence region of the described judgment clock event is carried out according to the following steps: when the clock event signal arrives (SOF), the D flip-flop will latch and output each phase clock signal, and output a 4-bit encoded value to the decoder; according to the decoding mapping table, determine The area where the incident occurred. To illustrate this embodiment, the system clock is set to 125 MHz (period 8 ns). It can be seen from Table 1 that the judgment accuracy of event arrival time can be increased from 8 ns to 2 ns without considering the influence of other factors.

Table 1. Event decoding time mapping table

The preferred specific embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make many modifications and changes according to the concept of the present invention without creative efforts. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning or limited experiments on the basis of the prior art shall be within the scope of protection defined by the claims.

Claims (2)

1. A high-precision clock detection method based on FPGA, characterized in that: a plurality of clock signals with different phases are produced in one clock cycle, and by judging the phase relationship between the measured signal and each clock signal, the time of occurrence of the measured signal is determined ; The system master clock generates n phase clock signals, n is a positive integer; the arrival of the clock event is represented by a rising edge pulse; the clock input terminal of the D flip-flop receives the clock signal as the data input signal of the D flip-flop; the clock The signal divides a system clock cycle into n regions, and then determines the occurrence region of the clock event. 2. a kind of high-precision clock detection method based on FPGA as claimed in claim 1, is characterized in that: The determination of the occurrence area of the clock event is carried out according to the following steps: when the clock event signal arrives, the D flip-flop will latch and output each phase clock signal, and output a 4-bit encoded value; determine the event occurrence area according to the decoding mapping table.